WO2020124669A1 - Level shifter and signal conversion method - Google Patents
Level shifter and signal conversion method Download PDFInfo
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- WO2020124669A1 WO2020124669A1 PCT/CN2018/124527 CN2018124527W WO2020124669A1 WO 2020124669 A1 WO2020124669 A1 WO 2020124669A1 CN 2018124527 W CN2018124527 W CN 2018124527W WO 2020124669 A1 WO2020124669 A1 WO 2020124669A1
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
Definitions
- the invention relates to the field of display technology, and in particular to a level conversion module and a signal conversion method.
- liquid crystal display Liquid Crystal Display
- LCD Liquid Crystal Display
- other flat display devices are widely used in mobile phones, TVs, etc. due to their advantages of high image quality, power saving, thin body and wide range of applications.
- Various consumer electronic products such as personal digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream in display devices.
- each pixel is electrically connected to a thin film transistor (TFT), the gate of the thin film transistor is connected to the horizontal scanning line, and the source is connected to the vertical data line and the drain ( Drain) is connected to the pixel electrode.
- TFT thin film transistor
- the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly completed by an external integrated circuit (Integrated Circuit, IC).
- the external IC can control the charging and discharging of the horizontal scanning lines at all levels.
- the GOA technology (Gate Driver on Array) is the array substrate row driving technology, which can use the array manufacturing process of the liquid crystal display panel to make the gate driving circuit on the TFT array substrate to realize the progressive scanning of the gate.
- the GOA circuit generally needs to access several clock signals and start signals in order to realize the function of progressive scanning of its gate.
- a timing controller (Tcon) is usually used to output an original clock signal and an original start signal and transmit it to a level shifter, and the level shifter performs boosting to generate an output clock signal and an output start The signal is output to the GOA circuit of the liquid crystal display panel.
- the first output clock signal CLKout1, the second output clock after the rising edge of the output start signal STVout passes 1/2 times the high level duration of the output start signal STVout
- the first rising edge of the signal CLKout2, the third output clock signal CLKout3 and the fourth output clock signal CLKout4 are generated in sequence, the first output clock signal CLKout1, the second output clock signal CLKout2, the third output clock signal CLKout3 and the fourth output clock
- the first rising edge of the signal CLKout4 differs by 1/2 times the high-level duration of the output start signal STVout, and the falling edge of the output start signal STVout when the first rising edge of the second output clock signal CLKout2 arrives arrival.
- the width of the output start signal output by the level conversion module follows the width of the original start signal transmitted by the timing controller, when a large number of output clock signals need to be provided, the original start signal has a serious shortage of width. As a result, the width of the output start signal is seriously insufficient, and the falling edge of the output signal cannot be satisfied to occur at the same time as the rising edge of the N/2th output clock signal, which will cause the GOA to fail and cause reliability problems.
- the object of the present invention is to provide a level conversion module, which can make the high-level width of the output start signal meet the timing requirements.
- Another object of the present invention is to provide a signal conversion method that enables the high-level width of the output start signal to meet timing requirements.
- the present invention first provides a level conversion module, including a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit;
- the clock signal output unit is used to output an output clock signal of N pulses, and the first rising edge of each of the N output clock signals is generated in sequence; where N is a positive even number;
- the input end of the inverter is electrically connected to the clock signal output unit, and the N/2th output clock signal of the N output clock signals is connected, and the output end is electrically connected to the first moving contact of the single-pole double-throw switch;
- the second moving contact of the single-pole double-throw switch is connected to the input start signal, the static contact outputs the intermediate start signal to the start signal output unit, and the control terminal is electrically connected to the static contact;
- the single-pole double-throw switch is at Connect the static contact to the first moving contact when the control terminal is high potential, and connect the static contact to the second moving contact when the control terminal is low potential;
- the rising edge of the input start signal is at N Generated before the first rising edge of the first output clock signal in the output clock signal;
- the start signal output unit is used to generate an output start signal after boosting the intermediate start signal; the high potential period and the low potential period of the output start signal are respectively the same as the high potential of the intermediate start signal The period corresponds to the low-potential period.
- the clock signal output unit is used to electrically connect the timing controller and access N input clock signals provided by the timing controller.
- the clock signal output unit performs boosting processing on the N input clock signals and outputs the output signals and N respectively. N output clock signals corresponding to one input clock signal.
- the high potential period and low potential period of each output clock signal correspond to the corresponding high potential period and low potential period of the input clock signal, respectively.
- the input start signal is provided by the timing controller.
- the period and duty cycle of the N output clock signals are the same.
- the interval between the first rising edges of any two adjacent output clock signals is a preset duration.
- the interval between the first rising edge of the first clock signal and the rising edge of the input start signal in the N output clock signals is the preset duration.
- the output start signal is a preset constant voltage high potential, and the preset constant voltage high potential is greater than the high potential of the intermediate start signal.
- the output start signal is the same low potential as the intermediate start signal.
- the invention also provides a signal conversion method, including the following steps:
- Step S1 Provide the above-mentioned level conversion module
- Step S2 The N/2th output clock signal of the N output clock signals is low potential, the input start signal is low potential, the intermediate start signal and the control end of the single pole double throw switch are low potential, single pole
- the double-throw switch connects the static contact with the second moving contact so that the intermediate start signal and the control end of the single-pole double-throw switch remain low, and the output start signal is low;
- Step S3 The N/2th output clock signal of the N output clock signals is a low potential, the output terminal of the inverter is a high potential, the input start signal becomes a high potential, the intermediate start signal and the single pole The control end of the double-throw switch becomes a high potential, and the single-pole double-throw switch connects the static contact with the first moving contact to keep the intermediate start signal and the control end of the single-pole double-throw switch high, and the output starts
- the signal is a preset constant voltage high potential;
- Step S4 The N/2th output clock signal of the N output clock signals becomes a high potential, the output terminal of the inverter becomes a low potential, the intermediate start signal becomes a low potential, and the output start signal Low potential.
- the level conversion module of the present invention includes a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit.
- the input start signal is used to pull up the output potential of the start signal .
- the rising edge of the output clock signal arrives the falling edge of the output start signal arrives, which can make the high-level width of the output start signal meet the timing requirements, and can ensure the normal operation of the GOA circuit when applied to the GOA circuit.
- the signal conversion method of the present invention can enable the high-level width of the output start signal to meet the timing requirements.
- FIG. 1 is a waveform diagram of the output start signal and the output clock signal of the existing level conversion module
- FIG. 2 is a schematic structural diagram of a level conversion module of the present invention
- the present invention provides a level conversion module, including a clock signal output unit 10 ,inverter 20 , Single pole double throw switch K And start signal output unit 30 .
- the clock signal output unit 10 For output N Output clock signal of one pulse, N The first rising edge of each output clock signal is generated in sequence. among them, N Is a positive even number, for example, it can be 4 , 6 , 8 .
- the N The output clock signal of the pulse is output to the LCD panel GOA Used for control in the circuit GOA The circuit performs progressive scanning.
- the inverter 20 The input of the is electrically connected to the clock signal output unit 10 , Access N Output clock signal N/2 Output clock signal CLKOUT-N/2 , The output is electrically connected to the single pole double throw switch K The first moving contact.
- the single pole double throw switch K The second moving contact is connected to the input start signal STV ,
- the static contact outputs the intermediate start signal STV1 To start signal output unit 30 ,
- the control terminal is electrically connected to the static contact.
- the single pole double throw switch K Connect the static contact to the first moving contact when its control terminal is high potential, and connect the static contact to the second moving contact when its control terminal is low potential; the input start signal STV The rising edge of N Generated before the first rising edge of the first output clock signal in the output clock signal.
- the start signal output unit 30 Used for intermediate start signal STV1
- the output start signal is generated after the boosting process STVOUT .
- the output start signal STVOUT The high potential period and the low potential period of the STV1 Corresponds to the high-potential period and the low-potential period.
- the clock signal output unit 10 Timing controller for electrically connecting the level conversion module 9 , Access by the timing controller 9 which provided N Input clock signal, the clock signal output unit 10 Correct N
- the input clock signal is boosted and the output is N Corresponding to the input clock signal N Output clock signal.
- the high potential period and low potential period of each output clock signal correspond to the corresponding high potential period and low potential period of the input clock signal, respectively.
- the input start signal STV By the timing controller 9 provide.
- N The period and duty cycle of the output clock signal are the same.
- the interval between the first rising edges of any two adjacent output clock signals is a preset duration.
- N The first rising edge of the first clock signal in the output clock signal and the input start signal STV The interval between the rising edges of is the preset duration.
- the output start signal STVOUT Is a preset constant voltage high potential
- the preset constant voltage high potential is greater than the intermediate start signal STV1 High potential.
- the output start signal STVOUT Start signal STV1 The low potential is the same as the low potential.
- N In the initial stage, N Output clock signal N/2 Output clock signal CLKOUT-N/2 Low potential, inverter 20
- the output terminal is high potential, the input start signal STV Is low, the intermediate start signal STV1 And single pole double throw switch K
- the control terminal is low potential, single pole double throw switch K Connect the static contact with the second moving contact so that the intermediate start signal STV1 And single pole double throw switch K
- the control end of the input keeps the start signal STV Low potential, the start signal is output STVOUT Low potential.
- N Output clock signal N/2 Output clock signal CLKOUT-N/2 Keep low, inverter 20
- the output of the input remains high, the input start signal STV Becomes high potential, in the single pole double throw switch K
- the intermediate start signal STV1 And single pole double throw switch K The control terminal of the switch becomes high potential, making the single pole double throw switch K Connect the static contact with the first moving contact, the intermediate start signal STV1 And single pole double throw switch K
- Control terminal of the inverter 20 High potential at the output of the device, at this time, the output start signal STVOUT It is a preset constant voltage high potential.
- the present invention realizes the use of input start signals STV Output start signal STVOUT Pull up so that the start signal is input STV
- the start signal is output when the rising edge of STVOUT The rising edge comes and uses the first N/2 Output clock signal CLKOUT-N/2 Output start signal STVOUT Pull down so that N/2 Output clock signal CLKOUT-N/2
- the start signal is output when the rising edge of STVOUT
- the falling edge of, no matter how many output clock signals, the start signal is output STVOUT Can be kept high until the first N/2 Output clock signal CLKOUT-N/2
- the rising edge of the arrival can make the output start signal STVOUT
- the high level width of meets the timing requirements and is applied to GOA Circuit can guarantee GOA The circuit works normally.
- the present invention also provides a signal conversion method, including the following steps:
- step S1 Please refer to the picture 2
- the above-mentioned level conversion module is provided, and the structure of the level conversion module will not be described repeatedly here.
- step S2 N Output clock signal N/2 Output clock signal CLKOUT-N/2 Low potential, inverter 20
- the output terminal is high potential, the input start signal STV Is low, the intermediate start signal STV1 And single pole double throw switch K
- the control terminal is low potential, single pole double throw switch K Connect the static contact with the second moving contact so that the intermediate start signal STV1 And single pole double throw switch K
- the control end of the input keeps the start signal STV Low potential, the start signal is output STVOUT Low potential.
- step S3 N Output clock signal N/2 Output clock signal CLKOUT-N/2 Keep low, inverter 20
- the output of the input remains high, the input start signal STV Becomes high potential, in the single pole double throw switch K
- the intermediate start signal STV1 And single pole double throw switch K The control terminal of the switch becomes high potential, making the single pole double throw switch K Connect the static contact with the first moving contact, the intermediate start signal STV1 And single pole double throw switch K
- Control terminal of the inverter 20 High potential at the output of the device, at this time, the output start signal STVOUT It is a preset constant voltage high potential.
- step S4 N Output clock signal N/2 Output clock signal CLKOUT-N/2 Go high, inverter 20 The output of the switch becomes low potential, in the single pole double throw switch K When the static contact is still connected to the first moving contact, the intermediate start signal STV1 Goes low, the output start signal STVOUT Low potential.
- the signal conversion method of the present invention using the above-mentioned level conversion module, can realize the use of the input start signal STV Output start signal STVOUT Pull up so that the start signal is input STV
- the start signal is output when the rising edge of STVOUT The rising edge comes and uses the first N/2 Output clock signal CLKOUT-N/2 Output start signal STVOUT Pull down so that N/2 Output clock signal CLKOUT-N/2
- the start signal is output when the rising edge of STVOUT
- the falling edge of, no matter how many output clock signals, the start signal is output STVOUT Can be kept high until the first N/2 Output clock signal CLKOUT-N/2
- the rising edge of the arrival can make the output start signal STVOUT
- the high level width of meets the timing requirements and is applied to GOA Circuit can guarantee GOA The circuit works normally.
- the level conversion module of the present invention includes a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit.
- the input start signal is used to pull up to output the potential of the start signal.
- N/2 N Is an even number
- output clock signal pulls down the potential of the start signal, so that N/2
- the rising edge of the output clock signal arrives, the falling edge of the output start signal arrives, which can make the high-level width of the output start signal meet the timing requirements.
- GOA Circuit can guarantee GOA The circuit works normally.
- the signal conversion method of the present invention can enable the high-level width of the output start signal to meet the timing requirements.
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Abstract
A level shifter and a signal conversion method. The level shifter comprises a clock signal output unit (10), an inverter (20), a single-pole double-throw switch (K) and a start signal output unit. When working, an input start signal (STV) is used to pull up the potential of an output start signal (STVOUT), so that when a rising edge of the input start signal (STV) arrives, a rising edge of the output start signal (STVOUT) arrives. An (N/2)th (N is a positive even number) output clock signal (CLKOUT-N/2) is used to pull down the potential of the output start signal (STVOUT), so that when a rising edge of the (N/2)th output clock signal (CLKOUT-N/2) arrives, a falling edge of the output start signal (STVOUT) arrives. The present invention enables the high-level width of the output start signal (STVOUT) to meet timing requirements, and may guarantee the normal operation of a GOA circuit when applied to the GOA circuit.
Description
本发明涉及显示技术领域，尤其涉及一种电平转换模块及信号转换方法。The invention relates to the field of display technology, and in particular to a level conversion module and a signal conversion method.
随着显示技术的发展，液晶显示装置(Liquid Crystal Display，LCD)等平面显示装置因具有高画质、省电、机身薄及应用范围广等优点，而被广泛地应用于手机、电视、个人数字助理、数字相机、笔记本电脑、台式计算机等各种消费性电子产品，成为显示装置中的主流。With the development of display technology, liquid crystal display (Liquid Crystal Display, LCD) and other flat display devices are widely used in mobile phones, TVs, etc. due to their advantages of high image quality, power saving, thin body and wide range of applications. Various consumer electronic products such as personal digital assistants, digital cameras, notebook computers, and desktop computers have become the mainstream in display devices.
主动式液晶显示装置中，每个像素电性连接一个薄膜晶体管(TFT)，薄膜晶体管的栅极(Gate)连接至水平扫描线，源极(Source)连接至垂直方向的数据线，漏极(Drain)则连接至像素电极。在水平扫描线上施加足够的电压，会使得电性连接至该条水平扫描线上的所有TFT打开，从而数据线上的信号电压能够写入像素，控制液晶的不同透光度进而达到控制色彩与亮度的效果。In an active liquid crystal display device, each pixel is electrically connected to a thin film transistor (TFT), the gate of the thin film transistor is connected to the horizontal scanning line, and the source is connected to the vertical data line and the drain ( Drain) is connected to the pixel electrode. Applying sufficient voltage on the horizontal scanning line will turn on all the TFTs electrically connected to the horizontal scanning line, so that the signal voltage on the data line can be written to the pixels, control the different transmittance of the liquid crystal and thus control the color With brightness effect.
目前主动式液晶显示面板水平扫描线的驱动主要由外接的集成电路板(Integrated Circuit，IC)来完成，外接的IC可以控制各级水平扫描线的逐级充电和放电。而GOA技术(Gate
Driver on Array)即阵列基板行驱动技术，是可以运用液晶显示面板的阵列制程将栅极驱动电路制作在TFT阵列基板上，实现对栅极逐行扫描的驱动方式。GOA电路中一般需要接入若干时钟信号及起始信号，以实现其栅极逐行扫描的功能。现有技术中，通常利用时序控制器(Tcon)输出原始时钟信号及原始起始信号并传输至电平转换模块 (level shifter)，由电平转换模块进行升压产生输出时钟信号及输出起始信号并输出至液晶显示面板的GOA电路中。At present, the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly completed by an external integrated circuit (Integrated Circuit, IC). The external IC can control the charging and discharging of the horizontal scanning lines at all levels. The GOA technology (Gate
Driver on Array) is the array substrate row driving technology, which can use the array manufacturing process of the liquid crystal display panel to make the gate driving circuit on the TFT array substrate to realize the progressive scanning of the gate. The GOA circuit generally needs to access several clock signals and start signals in order to realize the function of progressive scanning of its gate. In the prior art, a timing controller (Tcon) is usually used to output an original clock signal and an original start signal and transmit it to a level shifter, and the level shifter performs boosting to generate an output clock signal and an output start The signal is output to the GOA circuit of the liquid crystal display panel.
目前的电平转换单元输出的输出起始信号的上升沿之后经预设的时长开始依次输出多个输出时钟信号，并且一般需要满足输出起始信号的下降沿与第n/2个输出时钟信号的上升沿同时发生，n为正偶数。请参阅图1，以四条输出时钟信号为例，输出起始信号STVout的上升沿后经过1/2倍的输出起始信号STVout的高电平时长后第一输出时钟信号CLKout1、第二输出时钟信号CLKout2、第三输出时钟信号CLKout3及第四输出时钟信号CLKout4的第一个上升沿依次产生，第一输出时钟信号CLKout1、第二输出时钟信号CLKout2、第三输出时钟信号CLKout3及第四输出时钟信号CLKout4的第一个上升沿之间相差1/2倍的输出起始信号STVout的高电平时长，在第二输出时钟信号CLKout2的第一个上升沿到来时输出起始信号STVout的下降沿到来。由于电平转换模块所输出的输出起始信号的宽度跟随时序控制器传输的原始起始信号的宽度，当需要提供数量较多的输出时钟信号时，原始起始信号存在宽度严重不足的情况，导致输出起始信号的宽度严重不足，无法满足其下降沿与第N/2个输出时钟信号的上升沿同时发生，会导致GOA失效，出现信赖性的问题。After the rising edge of the output start signal output by the current level conversion unit starts to output multiple output clock signals in sequence after a preset duration, and generally needs to satisfy the falling edge of the output start signal and the n/2th output clock signal The rising edges occur simultaneously, n is a positive even number. Please refer to FIG. 1, taking four output clock signals as an example, the first output clock signal CLKout1, the second output clock after the rising edge of the output start signal STVout passes 1/2 times the high level duration of the output start signal STVout The first rising edge of the signal CLKout2, the third output clock signal CLKout3 and the fourth output clock signal CLKout4 are generated in sequence, the first output clock signal CLKout1, the second output clock signal CLKout2, the third output clock signal CLKout3 and the fourth output clock The first rising edge of the signal CLKout4 differs by 1/2 times the high-level duration of the output start signal STVout, and the falling edge of the output start signal STVout when the first rising edge of the second output clock signal CLKout2 arrives arrival. Since the width of the output start signal output by the level conversion module follows the width of the original start signal transmitted by the timing controller, when a large number of output clock signals need to be provided, the original start signal has a serious shortage of width. As a result, the width of the output start signal is seriously insufficient, and the falling edge of the output signal cannot be satisfied to occur at the same time as the rising edge of the N/2th output clock signal, which will cause the GOA to fail and cause reliability problems.
本发明的目的在于提供一种电平转换模块，能够使得输出起始信号的高电平宽度满足时序要求。The object of the present invention is to provide a level conversion module, which can make the high-level width of the output start signal meet the timing requirements.
本发明的另一目的在于提供一种信号转换方法，能够使得输出起始信号的高电平宽度满足时序要求。Another object of the present invention is to provide a signal conversion method that enables the high-level width of the output start signal to meet timing requirements.
为实现上述目的，本发明首先提供一种电平转换模块，包括时钟信号输出单元、反相器、单刀双掷开关及起始信号输出单元；To achieve the above object, the present invention first provides a level conversion module, including a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit;
所述时钟信号输出单元用于输出N条脉冲的输出时钟信号，N条输出时钟信号各自的第一个上升沿依次产生；其中，N为正偶数；The clock signal output unit is used to output an output clock signal of N pulses, and the first rising edge of each of the N output clock signals is generated in sequence; where N is a positive even number;
所述反相器的输入端电性连接时钟信号输出单元，接入N条输出时钟信号中的第N/2条输出时钟信号，输出端电性连接单刀双掷开关的第一动触点；The input end of the inverter is electrically connected to the clock signal output unit, and the N/2th output clock signal of the N output clock signals is connected, and the output end is electrically connected to the first moving contact of the single-pole double-throw switch;
所述单刀双掷开关的第二动触点接入输入起始信号，静触点输出中间起始信号至起始信号输出单元，控制端电性连接静触点；所述单刀双掷开关在其控制端为高电位时将静触点与第一动触点连接，在其控制端为低电位时将静触点与第二动触点连接；所述输入起始信号的上升沿在N条输出时钟信号中的第一条输出时钟信号的第一个上升沿之前产生；The second moving contact of the single-pole double-throw switch is connected to the input start signal, the static contact outputs the intermediate start signal to the start signal output unit, and the control terminal is electrically connected to the static contact; the single-pole double-throw switch is at Connect the static contact to the first moving contact when the control terminal is high potential, and connect the static contact to the second moving contact when the control terminal is low potential; the rising edge of the input start signal is at N Generated before the first rising edge of the first output clock signal in the output clock signal;
所述起始信号输出单元用于对中间起始信号进行升压处理后产生输出起始信号；所述输出起始信号的高电位时段及低电位时段分别与所述中间起始信号的高电位时段及低电位时段相对应。The start signal output unit is used to generate an output start signal after boosting the intermediate start signal; the high potential period and the low potential period of the output start signal are respectively the same as the high potential of the intermediate start signal The period corresponds to the low-potential period.
所述时钟信号输出单元用于电性连接时序控制器，接入由时序控制器提供的N条输入时钟信号，所述时钟信号输出单元对N条输入时钟信号进行升压处理后输出分别与N条输入时钟信号对应的N条输出时钟信号。The clock signal output unit is used to electrically connect the timing controller and access N input clock signals provided by the timing controller. The clock signal output unit performs boosting processing on the N input clock signals and outputs the output signals and N respectively. N output clock signals corresponding to one input clock signal.
每一条输出时钟信号的高电位时段及低电位时段分别与对应的输入时钟信号的高电位时段及低电位时段相对应。The high potential period and low potential period of each output clock signal correspond to the corresponding high potential period and low potential period of the input clock signal, respectively.
所述输入起始信号由所述时序控制器提供。The input start signal is provided by the timing controller.
N条输出时钟信号的周期及占空比均相同。The period and duty cycle of the N output clock signals are the same.
任意两条相邻的输出时钟信号各自的第一个上升沿之间的间隔均为一预设时长。The interval between the first rising edges of any two adjacent output clock signals is a preset duration.
N条输出时钟信号中第一条时钟信号的第一个上升沿与输入起始信号的上升沿之间的间隔为所述预设时长。The interval between the first rising edge of the first clock signal and the rising edge of the input start signal in the N output clock signals is the preset duration.
当中间起始信号为高电位时，所述输出起始信号为预设的恒压高电位，该预设的恒压高电位大于中间起始信号的高电位。When the intermediate start signal is a high potential, the output start signal is a preset constant voltage high potential, and the preset constant voltage high potential is greater than the high potential of the intermediate start signal.
当中间起始信号为低电位时，所述输出起始信号为与中间起始信号的低电位相同的低电位。When the intermediate start signal is low, the output start signal is the same low potential as the intermediate start signal.
本发明还提供一种信号转换方法，包括如下步骤：The invention also provides a signal conversion method, including the following steps:
步骤S1、提供上述的电平转换模块；Step S1: Provide the above-mentioned level conversion module;
步骤S2、N条输出时钟信号中第N/2条输出时钟信号为低电位，所述输入起始信号为低电位，所述中间起始信号及单刀双掷开关的控制端为低电位，单刀双掷开关将静触点与第二动触点连接使得中间起始信号及单刀双掷开关的控制端保持低电位，所述输出起始信号为低电位；Step S2. The N/2th output clock signal of the N output clock signals is low potential, the input start signal is low potential, the intermediate start signal and the control end of the single pole double throw switch are low potential, single pole The double-throw switch connects the static contact with the second moving contact so that the intermediate start signal and the control end of the single-pole double-throw switch remain low, and the output start signal is low;
步骤S3、N条输出时钟信号中第N/2条输出时钟信号为低电位，反相器的输出端为高电位，所述输入起始信号变为高电位，所述中间起始信号及单刀双掷开关的控制端变为高电位，单刀双掷开关将静触点与第一动触点连接使所述中间起始信号及单刀双掷开关的控制端保持高电位，所述输出起始信号为预设的恒压高电位；Step S3. The N/2th output clock signal of the N output clock signals is a low potential, the output terminal of the inverter is a high potential, the input start signal becomes a high potential, the intermediate start signal and the single pole The control end of the double-throw switch becomes a high potential, and the single-pole double-throw switch connects the static contact with the first moving contact to keep the intermediate start signal and the control end of the single-pole double-throw switch high, and the output starts The signal is a preset constant voltage high potential;
步骤S4、N条输出时钟信号中第N/2条输出时钟信号变为高电位，反相器的输出端变为低电位，所述中间起始信号变为低电位，所述输出起始信号为低电位。Step S4. The N/2th output clock signal of the N output clock signals becomes a high potential, the output terminal of the inverter becomes a low potential, the intermediate start signal becomes a low potential, and the output start signal Low potential.
本发明的有益效果：本发明的电平转换模块包括时钟信号输出单元、反相器、单刀双掷开关及起始信号输出单元，工作时，利用输入起始信号上拉输出起始信号的电位，使得输入起始信号的上升沿到来时输出起始信号的上升沿到来，利用第N/2（N为正偶数）条输出时钟信号下拉输出起始信号的电位，使得在第N/2条输出时钟信号的上升沿到来时输出起始信号的下降沿到来，能够使得输出起始信号的高电平宽度满足时序要求，应用于GOA电路时能够保证GOA电路正常工作。本发明的信号转换方法能够使得输出起始信号的高电平宽度满足时序要求。Beneficial effect of the present invention: The level conversion module of the present invention includes a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit. When working, the input start signal is used to pull up the output potential of the start signal , Make the rising edge of the output start signal come when the rising edge of the input start signal arrives, use the N/2 (N is positive even) output clock signal to pull down the potential of the start signal, so that the N/2 When the rising edge of the output clock signal arrives, the falling edge of the output start signal arrives, which can make the high-level width of the output start signal meet the timing requirements, and can ensure the normal operation of the GOA circuit when applied to the GOA circuit. The signal conversion method of the present invention can enable the high-level width of the output start signal to meet the timing requirements.
为了能更进一步了解本发明的特征以及技术内容，请参阅以下有关本发明的详细说明与附图，然而附图仅提供参考与说明用，并非用来对本发明加以限制。In order to further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings are provided for reference and explanation only, and are not intended to limit the present invention.
附图中，In the drawings,
图1为现有的电平转换模块的输出起始信号及输出时钟信号的波形图；FIG. 1 is a waveform diagram of the output start signal and the output clock signal of the existing level conversion module;
图2为本发明的电平转换模块的结构示意图；2 is a schematic structural diagram of a level conversion module of the present invention;
图3为本发明的信号转换方法的流程图；3 is a flowchart of the signal conversion method of the present invention;
图4为本发明的信号转换方法的时序图。4 is a timing diagram of the signal conversion method of the present invention.
为更进一步阐述本发明所采取的技术手段及其效果，以下结合本发明的优选实施例及其附图进行详细描述。In order to further elaborate on the technical means and effects adopted by the present invention, the following will describe in detail with reference to the preferred embodiments of the present invention and the accompanying drawings.
请参阅图Please refer to the picture
22
，本发明提供一种电平转换模块，包括时钟信号输出单元, The present invention provides a level conversion module, including a clock signal output unit
1010
、反相器,inverter
2020
、单刀双掷开关, Single pole double throw switch
KK
及起始信号输出单元And start signal output unit
3030
。.
所述时钟信号输出单元The clock signal output unit
1010
用于输出For output
NN
条脉冲的输出时钟信号，Output clock signal of one pulse,
NN
条输出时钟信号各自的第一个上升沿依次产生。其中，The first rising edge of each output clock signal is generated in sequence. among them,
NN
为正偶数，例如，可以为Is a positive even number, for example, it can be
44
、,
66
、,
88
。该. The
NN
条脉冲的输出时钟信号输出至液晶显示面板的The output clock signal of the pulse is output to the LCD panel
GOAGOA
电路中用于控制Used for control in the circuit
GOAGOA
电路进行逐行扫描。The circuit performs progressive scanning.
所述反相器The inverter
2020
的输入端电性连接时钟信号输出单元The input of the is electrically connected to the clock signal output unit
1010
，接入, Access
NN
条输出时钟信号中的第Output clock signal
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
，输出端电性连接单刀双掷开关, The output is electrically connected to the single pole double throw switch
KK
的第一动触点。所述单刀双掷开关The first moving contact. The single pole double throw switch
KK
的第二动触点接入输入起始信号The second moving contact is connected to the input start signal
STVSTV
，静触点输出中间起始信号, The static contact outputs the intermediate start signal
STV1STV1
至起始信号输出单元To start signal output unit
3030
，控制端电性连接静触点。所述单刀双掷开关, The control terminal is electrically connected to the static contact. The single pole double throw switch
KK
在其控制端为高电位时将静触点与第一动触点连接，在其控制端为低电位时将静触点与第二动触点连接；所述输入起始信号Connect the static contact to the first moving contact when its control terminal is high potential, and connect the static contact to the second moving contact when its control terminal is low potential; the input start signal
STVSTV
的上升沿在The rising edge of
NN
条输出时钟信号中的第一条输出时钟信号的第一个上升沿之前产生。所述起始信号输出单元Generated before the first rising edge of the first output clock signal in the output clock signal. The start signal output unit
3030
用于对中间起始信号Used for intermediate start signal
STV1STV1
进行升压处理后产生输出起始信号The output start signal is generated after the boosting process
STVOUTSTVOUT
。所述输出起始信号. The output start signal
STVOUTSTVOUT
的高电位时段及低电位时段分别与所述中间起始信号The high potential period and the low potential period of the
STV1STV1
的高电位时段及低电位时段相对应。Corresponds to the high-potential period and the low-potential period.
具体地，所述时钟信号输出单元Specifically, the clock signal output unit
1010
用于电性连接电平转换模块外部的时序控制器Timing controller for electrically connecting the level conversion module
99
，接入由时序控制器, Access by the timing controller
99
提供的which provided
NN
条输入时钟信号，所述时钟信号输出单元Input clock signal, the clock signal output unit
1010
对Correct
NN
条输入时钟信号进行升压处理后输出分别与The input clock signal is boosted and the output is
NN
条输入时钟信号对应的Corresponding to the input clock signal
NN
条输出时钟信号。每一条输出时钟信号的高电位时段及低电位时段分别与对应的输入时钟信号的高电位时段及低电位时段相对应。Output clock signal. The high potential period and low potential period of each output clock signal correspond to the corresponding high potential period and low potential period of the input clock signal, respectively.
具体地，所述输入起始信号Specifically, the input start signal
STVSTV
由所述时序控制器By the timing controller
99
提供。provide.
具体地，specifically,
NN
条输出时钟信号的周期及占空比均相同。任意两条相邻的输出时钟信号各自的第一个上升沿之间的间隔均为一预设时长。The period and duty cycle of the output clock signal are the same. The interval between the first rising edges of any two adjacent output clock signals is a preset duration.
NN
条输出时钟信号中第一条时钟信号的第一个上升沿与输入起始信号The first rising edge of the first clock signal in the output clock signal and the input start signal
STVSTV
的上升沿之间的间隔为所述预设时长。The interval between the rising edges of is the preset duration.
具体地，当中间起始信号Specifically, when the intermediate start signal
STV1STV1
为高电位时，所述输出起始信号When it is high potential, the output start signal
STVOUTSTVOUT
为预设的恒压高电位，该预设的恒压高电位大于中间起始信号Is a preset constant voltage high potential, the preset constant voltage high potential is greater than the intermediate start signal
STV1STV1
的高电位。当中间起始信号High potential. When the intermediate start signal
STV1STV1
为低电位时，所述输出起始信号When it is low, the output start signal
STVOUTSTVOUT
为与中间起始信号Start signal
STV1STV1
的低电位相同的低电位。The low potential is the same as the low potential.
请结合图Please combine pictures
22
及图And figure
44
，本发明的电平转换模块的工作过程如下：The working process of the level conversion module of the present invention is as follows:
在初始阶段，In the initial stage,
NN
条输出时钟信号中第Output clock signal
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
为低电位，反相器Low potential, inverter
2020
的输出端为高电位，所述输入起始信号The output terminal is high potential, the input start signal
STVSTV
为低电位，所述中间起始信号Is low, the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端为低电位，单刀双掷开关The control terminal is low potential, single pole double throw switch
KK
将静触点与第二动触点连接使得中间起始信号Connect the static contact with the second moving contact so that the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端保持输入起始信号The control end of the input keeps the start signal
STVSTV
的低电位，此时输出起始信号Low potential, the start signal is output
STVOUTSTVOUT
为低电位。而后，Low potential. then,
NN
条输出时钟信号中第Output clock signal
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
保持低电位，反相器Keep low, inverter
2020
的输出端保持为高电位，所述输入起始信号The output of the input remains high, the input start signal
STVSTV
变为高电位，在单刀双掷开关Becomes high potential, in the single pole double throw switch
KK
将静触点与第二动触点仍旧连接的情况下，中间起始信号When the static contact and the second moving contact are still connected, the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端变为高电位，使得单刀双掷开关The control terminal of the switch becomes high potential, making the single pole double throw switch
KK
将静触点与第一动触点连接，所述中间起始信号Connect the static contact with the first moving contact, the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端保持反相器Control terminal of the inverter
2020
的输出端的高电位，此时，所述输出起始信号High potential at the output of the device, at this time, the output start signal
STVOUTSTVOUT
为预设的恒压高电位。而后，当It is a preset constant voltage high potential. Then, when
NN
条输出时钟信号中第Output clock signal
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
变为高电位，反相器Go high, inverter
2020
的输出端变为低电位，在单刀双掷开关The output of the switch becomes low potential, in the single pole double throw switch
KK
将静触点与第一动触点仍旧连接的情况下，所述中间起始信号When the static contact is still connected to the first moving contact, the intermediate start signal
STV1STV1
变为低电位，所述输出起始信号Goes low, the output start signal
STVOUTSTVOUT
为低电位。从而，本发明实现利用输入起始信号Low potential. Thus, the present invention realizes the use of input start signals
STVSTV
对输出起始信号Output start signal
STVOUTSTVOUT
进行上拉，使得输入起始信号Pull up so that the start signal is input
STVSTV
的上升沿到来时输出起始信号The start signal is output when the rising edge of
STVOUTSTVOUT
的上升沿到来，并利用第The rising edge comes and uses the first
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
对输出起始信号Output start signal
STVOUTSTVOUT
进行下拉，使得在第Pull down so that
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
的上升沿到来时输出起始信号The start signal is output when the rising edge of
STVOUTSTVOUT
的下降沿到来，不论输出时钟信号的数量有多少条，输出起始信号The falling edge of, no matter how many output clock signals, the start signal is output
STVOUTSTVOUT
均能够保持高电平直至第Can be kept high until the first
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
的上升沿到来，能够使得输出起始信号The rising edge of the arrival can make the output start signal
STVOUTSTVOUT
的高电平宽度满足时序要求，应用于The high level width of meets the timing requirements and is applied to
GOAGOA
电路时能够保证Circuit can guarantee
GOAGOA
电路正常工作。The circuit works normally.
基于同一发明构思，请参阅图Based on the same inventive concept, please refer to the picture
33
，并结合图And combined with the picture
44
，本发明还提供一种信号转换方法，包括如下步骤：The present invention also provides a signal conversion method, including the following steps:
步骤step
S1S1
、请参阅图, Please refer to the picture
22
，提供上述的电平转换模块，在此不再对电平转换模块的结构进行重复性描述。The above-mentioned level conversion module is provided, and the structure of the level conversion module will not be described repeatedly here.
步骤step
S2S2
、,
NN
条输出时钟信号中第Output clock signal
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
为低电位，反相器Low potential, inverter
2020
的输出端为高电位，所述输入起始信号The output terminal is high potential, the input start signal
STVSTV
为低电位，所述中间起始信号Is low, the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端为低电位，单刀双掷开关The control terminal is low potential, single pole double throw switch
KK
将静触点与第二动触点连接使得中间起始信号Connect the static contact with the second moving contact so that the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端保持输入起始信号The control end of the input keeps the start signal
STVSTV
的低电位，此时输出起始信号Low potential, the start signal is output
STVOUTSTVOUT
为低电位。Low potential.
步骤step
S3S3
、,
NN
条输出时钟信号中第Output clock signal
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
保持低电位，反相器Keep low, inverter
2020
的输出端保持为高电位，所述输入起始信号The output of the input remains high, the input start signal
STVSTV
变为高电位，在单刀双掷开关Becomes high potential, in the single pole double throw switch
KK
将静触点与第二动触点仍旧连接的情况下，中间起始信号When the static contact and the second moving contact are still connected, the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端变为高电位，使得单刀双掷开关The control terminal of the switch becomes high potential, making the single pole double throw switch
KK
将静触点与第一动触点连接，所述中间起始信号Connect the static contact with the first moving contact, the intermediate start signal
STV1STV1
及单刀双掷开关And single pole double throw switch
KK
的控制端保持反相器Control terminal of the inverter
2020
的输出端的高电位，此时，所述输出起始信号High potential at the output of the device, at this time, the output start signal
STVOUTSTVOUT
为预设的恒压高电位。It is a preset constant voltage high potential.
步骤step
S4S4
、,
NN
条输出时钟信号中第Output clock signal
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
变为高电位，反相器Go high, inverter
2020
的输出端变为低电位，在单刀双掷开关The output of the switch becomes low potential, in the single pole double throw switch
KK
将静触点与第一动触点仍旧连接的情况下，所述中间起始信号When the static contact is still connected to the first moving contact, the intermediate start signal
STV1STV1
变为低电位，所述输出起始信号Goes low, the output start signal
STVOUTSTVOUT
为低电位。Low potential.
需要说明的是，本发明的信号转换方法，应用上述的电平转换模块，能够实现利用输入起始信号It should be noted that the signal conversion method of the present invention, using the above-mentioned level conversion module, can realize the use of the input start signal
STVSTV
对输出起始信号Output start signal
STVOUTSTVOUT
进行上拉，使得输入起始信号Pull up so that the start signal is input
STVSTV
的上升沿到来时输出起始信号The start signal is output when the rising edge of
STVOUTSTVOUT
的上升沿到来，并利用第The rising edge comes and uses the first
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
对输出起始信号Output start signal
STVOUTSTVOUT
进行下拉，使得在第Pull down so that
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
的上升沿到来时输出起始信号The start signal is output when the rising edge of
STVOUTSTVOUT
的下降沿到来，不论输出时钟信号的数量有多少条，输出起始信号The falling edge of, no matter how many output clock signals, the start signal is output
STVOUTSTVOUT
均能够保持高电平直至第Can be kept high until the first
N/2N/2
条输出时钟信号Output clock signal
CLKOUT-N/2CLKOUT-N/2
的上升沿到来，能够使得输出起始信号The rising edge of the arrival can make the output start signal
STVOUTSTVOUT
的高电平宽度满足时序要求，应用于The high level width of meets the timing requirements and is applied to
GOAGOA
电路时能够保证Circuit can guarantee
GOAGOA
电路正常工作。The circuit works normally.
综上所述，本发明的电平转换模块包括时钟信号输出单元、反相器、单刀双掷开关及起始信号输出单元，工作时，利用输入起始信号上拉输出起始信号的电位，使得输入起始信号的上升沿到来时输出起始信号的上升沿到来，利用第In summary, the level conversion module of the present invention includes a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit. During operation, the input start signal is used to pull up to output the potential of the start signal. When the rising edge of the input start signal arrives, the rising edge of the output start signal arrives.
N/2N/2
（(
NN
为正偶数）条输出时钟信号下拉输出起始信号的电位，使得在第Is an even number) output clock signal pulls down the potential of the start signal, so that
N/2N/2
条输出时钟信号的上升沿到来时输出起始信号的下降沿到来，能够使得输出起始信号的高电平宽度满足时序要求，应用于When the rising edge of the output clock signal arrives, the falling edge of the output start signal arrives, which can make the high-level width of the output start signal meet the timing requirements.
GOAGOA
电路时能够保证Circuit can guarantee
GOAGOA
电路正常工作。本发明的信号转换方法能够使得输出起始信号的高电平宽度满足时序要求。The circuit works normally. The signal conversion method of the present invention can enable the high-level width of the output start signal to meet the timing requirements.
以上所述，对于本领域的普通技术人员来说，可以根据本发明的技术方案和技术构思作出其他各种相应的改变和变形，而所有这些改变和变形都应属于本发明权利要求的保护范围。As mentioned above, for those of ordinary skill in the art, various other corresponding changes and modifications can be made according to the technical solutions and technical concepts of the present invention, and all these changes and modifications should fall within the protection scope of the claims of the present invention. .
Claims (18)
- 一种电平转换模块，包括时钟信号输出单元、反相器、单刀双掷开关及起始信号输出单元；A level conversion module includes a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit;所述时钟信号输出单元用于输出N条脉冲的输出时钟信号，N条输出时钟信号各自的第一个上升沿依次产生；其中，N为正偶数；The clock signal output unit is used to output an output clock signal of N pulses, and the first rising edge of each of the N output clock signals is generated in sequence; where N is a positive even number;所述反相器的输入端电性连接时钟信号输出单元，接入N条输出时钟信号中的第N/2条输出时钟信号，输出端电性连接单刀双掷开关的第一动触点；The input end of the inverter is electrically connected to the clock signal output unit, and the N/2th output clock signal of the N output clock signals is connected, and the output end is electrically connected to the first moving contact of the single-pole double-throw switch;所述单刀双掷开关的第二动触点接入输入起始信号，静触点输出中间起始信号至起始信号输出单元，控制端电性连接静触点；所述单刀双掷开关在其控制端为高电位时将静触点与第一动触点连接，在其控制端为低电位时将静触点与第二动触点连接；所述输入起始信号的上升沿在N条输出时钟信号中的第一条输出时钟信号的第一个上升沿之前产生；The second moving contact of the single-pole double-throw switch is connected to the input start signal, the static contact outputs the intermediate start signal to the start signal output unit, and the control terminal is electrically connected to the static contact; the single-pole double-throw switch is at Connect the static contact to the first moving contact when the control terminal is high potential, and connect the static contact to the second moving contact when the control terminal is low potential; the rising edge of the input start signal is at N Generated before the first rising edge of the first output clock signal in the output clock signal;所述起始信号输出单元用于对中间起始信号进行升压处理后产生输出起始信号；所述输出起始信号的高电位时段及低电位时段分别与所述中间起始信号的高电位时段及低电位时段相对应。The start signal output unit is used to generate an output start signal after boosting the intermediate start signal; the high potential period and the low potential period of the output start signal are respectively the same as the high potential of the intermediate start signal The period corresponds to the low-potential period.
- 如权利要求1所述的电平转换模块，其中，所述时钟信号输出单元用于电性连接时序控制器，接入由时序控制器提供的N条输入时钟信号，所述时钟信号输出单元对N条输入时钟信号进行升压处理后输出分别与N条输入时钟信号对应的N条输出时钟信号。The level conversion module according to claim 1, wherein the clock signal output unit is used to electrically connect a timing controller and access N input clock signals provided by the timing controller, and the clock signal output unit The N input clock signals are boosted and output N output clock signals respectively corresponding to the N input clock signals.
- 如权利要求2所述的电平转换模块，其中，每一条输出时钟信号的高电位时段及低电位时段分别与对应的输入时钟信号的高电位时段及低电位时段相对应。The level conversion module of claim 2, wherein the high potential period and the low potential period of each output clock signal correspond to the corresponding high potential period and the low potential period of the input clock signal, respectively.
- 如权利要求2所述的电平转换模块，其中，所述输入起始信号由所述时序控制器提供。The level conversion module according to claim 2, wherein the input start signal is provided by the timing controller.
- 如权利要求1所述的电平转换模块，其中，N条输出时钟信号的周期及占空比均相同。The level conversion module according to claim 1, wherein the period and the duty ratio of the N output clock signals are the same.
- 如权利要求5所述的电平转换模块，其中，任意两条相邻的输出时钟信号各自的第一个上升沿之间的间隔均为一预设时长。The level conversion module according to claim 5, wherein the interval between the first rising edges of any two adjacent output clock signals is a preset duration.
- 如权利要求6所述的电平转换模块，其中，N条输出时钟信号中第一条时钟信号的第一个上升沿与输入起始信号的上升沿之间的间隔为所述预设时长。The level conversion module according to claim 6, wherein the interval between the first rising edge of the first clock signal and the rising edge of the input start signal among the N output clock signals is the preset duration.
- 如权利要求1所述的电平转换模块，其中，当中间起始信号为高电位时，所述输出起始信号为预设的恒压高电位，该预设的恒压高电位大于中间起始信号的高电位。The level conversion module according to claim 1, wherein when the intermediate start signal is a high potential, the output start signal is a preset constant voltage high potential, the preset constant voltage high potential is greater than the middle The high potential of the start signal.
- 如权利要求1所述的电平转换模块，其中，当中间起始信号为低电位时，所述输出起始信号为与中间起始信号的低电位相同的低电位。The level conversion module according to claim 1, wherein, when the intermediate start signal is a low potential, the output start signal is the same low potential as the low potential of the intermediate start signal.
- 一种信号转换方法，包括如下步骤：A signal conversion method includes the following steps:步骤S1、提供电平转换模块；Step S1: Provide a level conversion module;步骤S2、N条输出时钟信号中第N/2条输出时钟信号为低电位，所述输入起始信号为低电位，所述中间起始信号及单刀双掷开关的控制端为低电位，单刀双掷开关将静触点与第二动触点连接使得中间起始信号及单刀双掷开关的控制端保持低电位，所述输出起始信号为低电位；Step S2. The N/2th output clock signal of the N output clock signals is low potential, the input start signal is low potential, the intermediate start signal and the control end of the single pole double throw switch are low potential, single pole The double-throw switch connects the static contact with the second moving contact so that the intermediate start signal and the control end of the single-pole double-throw switch remain low, and the output start signal is low;步骤S3、N条输出时钟信号中第N/2条输出时钟信号为低电位，反相器的输出端为高电位，所述输入起始信号变为高电位，所述中间起始信号及单刀双掷开关的控制端变为高电位，单刀双掷开关将静触点与第一动触点连接使所述中间起始信号及单刀双掷开关的控制端保持高电位，所述输出起始信号为预设的恒压高电位；Step S3. The N/2th output clock signal of the N output clock signals is a low potential, the output terminal of the inverter is a high potential, the input start signal becomes a high potential, the intermediate start signal and the single pole The control end of the double-throw switch becomes a high potential, and the single-pole double-throw switch connects the static contact with the first moving contact to keep the intermediate start signal and the control end of the single-pole double-throw switch high, and the output starts The signal is a preset constant voltage high potential;步骤S4、N条输出时钟信号中第N/2条输出时钟信号变为高电位，反相器的输出端变为低电位，所述中间起始信号变为低电位，所述输出起始信号为低电位；Step S4. The N/2th output clock signal of the N output clock signals becomes a high potential, the output terminal of the inverter becomes a low potential, the intermediate start signal becomes a low potential, and the output start signal Low potential所述电平转换模块包括时钟信号输出单元、反相器、单刀双掷开关及起始信号输出单元；The level conversion module includes a clock signal output unit, an inverter, a single-pole double-throw switch, and a start signal output unit;所述时钟信号输出单元用于输出N条脉冲的输出时钟信号，N条输出时钟信号各自的第一个上升沿依次产生；其中，N为正偶数；The clock signal output unit is used to output an output clock signal of N pulses, and the first rising edge of each of the N output clock signals is generated in sequence; where N is a positive even number;所述反相器的输入端电性连接时钟信号输出单元，接入N条输出时钟信号中的第N/2条输出时钟信号，输出端电性连接单刀双掷开关的第一动触点；The input end of the inverter is electrically connected to the clock signal output unit, and the N/2th output clock signal of the N output clock signals is connected, and the output end is electrically connected to the first moving contact of the single-pole double-throw switch;所述单刀双掷开关的第二动触点接入输入起始信号，静触点输出中间起始信号至起始信号输出单元，控制端电性连接静触点；所述单刀双掷开关在其控制端为高电位时将静触点与第一动触点连接，在其控制端为低电位时将静触点与第二动触点连接；所述输入起始信号的上升沿在N条输出时钟信号中的第一条输出时钟信号的第一个上升沿之前产生；The second moving contact of the single-pole double-throw switch is connected to the input start signal, the static contact outputs the intermediate start signal to the start signal output unit, and the control terminal is electrically connected to the static contact; the single-pole double-throw switch is at Connect the static contact to the first moving contact when the control terminal is high potential, and connect the static contact to the second moving contact when the control terminal is low potential; the rising edge of the input start signal is at N Generated before the first rising edge of the first output clock signal in the output clock signal;所述起始信号输出单元用于对中间起始信号进行升压处理后产生输出起始信号；所述输出起始信号的高电位时段及低电位时段分别与所述中间起始信号的高电位时段及低电位时段相对应。The start signal output unit is used to generate an output start signal after boosting the intermediate start signal; the high potential period and the low potential period of the output start signal are respectively the same as the high potential of the intermediate start signal The period corresponds to the low-potential period.
- 如权利要求10As claimed in claim 10 所述的信号转换方法，其中，所述时钟信号输出单元用于电性连接时序控制器，接入由时序控制器提供的NThe signal conversion method, wherein the clock signal output unit is used to electrically connect the timing controller and access the N provided by the timing controller 条输入时钟信号，所述时钟信号输出单元对NInput clock signal, the clock signal output unit pair N 条输入时钟信号进行升压处理后输出分别与NThe input clock signal is boosted and output separately from N 条输入时钟信号对应的NN corresponding to the input clock signal 条输出时钟信号。Output clock signal.
- 如权利要求11As claimed in claim 11 所述的信号转换方法，其中，每一条输出时钟信号的高电位时段及低电位时段分别与对应的输入时钟信号的高电位时段及低电位时段相对应。In the signal conversion method, the high potential period and the low potential period of each output clock signal correspond to the corresponding high potential period and the low potential period of the input clock signal, respectively.
- 如权利要求11As claimed in claim 11 所述的信号转换方法，其中，所述输入起始信号由所述时序控制器提供。In the signal conversion method, the input start signal is provided by the timing controller.
- 如权利要求10As claimed in claim 10 所述的信号转换方法，其中，NThe signal conversion method described, wherein, N 条输出时钟信号的周期及占空比均相同。The period and duty cycle of the output clock signal are the same.
- 如权利要求14As claimed in claim 14 所述的信号转换方法，其中，任意两条相邻的输出时钟信号各自的第一个上升沿之间的间隔均为一预设时长。In the signal conversion method, the interval between the first rising edges of any two adjacent output clock signals is a preset duration.
- 如权利要求15As claimed in claim 15 所述的信号转换方法，其中，NThe signal conversion method described, wherein, N 条输出时钟信号中第一条时钟信号的第一个上升沿与输入起始信号的上升沿之间的间隔为所述预设时长。The interval between the first rising edge of the first clock signal in the output clock signal and the rising edge of the input start signal is the preset duration.
- 如权利要求10As claimed in claim 10 所述的信号转换方法，其中，当中间起始信号为高电位时，所述输出起始信号为预设的恒压高电位，该预设的恒压高电位大于中间起始信号的高电位。The signal conversion method, wherein, when the intermediate start signal is a high potential, the output start signal is a preset constant voltage high potential, the preset constant voltage high potential is greater than the high potential of the intermediate start signal .
- 如权利要求10As claimed in claim 10 所述的信号转换方法，其中，当中间起始信号为低电位时，所述输出起始信号为与中间起始信号的低电位相同的低电位。In the signal conversion method, when the intermediate start signal is a low potential, the output start signal is the same low potential as the intermediate start signal.
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