CN109300448B - Level conversion module and signal conversion method - Google Patents
Level conversion module and signal conversion method Download PDFInfo
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- CN109300448B CN109300448B CN201811550482.2A CN201811550482A CN109300448B CN 109300448 B CN109300448 B CN 109300448B CN 201811550482 A CN201811550482 A CN 201811550482A CN 109300448 B CN109300448 B CN 109300448B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
Abstract
The invention provides a level conversion module and a signal conversion method. The level conversion module comprises a clock signal output unit, a phase inverter, a single-pole double-throw switch and an initial signal output unit, wherein during work, the potential of an output initial signal is pulled up by using an input initial signal, so that the rising edge of the output initial signal arrives when the rising edge of the input initial signal arrives, and the potential of the output initial signal is pulled down by using an N/2(N is a positive even number) output clock signal, so that the falling edge of the output initial signal arrives when the rising edge of the N/2 output clock signal arrives, the high level width of the output initial signal can meet the time sequence requirement, and the normal work of a GOA circuit can be ensured when the level conversion module is applied to the GOA circuit.
Description
Technical Field
The present invention relates to the field of display technologies, and in particular, to a level conversion module and a signal conversion method.
Background
With the development of Display technology, flat panel Display devices such as Liquid Crystal Display (LCD) devices have been widely used in various consumer electronics products such as mobile phones, televisions, personal digital assistants, digital cameras, notebook computers, and desktop computers, and become the mainstream of Display devices, because of their advantages such as high image quality, power saving, thin body, and wide application range.
In the active liquid crystal display device, each pixel is electrically connected with a Thin Film Transistor (TFT), a Gate (Gate) of the TFT is connected to a horizontal scanning line, a Source (Source) is connected to a data line in a vertical direction, and a Drain (Drain) is connected to a pixel electrode. Applying sufficient voltage to the horizontal scanning lines can turn on all TFTs electrically connected to the horizontal scanning lines, so that signal voltage on the data lines can be written into the pixels, and different transmittances of liquid crystals can be controlled to achieve the effect of controlling color and brightness.
Currently, the driving of the horizontal scanning lines of the active liquid crystal display panel is mainly performed by an external Integrated Circuit (IC), and the external IC can control the charging and discharging of each level of horizontal scanning lines step by step. The GOA (Gate Driver on Array) technology is a driving method that can use the Array process of the liquid crystal display panel to fabricate the Gate driving circuit on the TFT Array substrate to scan the Gate line by line. In the GOA circuit, several clock signals and start signals are generally required to be accessed to implement the function of scanning the gate line by line. In the prior art, a timing controller (Tcon) is generally used to output an original clock signal and an original start signal to a level shifter (level shifter), and the level shifter performs a voltage boost operation to generate an output clock signal and an output start signal, and outputs the output clock signal and the output start signal to a GOA circuit of a liquid crystal display panel.
The present level shift unit outputs a plurality of output clock signals sequentially after a rising edge of an output start signal for a preset time period, and generally it is required to satisfy that a falling edge of the output start signal and a rising edge of an n/2 th output clock signal occur simultaneously, where n is a positive even number. Referring to fig. 1, taking four output clock signals as an example, after the rising edge of the output start signal STVout passes through 1/2 times of the high-level duration of the output start signal STVout, a first rising edge of the first output clock signal CLKout1, a second output clock signal CLKout2, a third output clock signal CLKout3 and a fourth output clock signal CLKout4 are sequentially generated, the first rising edge of the first output clock signal CLKout1, the second output clock signal CLKout2, the third output clock signal CLKout3 and the fourth output clock signal CLKout4 have 1/2 times of the high-level duration of the output start signal STVout, and when the first rising edge of the second output clock signal CLKout2 comes, the falling edge of the output start signal STVout comes. Because the width of the output initial signal output by the level conversion module follows the width of the original initial signal transmitted by the timing controller, when a large number of output clock signals need to be provided, the original initial signal has a condition of seriously insufficient width, which leads to the serious insufficiency of the width of the output initial signal, and can not meet the condition that the falling edge of the original initial signal and the rising edge of the Nth/2 th output clock signal occur simultaneously, thereby leading to the failure of GOA and the problem of reliability.
Disclosure of Invention
The invention aims to provide a level conversion module which can enable the high level width of an output starting signal to meet the time sequence requirement.
Another objective of the present invention is to provide a signal conversion method, which can make the high level width of the output start signal satisfy the timing requirement.
In order to achieve the above object, the present invention first provides a level shift module, which includes a clock signal output unit, an inverter, a single-pole double-throw switch, and an initial signal output unit;
the clock signal output unit is used for outputting output clock signals of N pulses, and respective first rising edges of the N output clock signals are generated in sequence; wherein N is a positive even number;
the input end of the phase inverter is electrically connected with the clock signal output unit and is connected with the (N/2) th output clock signal in the N output clock signals, and the output end of the phase inverter is electrically connected with the first movable contact of the single-pole double-throw switch;
the second movable contact of the single-pole double-throw switch is connected with an input initial signal, the fixed contact outputs a middle initial signal to the initial signal output unit, and the control end is electrically connected with the fixed contact; the single-pole double-throw switch connects the static contact with the first movable contact when the control end of the single-pole double-throw switch is at a high potential, and connects the static contact with the second movable contact when the control end of the single-pole double-throw switch is at a low potential; a rising edge of the input start signal is generated before a first rising edge of a first one of the N output clock signals;
the starting signal output unit is used for generating an output starting signal after boosting the intermediate starting signal; the high potential period and the low potential period of the output start signal correspond to the high potential period and the low potential period of the intermediate start signal, respectively.
The clock signal output unit is used for being electrically connected with the time schedule controller and accessing N input clock signals provided by the time schedule controller, and outputs N output clock signals respectively corresponding to the N input clock signals after the clock signal output unit performs voltage boosting processing on the N input clock signals.
The high potential period and the low potential period of each output clock signal respectively correspond to the high potential period and the low potential period of the corresponding input clock signal.
The input start signal is provided by the timing controller.
The period and the duty ratio of the N output clock signals are the same.
The interval between the first rising edges of any two adjacent output clock signals is a preset time length.
And the interval between the first rising edge of the first clock signal in the N output clock signals and the rising edge of the input starting signal is the preset duration.
And when the middle initial signal is at a high potential, the output initial signal is a preset constant voltage high potential, and the preset constant voltage high potential is greater than the high potential of the middle initial signal.
When the intermediate start signal is at a low potential, the output start signal is at a low potential that is the same as the low potential of the intermediate start signal.
The invention also provides a signal conversion method, which comprises the following steps:
step S1, providing the level conversion module;
step S2, the N/2 th output clock signal in the N output clock signals is low potential, the input starting signal is low potential, the middle starting signal and the control end of the single-pole double-throw switch are low potential, the single-pole double-throw switch connects the static contact with the second movable contact to keep the middle starting signal and the control end of the single-pole double-throw switch low potential, and the output starting signal is low potential;
step S3, the N/2 th output clock signal in the N output clock signals is low potential, the output end of the phase inverter is high potential, the input initial signal is high potential, the middle initial signal and the control end of the single-pole double-throw switch are high potential, the single-pole double-throw switch connects the static contact with the first movable contact to make the middle initial signal and the control end of the single-pole double-throw switch keep high potential, the output initial signal is preset constant voltage high potential;
step S4, the N/2 th output clock signal among the N output clock signals becomes high potential, the output end of the inverter becomes low potential, the intermediate start signal becomes low potential, and the output start signal is low potential.
The invention has the beneficial effects that: the level conversion module comprises a clock signal output unit, a phase inverter, a single-pole double-throw switch and an initial signal output unit, wherein during work, the potential of an output initial signal is pulled up by using an input initial signal, so that the rising edge of the output initial signal arrives when the rising edge of the input initial signal arrives, and the potential of the output initial signal is pulled down by using an N/2(N is a positive even number) output clock signal, so that the falling edge of the output initial signal arrives when the rising edge of the N/2 output clock signal arrives, the high level width of the output initial signal can meet the time sequence requirement, and the normal work of a GOA circuit can be ensured when the level conversion module is applied to the GOA circuit. The signal conversion method can enable the high level width of the output initial signal to meet the time sequence requirement.
Drawings
For a better understanding of the nature and technical aspects of the present invention, reference should be made to the following detailed description of the invention, taken in conjunction with the accompanying drawings, which are provided for purposes of illustration and description and are not intended to limit the invention.
In the drawings, there is shown in the drawings,
fig. 1 is a waveform diagram of an output start signal and an output clock signal of a conventional level shift module;
FIG. 2 is a schematic structural diagram of a level shift module according to the present invention;
FIG. 3 is a flow chart of a signal conversion method according to the present invention;
FIG. 4 is a timing diagram illustrating a signal conversion method according to the present invention.
Detailed Description
To further illustrate the technical means and effects of the present invention, the following detailed description is given with reference to the preferred embodiments of the present invention and the accompanying drawings.
Referring to fig. 2, the present invention provides a level shift module, which includes a clock signal output unit 10, an inverter 20, a single-pole double-throw switch K, and an initial signal output unit 30.
The clock signal output unit 10 is configured to output N pulse output clock signals, where respective first rising edges of the N output clock signals are sequentially generated. Where N is a positive even number, for example, it may be 4, 6, 8. The output clock signals of the N pulses are output to a GOA circuit of the liquid crystal display panel to control the GOA circuit to perform progressive scanning.
The input end of the inverter 20 is electrically connected to the clock signal output unit 10, and is connected to the N/2 th output clock signal CLKOUT-N/2 of the N output clock signals, and the output end is electrically connected to the first moving contact of the single-pole double-throw switch K. The second moving contact of the single-pole double-throw switch K is connected with the input starting signal STV, the fixed contact outputs the intermediate starting signal STV1 to the starting signal output unit 30, and the control end is electrically connected with the fixed contact. The single-pole double-throw switch K connects the static contact with the first movable contact when the control end of the single-pole double-throw switch is at a high potential, and connects the static contact with the second movable contact when the control end of the single-pole double-throw switch is at a low potential; the rising edge of the input start signal STV is generated before the first rising edge of the first one of the N output clock signals. The start signal output unit 30 is configured to generate an output start signal STVOUT after performing a boosting process on the intermediate start signal STV 1. The high-potential period and the low-potential period of the output start signal STVOUT correspond to the high-potential period and the low-potential period of the intermediate start signal STV1, respectively.
Specifically, the clock signal output unit 10 is electrically connected to the timing controller 9 outside the level shift module, and is connected to N input clock signals provided by the timing controller 9, and the clock signal output unit 10 performs voltage boosting processing on the N input clock signals and outputs N output clock signals respectively corresponding to the N input clock signals. The high potential period and the low potential period of each output clock signal respectively correspond to the high potential period and the low potential period of the corresponding input clock signal.
Specifically, the input start signal STV is supplied from the timing controller 9.
Specifically, the period and the duty ratio of the N output clock signals are the same. The interval between the first rising edges of any two adjacent output clock signals is a preset time length. And the interval between the first rising edge of the first clock signal in the N output clock signals and the rising edge of the input start signal STV is the preset duration.
Specifically, when the intermediate start signal STV1 is at a high potential, the output start signal STVOUT is at a predetermined constant voltage high potential, which is greater than the high potential of the intermediate start signal STV 1. When the intermediate start signal STV1 is low, the output start signal STVOUT is low, which is the same as the low of the intermediate start signal STV 1.
Referring to fig. 2 and fig. 4, the operation process of the level shift module of the present invention is as follows:
in the initial stage, the N/2 th output clock signal CLKOUT-N/2 of the N output clock signals is at a low potential, the output end of the inverter 20 is at a high potential, the input start signal STV is at a low potential, the intermediate start signal STV1 and the control end of the single-pole double-throw switch K are at a low potential, the single-pole double-throw switch K connects the stationary contact with the second movable contact so that the intermediate start signal STV1 and the control end of the single-pole double-throw switch K keep the low potential of the input start signal STV, and at this time, the output start signal STVOUT is at a low potential. Then, the N/2 th output clock signal CLKOUT-N/2 of the N output clock signals keeps a low potential, the output end of the inverter 20 keeps a high potential, the input start signal STV becomes a high potential, under the condition that the single-pole double-throw switch K still connects the stationary contact with the second movable contact, the control ends of the middle start signal STV1 and the single-pole double-throw switch K become high potentials, so that the single-pole double-throw switch K connects the stationary contact with the first movable contact, the control ends of the middle start signal STV1 and the single-pole double-throw switch K keep the high potential of the output end of the inverter 20, and at this time, the output start signal STVOUT is a preset constant voltage high potential. Then, when the N/2 th output clock signal CLKOUT-N/2 of the N output clock signals becomes a high potential, the output terminal of the inverter 20 becomes a low potential, and under the condition that the single-pole double-throw switch K still connects the stationary contact with the first movable contact, the intermediate start signal STV1 becomes a low potential, and the output start signal STVOUT becomes a low potential. Therefore, the invention realizes that the output start signal STVOUT is pulled up by the input start signal STV, so that the rising edge of the output start signal STVOUT arrives when the rising edge of the input start signal STV arrives, and the output start signal STVOUT is pulled down by the N/2 th output clock signal CLKOUT-N/2, so that the falling edge of the output start signal STVOUT arrives when the rising edge of the N/2 th output clock signal CLKOUT-N/2 arrives, the output start signal STVOUT can keep high level until the rising edge of the N/2 th output clock signal CLKOUT-N/2 arrives no matter how many output clock signals exist, the high level width of the output start signal STVOUT can meet the time sequence requirement, and the GOA circuit can be ensured to normally work when the output start signal STVOUT is applied to the GOA circuit.
Based on the same inventive concept, referring to fig. 3 in combination with fig. 4, the present invention further provides a signal conversion method, including the following steps:
step S1, please refer to fig. 2, which provides the above level shift module, and the structure of the level shift module is not repeatedly described here.
Step S2, the N/2 th output clock signal CLKOUT-N/2 of the N output clock signals is at a low potential, the output end of the inverter 20 is at a high potential, the input start signal STV is at a low potential, the intermediate start signal STV1 and the control end of the single-pole double-throw switch K are at a low potential, the single-pole double-throw switch K connects the stationary contact with the second movable contact so that the intermediate start signal STV1 and the control end of the single-pole double-throw switch K keep the low potential of the input start signal STV, and at this time, the output start signal STVOUT is at a low potential.
Step S3, the N/2 th output clock signal CLKOUT-N/2 of the N output clock signals keeps a low potential, the output end of the inverter 20 keeps a high potential, the input start signal STV becomes a high potential, under the condition that the single-pole double-throw switch K still connects the stationary contact with the second movable contact, the middle start signal STV1 and the control end of the single-pole double-throw switch K become a high potential, so that the single-pole double-throw switch K connects the stationary contact with the first movable contact, the middle start signal STV1 and the control end of the single-pole double-throw switch K keep the high potential of the output end of the inverter 20, and at this time, the output start signal STVOUT is a preset constant voltage high potential.
Step S4, the N/2 th output clock signal CLKOUT-N/2 of the N output clock signals becomes high potential, the output terminal of the inverter 20 becomes low potential, under the condition that the single-pole double-throw switch K connects the stationary contact with the first movable contact, the middle start signal STV1 becomes low potential, and the output start signal STVOUT is low potential.
It should be noted that, the signal conversion method of the present invention, using the above-mentioned level conversion module, can realize the pull-up of the output start signal STVOUT by using the input start signal STV, so that the rising edge of the output start signal STVOUT comes when the rising edge of the input start signal STV comes, and pulls down the output start signal STVOUT using the N/2 th output clock signal CLKOUT-N/2, the falling edge of the output starting signal STVOUT arrives when the rising edge of the N/2 th output clock signal CLKOUT-N/2 arrives, the output starting signal STVOUT can keep high level until the rising edge of the N/2 th output clock signal CLKOUT-N/2 arrives no matter how many output clock signals exist, the high level width of the output starting signal STVOUT can meet the time sequence requirement, and the GOA circuit can be ensured to normally work when the output starting signal STVOUT is applied to the GOA circuit.
In summary, the level shift module of the present invention includes a clock signal output unit, an inverter, a single-pole double-throw switch, and an initial signal output unit, and during operation, the input initial signal is used to pull up the potential of the output initial signal, so that the rising edge of the output initial signal arrives when the rising edge of the input initial signal arrives, and the N/2(N is a positive even number) output clock signal is used to pull down the potential of the output initial signal, so that the falling edge of the output initial signal arrives when the rising edge of the N/2 output clock signal arrives, and the high level width of the output initial signal can meet the timing requirement, and when the level shift module is applied to a GOA circuit, the GOA circuit can be guaranteed to operate normally. The signal conversion method can enable the high level width of the output initial signal to meet the time sequence requirement.
As described above, it will be apparent to those skilled in the art that other various changes and modifications may be made based on the technical solution and concept of the present invention, and all such changes and modifications are intended to fall within the scope of the appended claims.
Claims (10)
1. A level conversion module is characterized by comprising a clock signal output unit (10), an inverter (20), a single-pole double-throw switch (K) and a starting signal output unit (30);
the clock signal output unit (10) is used for outputting output clock signals of N pulses, and respective first rising edges of the N output clock signals are generated in sequence; wherein N is a positive even number;
the input end of the phase inverter (20) is electrically connected with the clock signal output unit (10), is accessed to the N/2 th output clock signal (CLKOUT-N/2) in the N output clock signals, and the output end of the phase inverter is electrically connected with the first movable contact of the single-pole double-throw switch (K);
the second movable contact of the single-pole double-throw switch (K) is connected with an input initial Signal (STV), the fixed contact outputs an intermediate initial signal (STV1) to the initial signal output unit (30), and the control end is electrically connected with the fixed contact; the single-pole double-throw switch (K) connects the static contact with the first movable contact when the control end of the switch is at a high potential, and connects the static contact with the second movable contact when the control end of the switch is at a low potential; a rising edge of the input start Signal (STV) is generated before a first rising edge of a first one of the N output clock signals; a falling edge of the input start Signal (STV) is generated before a rising edge of the N/2 th output clock signal (CLKOUT-N/2);
the starting signal output unit (30) is used for generating an output starting Signal (STVOUT) after boosting the intermediate starting signal (STV 1); the high potential period and the low potential period of the output start Signal (STVOUT) correspond to the high potential period and the low potential period of the middle start signal (STV1), respectively.
2. The level shift module according to claim 1, wherein the clock signal output unit (10) is electrically connected to the timing controller (9) and is connected to N input clock signals provided by the timing controller (9), and the clock signal output unit (10) boosts the N input clock signals and outputs N output clock signals corresponding to the N input clock signals.
3. The level shift module as claimed in claim 2, wherein the high period and the low period of each output clock signal correspond to the high period and the low period of the corresponding input clock signal, respectively.
4. A level conversion module as claimed in claim 2, characterized in that the input start Signal (STV) is provided by the timing controller (9).
5. The level shift module of claim 1, wherein the period and duty cycle of the N output clock signals are the same.
6. The level shift module of claim 5, wherein the interval between the first rising edges of any two adjacent output clock signals is a predetermined time.
7. The level shift module of claim 6, wherein the interval between the first rising edge of the first of the N output clock signals and the rising edge of the input start Signal (STV) is the predetermined duration.
8. The level shift module as claimed in claim 1, wherein the output start Signal (STVOUT) is a predetermined constant voltage high when the middle start signal (STV1) is high, the predetermined constant voltage high being greater than the high of the middle start signal (STV 1).
9. The level shift module of claim 1, wherein when the intermediate start signal (STV1) is low, the output start Signal (STVOUT) is at a low potential that is the same as the low potential of the intermediate start signal (STV 1).
10. A method of signal conversion, comprising the steps of:
step S1, providing a level conversion module according to any one of claims 1-9;
step S2, the N/2 th output clock signal (CLKOUT-N/2) in the N output clock signals is at low potential, the input start Signal (STV) is at low potential, the control ends of the middle start signal (STV1) and the single-pole double-throw switch (K) are at low potential, the single-pole double-throw switch (K) connects the static contact with the second movable contact to enable the control ends of the middle start signal (STV1) and the single-pole double-throw switch (K) to keep at low potential, and the output start Signal (STVOUT) is at low potential;
step S3, the N/2 th output clock signal (CLKOUT-N/2) in the N output clock signals is low potential, the output end of the phase inverter (20) is high potential, the input starting Signal (STV) is changed into high potential, the control ends of the middle starting signal (STV1) and the single-pole double-throw switch (K) are changed into high potential, the single-pole double-throw switch (K) connects the static contact with the first movable contact to enable the control ends of the middle starting signal (STV1) and the single-pole double-throw switch (K) to keep high potential, and the output starting Signal (STVOUT) is preset constant voltage high potential;
step S4, the N/2 th output clock signal (CLKOUT-N/2) among the N output clock signals becomes high potential, the output terminal of the inverter (20) becomes low potential, the middle start signal (STV1) becomes low potential, and the output start Signal (STVOUT) is low potential.
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| PCT/CN2018/124527 WO2020124669A1 (en) | 2018-12-18 | 2018-12-27 | Level shifter and signal conversion method |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074197A (en) * | 2011-01-21 | 2011-05-25 | 昆山工研院新型平板显示技术中心有限公司 | Driving method for active matrix organic light emitting display |
| CN104680991A (en) * | 2015-03-03 | 2015-06-03 | 深圳市华星光电技术有限公司 | Level shifting circuit and method for GOA-framework liquid crystal panel |
| CN107665683A (en) * | 2017-10-12 | 2018-02-06 | 深圳市华星光电技术有限公司 | Clock signal output circuit and clock signal output method |
| CN108735162A (en) * | 2018-05-25 | 2018-11-02 | 京东方科技集团股份有限公司 | Display device, gate driving circuit, shift register and its control method |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI282984B (en) * | 2005-10-07 | 2007-06-21 | Innolux Display Corp | Shift register system, shift registering method and LCD driving circuit |
| KR20080004986A (en) * | 2006-07-07 | 2008-01-10 | 삼성전자주식회사 | Driving apparatus and liquid crystal display including the same and driving method thereof |
| KR101432818B1 (en) * | 2007-12-07 | 2014-08-26 | 엘지디스플레이 주식회사 | Device of driving liquid crystal display device and driving method thereof |
| CN102903317B (en) * | 2011-07-28 | 2015-07-29 | 群康科技(深圳)有限公司 | Display drive method and the display device applying it |
| KR20140023711A (en) * | 2012-08-17 | 2014-02-27 | 삼성디스플레이 주식회사 | Display device able to prevent abnormal display caused by soft fail and driving method of the same |
| CN106157893B (en) * | 2016-09-09 | 2018-12-11 | 京东方科技集团股份有限公司 | Shift register cell and its driving method, driving circuit and display device |
| CN107329612B (en) * | 2017-06-29 | 2020-04-21 | 上海天马微电子有限公司 | Scanning circuit, driving circuit and touch display device |
-
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102074197A (en) * | 2011-01-21 | 2011-05-25 | 昆山工研院新型平板显示技术中心有限公司 | Driving method for active matrix organic light emitting display |
| CN104680991A (en) * | 2015-03-03 | 2015-06-03 | 深圳市华星光电技术有限公司 | Level shifting circuit and method for GOA-framework liquid crystal panel |
| CN107665683A (en) * | 2017-10-12 | 2018-02-06 | 深圳市华星光电技术有限公司 | Clock signal output circuit and clock signal output method |
| CN108735162A (en) * | 2018-05-25 | 2018-11-02 | 京东方科技集团股份有限公司 | Display device, gate driving circuit, shift register and its control method |
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