CN107316839B - Manufacturing method of array substrate, array substrate and display device - Google Patents

Manufacturing method of array substrate, array substrate and display device Download PDF

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CN107316839B
CN107316839B CN201710526577.XA CN201710526577A CN107316839B CN 107316839 B CN107316839 B CN 107316839B CN 201710526577 A CN201710526577 A CN 201710526577A CN 107316839 B CN107316839 B CN 107316839B
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electrode
pattern
layer film
insulating layer
hole
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CN107316839A (en
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戴文君
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Shanghai Tianma Microelectronics Co Ltd
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Shanghai Tianma Microelectronics Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

Abstract

The invention relates to a manufacturing method of an array substrate, the array substrate and a display device, which are used for solving the problems that the existing TFT substrate manufacturing process is complex, an effective mode is urgently needed, the photoetching process can be reduced, and the product yield cannot be reduced. The manufacturing method comprises the following steps: forming a grid metal layer pattern, a grid insulation layer film, an active layer pattern and a source drain metal layer pattern on a substrate; sequentially forming a planarization layer film, a first electrode layer pattern, a first insulating layer film and a photoresist pattern on the source drain metal layer pattern; sequentially carrying out dry etching process on the first insulating layer film and the planarization layer film, and forming a first through hole by the via holes formed in the first insulating layer film, the first shielding electrode and the planarization layer film; and forming a second electrode layer pattern comprising a first bridging electrode on the first insulating layer film, wherein the first bridging electrode at least completely covers the region of the first through hole and is connected with the source drain metal layer pattern.

Description

Manufacturing method of array substrate, array substrate and display device
Technical Field
The invention relates to the technical field of array substrates, in particular to a manufacturing method of an array substrate, the array substrate and a display device.
Background
At present, in the manufacture of a liquid crystal display panel, especially in the process of manufacturing a Thin Film Transistor (TFT) substrate, the manufacturing process is complex, and seven photolithography processes are generally performed, which are a gate electrode, an active layer, a source/drain electrode, a planarization layer, a first passivation layer, a via hole, and a pixel electrode; or, a gate electrode, an active layer & source drain electrode, a first passivation layer, a planarization layer, a common electrode, a via hole, and a pixel electrode. The multiple mask exposure not only increases the processing time and the production cost, but also increases the difficulty of the process, is easy to cause poor alignment precision, and reduces the yield of products.
In order to reduce the number of photolithography processes and reduce the process time and production cost, there has been proposed in the prior art to reduce the photolithography process of the TFT substrate by using a common photolithography process for the electrode and the planarization layer, the array substrate can be further fabricated by five photolithography processes to form the structure shown in fig. 1a, specifically, a gate metal layer (not shown) is patterned on the base substrate 10 by a first photolithography process, the active layer 11 and the source and drain electrode layers 12 are patterned by a second photolithography process, the first electrode layer 13 and the planarization layer 14 are patterned by a third photolithography process, through the fourth photolithography process, via holes are formed in a thin film (some through holes need to be etched, which is not required in fig. 1) of the gate insulating layer 15, a thin film of the first insulating layer 16, and a thin film of the second insulating layer 17, and the second electrode layer 18 is patterned through the fifth photolithography process.
After the third photolithography process, the protrusion 13t is easily formed between the pattern of the first electrode layer 13 and the pattern of the planarization layer 14, i.e. the structure shown in fig. 1b is formed, which is not favorable for the climbing of the electrode layer material during the subsequent fabrication of the second electrode layer 108, and thus the product yield is reduced.
In addition, when the fourth photolithography process etches the via hole, the etching of the hole sleeve hole needs to be realized, at this time, in order to better etch the first insulating layer film and the second insulating layer film, the aperture of the via hole on the first electrode layer and the planarization layer needs to be set to be large so as to meet the etching requirement, but the aperture of the via hole on the planarization layer is large, so that the aperture ratio and the subsequent processing are influenced. In addition, since the gate insulating layer thin film, the first insulating layer thin film and the second insulating layer thin film are formed by different photolithography processes, defects due to insufficient alignment accuracy are likely to occur when the via holes are etched in the respective film layers, and the product yield is reduced.
In summary, the conventional TFT substrate manufacturing process is complex, and generally requires seven photolithography processes, and an effective method is needed to reduce the photolithography processes without reducing the yield of the product.
Disclosure of Invention
The invention aims to provide a manufacturing method of an array substrate, the array substrate and a display device, which are used for solving the problems that the existing manufacturing process of a TFT substrate is complex, seven photoetching processes are generally required, and an effective mode is urgently needed to reduce the photoetching processes and the product yield is not reduced.
The embodiment of the invention provides a manufacturing method of an array substrate, which comprises the following steps:
forming a grid metal layer pattern, a grid insulation layer film, an active layer pattern and a source drain metal layer pattern on a substrate;
sequentially forming a planarization layer film, a first electrode layer pattern, a first insulating layer film and a photoresist pattern on the source drain metal layer pattern;
sequentially carrying out dry etching process on the first insulating layer film and the planarization layer film by taking the first shielding electrode in the photoresist pattern and the first electrode layer pattern as shielding, and forming a first through hole by using via holes formed in the first insulating layer film, the first shielding electrode and the planarization layer film;
and forming a second electrode layer pattern comprising a first bridging electrode on the first insulating layer film, wherein the first bridging electrode at least completely covers the region of the first through hole and is connected with the source drain metal layer pattern.
An embodiment of the present invention further provides an array substrate, where the array substrate includes: the substrate comprises a grid metal layer pattern, a grid insulating layer, an active layer pattern, a source drain metal layer pattern, a planarization layer film, a first electrode layer pattern, a first insulating layer film and a second electrode layer pattern which are sequentially arranged on a substrate; wherein the content of the first and second substances,
forming a first through hole in the first insulating layer film, the first shielding electrode in the first electrode layer pattern and the via hole formed in the planarization layer film;
and the first bridging electrode included in the second electrode layer pattern at least completely covers the area of the first through hole and is respectively connected with the first shielding electrode and the source drain metal layer pattern.
The embodiment of the invention also provides a display device, which comprises the array substrate provided by the embodiment of the invention.
The invention has the following beneficial effects:
the embodiment of the invention provides a manufacturing method of an array substrate, the array substrate and a display device, which improve the manufacturing process of a plurality of film layers needing to etch through holes in the array substrate to form through holes by optimizing the manufacturing method of the array substrate, wherein a whole layer of a planarization layer film is required to be formed on a source and drain electrode metal layer pattern, a first electrode layer pattern comprising a first shielding electrode is formed on the planarization layer film through a photoetching process, then a photoresist pattern is formed through the photoetching process, the photoresist pattern and the first shielding electrode in the first electrode layer pattern are used as shielding, and the first insulating layer film and the planarization layer film are sequentially subjected to a dry etching process, because the invention forms the through holes on the first insulating layer film and the planarization layer film after the first electrode layer pattern and the whole layer of the first insulating layer film are manufactured, the etching process of the hole sleeve hole in the prior art is not adopted, and the first electrode layer pattern comprises the first shielding electrode used for shielding when the dry etching process is carried out on the planarization layer, so that the manufacturing method can meet the etching requirement without increasing the aperture of the through hole in the planarization layer, and further can improve the aperture opening ratio and the yield of subsequent processing procedures. In addition, the manufacturing method of the array substrate can manufacture the array substrate only by five photoetching processes, compared with the prior art, because the through holes in the first insulating layer film and the planarization layer film can be formed by only one photoetching process, the influence caused by insufficient alignment precision due to different photoetching process manufacturing can be reduced, the photoetching process can be reduced, and the yield of products can not be reduced.
Drawings
FIG. 1a is a schematic structural diagram of an array substrate in the prior art;
FIG. 1b is a schematic structural diagram of a prior art after a protrusion is formed in a first electrode layer on an array substrate;
fig. 2 is a flowchart illustrating a basic step of a method for forming a first via hole in an array substrate according to an embodiment of the present invention;
fig. 3 is a top view of the whole structure of a first structure array substrate according to an embodiment of the present invention;
FIG. 4a is an enlarged view of a portion of P in FIG. 3 according to an embodiment of the present invention;
fig. 4b is a schematic structural diagram of the first electrode layer corresponding to fig. 4a according to an embodiment of the present invention;
fig. 4c is a schematic structural diagram of a second electrode layer corresponding to fig. 4a according to an embodiment of the present invention;
fig. 5a is a top view of a single pixel unit after a first via hole is formed on an array substrate with a second structure according to an embodiment of the present invention;
fig. 5b is a schematic structural diagram of the first electrode layer corresponding to fig. 5a according to an embodiment of the present invention;
fig. 5c is a schematic structural diagram of a second electrode layer corresponding to fig. 5a according to an embodiment of the present invention;
FIG. 6 is a schematic cross-sectional view taken along the direction C-C' in FIG. 4a according to an embodiment of the present invention;
FIG. 7 is a schematic cross-sectional view taken along the direction D-D' in FIG. 5a according to an embodiment of the present invention;
fig. 8a to 8k are schematic structural diagrams respectively illustrating steps of a manufacturing method for forming a first via hole in an array substrate according to an embodiment of the present invention after the steps are performed;
FIG. 9 is a flowchart of a step of forming a via hole of a first via hole in each film layer according to an embodiment of the present invention;
FIG. 10 is a schematic cross-sectional view corresponding to FIG. 6 and including a second insulating layer according to an embodiment of the invention;
FIG. 11 is a schematic structural diagram of a first electrode layer pattern etched by a wet etching process according to an embodiment of the present invention;
fig. 12 is a schematic structural diagram after a wet etching process is used to etch a first electrode layer pattern according to an embodiment of the present invention;
fig. 13 is a flowchart illustrating the overall steps of a method for forming a first via on an array substrate according to an embodiment of the present invention;
fig. 14 is a flowchart illustrating a basic step of a method for forming a second via hole in an array substrate according to an embodiment of the present invention;
FIG. 15 is a schematic cross-sectional view taken along the direction E-E' in FIG. 4a according to an embodiment of the present invention;
FIG. 16 is a schematic cross-sectional view taken along the direction F-F' in FIG. 5a according to an embodiment of the present invention;
FIG. 17 is a flowchart illustrating a step of forming a via hole of a second via in each film layer according to an embodiment of the present invention;
fig. 18a to 18b are schematic structural diagrams respectively illustrating the step 143 of the method for forming a second via hole in an array substrate according to the embodiment of the present invention;
FIG. 19 is a schematic cross-sectional view corresponding to FIG. 15 and including a second insulating layer according to an embodiment of the invention;
fig. 20 is a flowchart illustrating the overall steps of a method for forming a second via hole in an array substrate according to an embodiment of the present invention;
fig. 21a is a top view of a first via hole formed in a non-display area of an array substrate according to an embodiment of the present invention;
FIG. 21b is a schematic cross-sectional view taken along GG' of FIG. 21a according to an embodiment of the present invention;
fig. 22a is a top view of a second via hole formed in a non-display area of an array substrate according to an embodiment of the present invention;
FIG. 22b is a schematic cross-sectional view taken along the direction HH' in FIG. 22a according to an embodiment of the present invention;
fig. 23a is a top view of a second via hole formed in a non-display area of an array substrate according to an embodiment of the present invention;
fig. 23b is a schematic cross-sectional structure view along direction II' in fig. 23a according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The thicknesses and shapes of the various film layers in the drawings do not reflect the actual scale of the array substrate, and are only intended to schematically illustrate the present invention.
According to the manufacturing method of the array substrate, the array substrate and the display device provided by the embodiment of the invention, the manufacturing process of a plurality of film layers which need to etch through holes in the array substrate to form through holes is improved by optimizing the manufacturing method of the array substrate, so that not only can the photoetching process be reduced, but also the yield of products can not be reduced, and the array substrate is suitable for various types of array substrates, mainly aiming at the array substrate comprising an OLED (Organic Light-Emitting Diode) structure. The following describes the manufacturing method of the array substrate, the array substrate formed correspondingly, and the display device in detail.
In specific implementation, the arrangement of the electrodes in the array substrate is generally divided into a Middle COM structure (a common electrode is arranged between a pixel electrode and a substrate; hereinafter referred to as a first structure) and a Top COM structure (a pixel electrode is arranged between a common electrode and a substrate; hereinafter referred to as a second structure).
In addition, in the array substrate provided by the embodiment of the present invention, in addition to the first structure and the second structure, two types of through holes (a first through hole for connecting a source/drain metal layer and a second through hole for connecting a gate metal layer) may be further disposed on the array substrate of each structure, when the through holes are located in the display area, the first through hole is used for connecting the pixel electrode and the source/drain metal layer, and the second through hole is used for connecting the common electrode and the common electrode line located in the gate metal layer; when the through holes are located in the non-display area, the first through holes are used for connecting the second electrode layer and the source drain metal layer, and the second through holes are used for connecting the second electrode layer and the grid metal layer.
The first through hole is generally disposed in the display area, and the second through hole is disposed in the non-display area, but both the first through hole and the second through hole may be disposed in the display area and the non-display area, for example, the first through hole may be disposed in the non-display area to bridge different film layers; for a large-size array substrate, if the common signal at the middle position of the substrate is to be increased, bridging between the common electrode and the gate metal layer can be realized by arranging the second through hole at the middle position of the display area.
In specific implementation, the first through hole and the second through hole can be both arranged in a display area and a non-display area of the array substrate, and the first through hole and the second through hole are both required to be arranged in the array substrate, and can be arranged according to requirements.
In order to clearly illustrate how to form the first through hole and the second through hole on the display regions of different types of array substrates, the following two specific embodiments will be described in detail with reference to a process flow for forming the first through hole on the array substrate (including the first structure and the second structure) and a process flow for forming the second through hole on the array substrate (including the first structure and the second structure).
The first embodiment is as follows: and forming a first through hole in the display area on the array substrate.
In specific implementation, the array substrate has at least two structures, namely a first structure and a second structure, and the two structures are mainly different in that the first electrode layer and the second electrode layer are pixel electrodes or common electrodes, and in the display region, the first through hole is used for connecting the pixel electrodes and the source and drain electrode metal layers, so that in the array substrate of the first structure and the array substrate of the second structure, the formed first electrode layer pattern and the second electrode layer pattern have a certain difference, the manufacturing sequence and pattern of other film layers and film layers are the same, and the manufacturing method flows are basically the same, so the embodiment of the invention will introduce the process flow of forming the first through hole on the array substrate together, and will explain in combination with the figures, the array substrate of the first structure and the array substrate of the second structure are different in structure.
As shown in fig. 2, a flowchart of basic steps of a manufacturing method for forming a first through hole on an array substrate according to an embodiment of the present invention may specifically be implemented by the following steps:
step 201, forming a grid metal layer pattern, a grid insulation layer film, an active layer pattern and a source drain metal layer pattern on a substrate;
step 202, sequentially forming a planarization layer film, a first electrode layer pattern, a first insulation layer film and a photoresist pattern on the source drain metal layer pattern;
step 203, taking the photoresist pattern and the first shielding electrode in the first electrode layer pattern as shielding, sequentially carrying out dry etching processes on the first insulating layer film and the planarization layer film, and forming a first through hole by using via holes formed in the first insulating layer film, the first shielding electrode and the planarization layer film;
step 204, forming a second electrode layer pattern including a first bridging electrode on the first insulating layer film, and enabling the first bridging electrode to at least completely cover the region of the first through hole and be connected with the source drain metal layer pattern.
The above method is a process flow for forming the first through hole in the array substrate, and is applicable to the array substrate with the first structure and also applicable to the array substrate with the second structure, and in order to clearly introduce the specific process flow, the following description is made in conjunction with a top view of the array substrate and a corresponding cross-sectional view.
As shown in fig. 3, for convenience of description, only 3 × 3 pixel cells are drawn in the embodiment of the present invention, and the actual manufacturing is not limited to only 3 × 3 pixel cells, fig. 3 is a simple schematic diagram of the array substrate with the first structure, and the array substrate with the second structure may refer to the drawing, and will not be described in detail herein, and a top view of a single pixel cell of the array substrate with the second structure will be described in detail later.
As shown in fig. 4a, a partial enlarged view of P in fig. 3 is provided for the embodiment of the present invention, that is, a top view of a single pixel unit after a first via is formed on the array substrate with the first structure. Fig. 4b is a schematic structural diagram of the first electrode layer corresponding to fig. 4a according to an embodiment of the present invention; wherein the first electrode layer comprises a common electrode; as shown in fig. 4c, which is a schematic structural diagram of the second electrode layer corresponding to fig. 4a according to an embodiment of the present invention, wherein the second electrode layer includes a pixel electrode.
Correspondingly, when the array substrate has the second structure, a top view of a single pixel unit after the first through hole is formed and a schematic structural diagram of the first electrode layer and the second electrode layer may be changed to some extent.
In the drawings in the embodiments of the present invention, the first electrode layer and the second electrode layer are marked with a certain color for clearly showing the relative position relationship between the first electrode layer and the second electrode layer, but the drawings are only for convenience of description and are not used to limit the present invention. It should be understood by those skilled in the art that, in the actual manufacturing process of the array substrate, both the first electrode layer and the second electrode layer can be made of transparent materials.
As shown in fig. 5a, it is a top view of a single pixel unit after a first through hole is formed on an array substrate with a second structure according to an embodiment of the present invention, that is, a top view of an array substrate with a second structure corresponding to fig. 4 a; fig. 5b is a schematic structural diagram of the first electrode layer corresponding to fig. 5a according to an embodiment of the present invention; wherein the first electrode layer comprises a pixel electrode; as shown in fig. 5c, a schematic structural diagram of a second electrode layer corresponding to fig. 5a is provided in the embodiment of the present invention, where the second electrode layer includes a common electrode.
In order to clearly show the position relationship between the electrode layers in the top view, the insulating layers (such as the gate insulating layer, the first insulating layer, etc.) are not shown in each top view given in the embodiments of the present invention, and the specific arrangement positions thereof are indicated in the corresponding cross-sectional views.
In order to clearly illustrate the patterns and the positional relationship formed by each film layer after the first through hole is formed, the embodiment of the present invention respectively provides cross-sectional views of two different types of array substrates after the first through hole is formed, as shown in fig. 6, a schematic cross-sectional structure along the direction C-C' in fig. 4a provided for the embodiment of the present invention is used to describe a process flow for forming the first through hole on the array substrate with the first structure. Fig. 7 is a schematic cross-sectional view taken along the direction D-D' in fig. 5a according to an embodiment of the present invention, for describing a process flow of forming a first via hole on an array substrate having a second structure.
A process flow of forming the first via hole on the array substrate of the first structure and the second structure is described below with reference to fig. 4a to 4c, 5a to 5c, 6 to 7, and 8a to 8 k; fig. 8a to 8k are schematic structural diagrams respectively illustrating steps of a manufacturing method for forming a first via on an array substrate according to an embodiment of the present invention after the steps are performed.
In a specific implementation, when the step 201 is implemented, the finally formed structure is the same regardless of the array substrate of the first structure or the array substrate of the second structure. As shown in fig. 8a, a gate metal layer pattern is formed on a substrate 100 by a single patterning process (i.e., a first photolithography process); then, a whole gate insulating layer 102 film is formed on the gate metal layer 101 pattern. Then, a one-step patterning process (i.e., a second photolithography process) is performed on the gate insulating layer 102 to simultaneously form an active layer 103 pattern and a source/drain metal layer 104 pattern, i.e., a half-mask process is used to form the structure shown in fig. 8a, except that an active layer is disposed between the source metal layer and the drain metal layer in fig. 4a, and the material of the active layer is also retained below all the source/drain metal layers.
In addition to the structure shown in fig. 8a, a photolithography process may be added, that is, the active layer 103 pattern and the source/drain metal layer 104 pattern are respectively manufactured by different photolithography processes, and at this time, only the active layer portion disposed between the source metal layer and the drain metal layer may be remained, so as to form the structure shown in fig. 8 b. Since the purpose of the method for manufacturing an array substrate according to the embodiment of the present invention is mainly to reduce the photolithography process, the following description of the present invention will be continued only by taking fig. 8a as an example, and the structure of fig. 8b is similar to that, which can be referred to the description of fig. 8 a.
In a specific implementation, when the step 202 is implemented, an entire planarization layer 105 film is formed on the source/drain metal layer 104 pattern shown in fig. 8a, and the array substrate with both structures forms the structure shown in fig. 8 c.
Then, a first electrode layer 106 is patterned on the planarization layer 105 by a single patterning process (i.e., a third photolithography process); at this time, the patterns of the first electrode layer 106 formed are different for different types of array substrates.
When the array substrate has the first structure, as shown in fig. 8d, in order to shield the common electrode from the subsequent dry etching planarization layer and other film layers, preferably, the first electrode layer 106 pattern includes the common electrode CE and the first shielding electrode 106a1And the first shielding electrode 106a1The structure is an independent structure which is arranged on the same layer as the common electrode CE and is mutually disconnected; the first shielding electrode 106a can be formed by combining the first through hole with a generally circular structure1The first through hole is arranged in a ring structure, as shown in fig. 4b, but may be arranged in other shapes as required, and is not limited herein.
When the array substrate has the second structure, as shown in fig. 8e, in order to shield the pixel electrode from the subsequent dry etching planarization layer and other film layers, preferably, the first electrode layer 106 pattern includes the pixel electrode PE and the first shielding electrode 106a1And the first shielding electrode 106a1Is an integral structure connected to the pixel electrode PE. I.e. to form the structure shown in fig. 5 b.
Then, a whole layer of the first insulating layer 107 film and the photoresist 108 is formed on the first electrode layer 106 pattern, and a photoresist pattern is formed by using a one-step patterning process (i.e., a fourth photolithography process), when the array substrate has a first structure, a structure as shown in fig. 8f is formed, and via holes 108v formed in the photoresist pattern 1081Is located on the first shielding electrode 106a1Via hole 106v formed thereon1Upper part ofAnd (4) preparing. When the array substrate has the second structure, the structure shown in fig. 8g is formed, and the via hole 108v formed in the photoresist pattern 1081Is located on the first shielding electrode 106a1Via hole 106v formed thereon1Above (b).
Wherein, for clarity of illustration of the position of the via formed in each film layer, the embodiment of the invention provides the figure with the reference number with v to denote the via, and the via 108v in fig. 8f1And via 106v1Are marked on the walls of the vias, and the via numbers in subsequent figures are similar thereto.
Preferably, as shown in fig. 9, a flowchart of a step of forming a via hole of a first through hole in each film layer according to an embodiment of the present invention is provided, where the flowchart is applicable to an array substrate of a first structure and is also applicable to an array substrate of a second structure, and only the patterns of the first electrode layer formed in the two structures are different. Therefore, when introduced herein, the first structure and the second structure are not distinguished, but rather, the figures are provided for the two structures, respectively. The step 203 may be implemented by the following steps:
step 2031, forming a via hole for forming a first through hole in the first insulating layer film by using the photoresist pattern as a mask and performing a dry etching process on the first insulating layer film, wherein the via hole formed in the first insulating layer film can expose a part of the first shielding electrode;
step 2032, using the photoresist pattern and the exposed portion of the first shielding electrode as shielding, and performing dry etching process on the planarization layer film to form a via hole for forming the first through hole in the planarization layer film.
In specific implementation, when the step 2031 is implemented, the photoresist pattern 108 is used as a mask to form a pattern of the first insulating layer 107 thin film, since the material of the first insulating layer 107 thin film is generally an organic material, a dry etching process and a gas used for etching can be directly applied to the first insulating layer 107 thin film, and details will be described later, the forming of the pattern of the first insulating layer 107 thin film mainly includes forming a via hole 107v for forming a first via hole in the first insulating layer 107 thin film1And is alsoIn order to make the first shielding electrode function as a better shielding effect, it is necessary to make the via hole 107v formed in the thin film of the first insulating layer 107 at the time of dry etching1A part of the first shielding electrode can be exposed. When the array substrate is in the first structure, a structure as shown in fig. 8h can be formed; when the array substrate has the second structure, a structure as shown in fig. 8i may be formed.
In specific implementation, when the step 2032 is implemented, the photoresist pattern 108 and the exposed portion of the first shielding electrode are used as shielding, a dry etching process is performed on the planarization layer 105 film, and a via hole 105v for forming the first through hole is formed in the planarization layer film1. Wherein a via hole 107v is formed on the first insulating layer 107 film1On the first shielding electrode 106a1Via hole 106v formed thereon1And via holes 105v formed in the planarization layer 105 film1Together forming a first through hole. In the subsequently fabricated second electrode layer 109 pattern, the first bridging electrode at least completely covers the region where the first through hole is located, and in order to prevent the first bridging electrode from breaking during fabrication, the apertures constituting the first through hole need to be sequentially reduced from top to bottom, that is, the via hole 107v1Via 106v1And via 105v1The hole diameters are sequentially reduced to form a step-shaped through hole. When the array substrate is in the first structure, a structure as shown in fig. 8j can be formed; when the array substrate is in the second structure, a structure as shown in fig. 8k can be formed.
In addition, in the prior art, a photosensitive material is used to form the planarization layer, so that the planarization layer needs to be formed by a single photolithography process or an ashing process to form the pattern of the planarization layer. In the invention, in order to simplify the manufacturing process, the material for manufacturing the planarization layer is improved, and the material which can be directly etched through a dry etching process is adopted, and preferably, the material of the planarization layer film comprises organic silicon resin. Therefore, the planarization layer pattern on the array substrate provided by the embodiment of the invention can be formed by adopting a dry etching process as the first insulating layer film and the like, so that a photoetching process is saved.
Therefore, the array substrate provided by the embodiment of the invention is the via hole on the first insulating layer film and the planarization layer film which are formed after the first electrode layer pattern and the whole first insulating layer film are manufactured, the etching process of the hole trepanning in the prior art is not adopted, and the first electrode layer pattern comprises the first shielding electrode which is used for shielding when the planarization layer is subjected to the dry etching process, so that the manufacturing method can meet the etching requirement without increasing the aperture of the via hole in the planarization layer, and further can improve the aperture opening ratio and the yield of the subsequent manufacturing process.
In a specific implementation, when the array substrate is in the first structure in the step 204, the structure shown in fig. 6 may be formed when the first through hole T is formed1Then, the photoresist pattern is removed, a whole second electrode layer 109 film is formed on the first insulating layer 107 film, a second electrode layer 109 pattern is formed by using a one-step patterning process (i.e., a fifth photolithography process), and the second electrode layer 109 pattern includes the pixel electrode PE and the first bridge electrode 109a1(ii) a Since the first via hole serves to connect the pixel electrode PE and the source-drain metal layer 104, the first bridge electrode 109a1Is a unitary structure connected to the pixel electrode PE even though the first bridge electrode 109a1At least the region of the first via hole is completely covered and is pattern-connected with the source-drain metal layer 104.
When the array substrate has the second structure, the structure shown in fig. 7 can be formed after the first through hole T is formed1Thereafter, the photoresist pattern is removed, and the second electrode layer 109 is patterned over the first insulating layer 107, wherein the second electrode layer 109 includes the first bridge electrode 109a1Since the first via hole serves to connect the pixel electrode PE and the source-drain metal layer 104, the first bridge electrode 109a1As shown in fig. 5c, which is a separate structure disposed at the same layer as the common electrode CE and disconnected from each other. At the same time, the bridge electrode 109a1(i.e. the circled part in fig. 5 c) covers at least the first through hole T completely1The region of the' site.
In summary, in the manufacturing method of the array substrate of the present invention, the array substrate can be manufactured only by five photolithography processes (the gate metal layer, the active layer, the source drain layer, the first electrode layer, the first insulating layer, the planarization layer, the second insulating layer, and the second electrode layer, respectively).
As can be seen from the above description of the basic process flow for forming the first through holes on the array substrate, the array substrate of the first structure and the array substrate of the second structure are only that the first electrode layer pattern and the second electrode layer pattern formed by the array substrate of the first structure have a certain difference, and the other film layers, the manufacturing sequence and the pattern of each film layer, and the like are the same.
In specific implementation, a first insulating layer film is generally disposed between the source/drain metal layer 104 and the planarization layer 105. As shown in fig. 10, which is a schematic cross-sectional structure corresponding to fig. 5 and including the second insulating layer according to the embodiment of the present invention, after step 201 is performed and before step 202 is performed, the method further includes: a second insulating layer 110 film is formed on the source-drain metal layer 104 pattern.
Specifically, after the source/drain metal layer 104 is patterned, a whole second insulating layer 110 film is formed above the source/drain metal layer, and in the process of patterning the second insulating layer 110 film, since the second insulating layer 110 film is disposed below the planarization layer 105, after the planarization layer film is subjected to a dry etching process, the second insulating layer 110 film is also subjected to a dry etching process, so that the second electrode pattern can be connected to the source/drain metal layer 104 through the formed first through hole.
To this end, inThe basic steps of the method for forming the first through hole on the array substrate are described, but in the specific implementation process, the first insulating layer film and the planarization layer film are dry etched, because the first shielding electrode 106a is adopted1The masking may cause an excessively large aperture etched on the planarization layer 105 film, and the first shielding electrode 106a1Over-etched via 106v1Is smaller than the via hole 105v etched on the planarization layer 1051The first shielding electrode 106a at the area of the via hole1Protrudes from the planarization layer 105 to form the structure shown in fig. 11, which is a schematic structural diagram before the wet etching process is used to etch the first electrode layer pattern according to the embodiment of the present invention; namely, the projection 106t (the encircled portion of the oval broken line in the figure) is formed.
Due to the structure shown in fig. 11, when the second electrode layer 109 is fabricated subsequently, it is easy to break at the protruding position, and preferably, after step 203 and before step 204, the method further includes: removing part of the exposed first shielding electrode 106a by wet etching1So that the first shielding electrode 106a1Via hole 106v in (c)1The aperture is larger than the aperture 105v of the via hole in the planarization layer 105 film1And (4) the aperture.
In the prior art, in order to reduce the photolithography process of the TFT substrate to five photolithography processes, the electrode and the planarization layer are performed by using one photolithography process, since the planarization layer uses a dry etching process, a protrusion 13t as shown in fig. 1b is usually formed between the pattern of the first electrode layer 13 and the pattern of the planarization layer 14, and in order to increase the side etching amount of the first electrode layer 13, the surface of the first electrode layer 13 is usually treated by using a hydrogen plasma bombardment process after the first electrode layer 13 pattern is formed and before the second insulating layer 17 is formed, but this causes the surface of the first electrode layer 13 to be reduced, and the transmittance to be reduced. In the method for manufacturing the array substrate provided in the embodiment of the invention, after a whole layer of the first insulating layer 107 film is formed on the first electrode layer 106 pattern, the first through hole is etched, and after the first through hole is etched, the first shielding electrode 106a is covered1Is protruded from the flat surfaceThe protrusion 106t of the layer 105 is formed by wet etching, so that the protrusion 106t can be effectively removed without affecting the first shielding electrode 106a1And the first electrode 106.
Since the structure shown in fig. 12 is generally formed after the wet etching process is adopted, the schematic structural diagram is provided after the first electrode layer pattern is etched by adopting the wet etching process according to the embodiment of the present invention; although the first shielding electrode 106a is removed at the region where the via hole is located1A via hole 107v protruding from the planarization layer 105 but on the first insulating layer 107 film1Aperture and first shielding electrode 106a1Via hole 106v in (c)1In order to make the finally formed first through hole be a step-shaped through hole, it is preferable that, after the wet etching process is performed and before step 204, the method further includes: a dry etching process is applied to the first insulating layer 107 film. Namely, the dry etching process is continued to be performed on the first insulating layer 107 film to enlarge the via hole 107v1The aperture of (a) is formed as shown in fig. 8j, which is beneficial to the climbing of the electrode layer material when the second electrode layer 109 is manufactured subsequently.
In order to clearly illustrate the method for forming the first through hole on the array substrate according to the embodiment of the present invention, as shown in fig. 13, an overall step flowchart of the method for forming the first through hole on the array substrate according to the embodiment of the present invention is applicable to an array substrate with a first structure and is also applicable to an array substrate with a second structure, and the overall step flowchart specifically includes the following steps:
step 1301, forming a grid metal layer pattern, a grid insulation layer film, an active layer pattern and a source drain metal layer pattern on a substrate;
step 1302, sequentially forming a planarization layer film, a first electrode layer pattern, a first insulation layer film and a photoresist pattern on the source drain metal layer pattern;
step 1303, forming a via hole for forming a first through hole in the first insulating layer film by using the photoresist pattern as a mask and adopting a dry etching process on the first insulating layer film, wherein the via hole formed in the first insulating layer film can expose part of the first shielding electrode;
step 1304, forming a via hole for forming a first through hole in the planarization layer film by using the photoresist pattern and the exposed part of the first shielding electrode as shielding and adopting a dry etching process for the planarization layer film;
step 1305, removing a part of the exposed first shielding electrode by adopting a wet etching process so that the aperture of the via hole in the first shielding electrode is larger than that of the via hole in the planarization layer film;
step 1306, a dry etching process is adopted for the first insulating layer film;
step 1307, a second electrode layer pattern including a first bridging electrode is formed on the first insulating layer film, and the first bridging electrode at least completely covers the area of the first via hole and is connected with the source drain metal layer pattern.
After the process flow of the first through hole is introduced, the process flow of forming the second through hole on the array substrate is further introduced, and actually, in the manufacturing process, if the first through hole and the second through hole exist on the array substrate at the same time, the two through holes are generally manufactured at the same time to reduce the manufacturing processes, but for the sake of clarity, the embodiment of the present invention separately describes the manufacturing processes of the two through holes.
Example two: and forming a second through hole in the display area on the array substrate.
In practical implementation, as in the first embodiment, the second embodiment also describes a structure in which the second through holes are formed in the display regions on the array substrate with the first structure and the array substrate with the second structure, respectively. Since the first electrode layer pattern and the second electrode layer pattern formed in the array substrate of the first structure and the array substrate of the second structure have a certain difference, and the other film layers, the manufacturing sequence and the pattern of each film layer, and the like are the same, the manufacturing method flows are basically the same, and therefore, the formation of the second through hole is not described too much here. It is only explained which of the first structure array substrate and the second structure array substrate are different in structure when the second via hole is formed mainly with reference to the drawings.
As shown in fig. 14, a flowchart of basic steps of a manufacturing method for forming a second through hole on an array substrate according to an embodiment of the present invention may specifically be implemented by the following steps:
step 141, forming a gate metal layer pattern, a gate insulating layer film, an active layer pattern and a source drain metal layer pattern on the substrate;
step 142, sequentially forming a planarization layer film, a first electrode layer pattern, a first insulation layer film and a photoresist pattern on the source drain metal layer pattern;
step 143, while forming the first through hole, sequentially performing a dry etching process on the first insulating layer film, the planarization layer film and the gate insulating layer film by using the photoresist pattern and the second shielding electrode in the first electrode layer pattern as shielding, and forming a second through hole by using the via holes formed in the first insulating layer film, the second shielding electrode, the planarization layer film and the gate insulating layer film;
step 144, forming a second electrode layer pattern including a second bridge electrode on the first insulating layer film, and connecting the second bridge electrode with the gate metal layer pattern while at least completely covering the region of the second via hole.
The above method is a process flow for forming the second through hole in the array substrate, and is suitable for the array substrate with the first structure and also suitable for the array substrate with the second structure, and in order to clearly introduce the specific process flow, the following description is made in conjunction with a top view of the array substrate and a corresponding cross-sectional view.
As shown in fig. 4a, the circle position at the lower left corner is the formed second through hole, in the figure, 101' is the common electrode line located in the gate metal layer, and the connection position between the common electrode line and the second through hole is provided with a circle portion (assumed as a connection portion) that is made at the same layer and protrudes out of the common electrode line, so that the common electrode line is connected to the common electrode through the connection portion. Of course, the common electrode line may be provided in other structures at the connection point with the second through hole as needed. For example, the position of the connecting portion may be located not only on one side of the common electrode line, but also directly above the common electrode line, and the specific position may be set according to actual needs; alternatively, if the width of the common electrode line 101' is sufficiently wide, a portion of the common electrode line may be directly connected to the common electrode without providing a connection portion. Fig. 15 is a schematic cross-sectional view taken along the direction E-E' in fig. 4a according to an embodiment of the present invention, and is used to describe a process flow for forming a second via on the array substrate with the first structure.
Correspondingly, as shown in fig. 5a, the circle position at the lower left corner is the formed second through hole, and the arrangement manner of the common electrode line 101' is the same as that in fig. 4a, and is not repeated herein. Fig. 16 is a schematic cross-sectional view taken along the direction F-F' in fig. 5a according to an embodiment of the present invention, for describing a process flow of forming a second via hole in an array substrate with a second structure.
In practical implementation, steps 141 and 142 are performed similarly to the first embodiment, except that the pattern of the first electrode layer 106 is different, and the rest can be referred to the description of steps 201 and 202 in the first embodiment.
When the array substrate has the first structure, as shown in fig. 15, in order to make the common electrode serve as a shield for each film layer such as a subsequent dry etching planarization layer, it is preferable that, in combination with fig. 4a and 15, the first electrode layer 106 includes a second shield electrode 106a2And the second shielding electrode 106a2For a unitary structure connected to the common electrode CE, wherein the position of the common electrode is not shown in fig. 15, see fig. 4 b.
When the array substrate has the second structure, as shown in fig. 16, in order to make the pixel electrode serve as a mask for each film layer such as a subsequent dry etching planarization layer, it is preferable that, in combination with fig. 5a and 16, the first electrode layer 106 pattern includes a second mask electrode 106a2And the second shielding electrode 106a2A separate structure disposed at the same layer as the pixel electrode PE and disconnected from each other, wherein the position of the pixel electrode is not shown in fig. 16, can be seen in fig. 5 b; and the second shielding electrode 106a can be arranged in a circular structure in combination with the second through hole2Is arranged to surround the second channelThe annular structure of the hole is shown in fig. 5 a-5 b, but of course, other shapes can be provided according to the requirement, and the invention is not limited herein.
Then, a whole first insulating layer 107 film and a photoresist 108 are formed on the first electrode layer 106 pattern, which may be specifically described in the first embodiment, and will not be repeated herein.
In specific implementation, since step 143 is mainly used to form a second through hole, and the second through hole is substantially the same as each film etched by the first through hole, the process of performing step 143 may be performed at the same time as step 203, that is, the first through hole and the second through hole are simultaneously etched, preferably, as shown in fig. 17, a flowchart of a step for forming a via hole of the second through hole in each film provided by an embodiment of the present invention is similar to the embodiment, and step 143 may be implemented by specifically using the following steps:
step 1431, while forming the first through hole, forming a via hole for forming the second through hole in the first insulating layer film by using the photoresist pattern as a mask and performing a dry etching process on the first insulating layer film, where a part of the second mask electrode can be exposed from the via hole formed in the first insulating layer film;
step 1432, forming a via hole for forming a second via hole in the planarization layer film by using the photoresist pattern and the exposed part of the second shielding electrode as shielding and adopting a dry etching process for the planarization layer film;
step 1433, a via hole for forming the second via hole is formed in the gate insulating film by performing a dry etching process on the gate insulating film, using the photoresist pattern and the exposed portion of the second shielding electrode as shielding.
Since the step 143 is implemented in a manner similar to that of the step 203, except that the step 1433 is executed in comparison with the first embodiment, the gate insulating film needs to be further etched, but actually, the material of the gate insulating film is similar to that of the first insulating film, and the etching process may be performed by using the same etching gas as that of the first insulating film.
Specifically, when the array substrate has the first structure, after step 143, the array substrate can be shapedWith the structure shown in fig. 18a, when the array substrate is the second structure, after step 143 is executed, the structure shown in fig. 18b may be formed, and fig. 18a to 18b are schematic structural diagrams after step 143 is executed in the manufacturing method for forming the second via hole on the array substrate according to the embodiment of the present invention; wherein the via hole 107v is formed on the first insulating layer 107 film2A via hole 106v formed on the first shielding electrode2Via hole 105v formed in planarization layer 105 film2And a via hole 102v formed in the gate insulating layer 102 film2Together form a second through hole T2(as shown in FIG. 18 a) or a second through hole T2' (as shown in FIG. 18 b); and via 107v2Via 106v2Vias and vias 102v2The hole diameters are sequentially reduced to form a step-shaped through hole.
In addition, the properties of the material of the planarization layer in the second embodiment are the same as those in the first embodiment, and specific reference may be made to the description of the first embodiment, which is not repeated herein.
In a specific implementation, when the step 144 is implemented, the second electrode layer pattern is mainly formed, and a specific forming manner is the same as that of the first embodiment, which can be referred to as the description of the first embodiment, and will not be repeated herein. Only the differences in the patterns of the second electrode layer formed will be briefly described below.
When the array substrate is in the first structure, the structure shown in fig. 15 can be formed; the second electrode layer pattern includes a second bridge electrode 109a2(ii) a Since the second via hole serves to connect the common electrode CE to the common electrode line at the gate metal layer, the second bridge electrode 109a2Is a separate structure disposed at the same layer as the pixel electrode PE and disconnected from each other even though the second bridge electrode 109a2And the area completely covers the second through hole and is connected with the common electrode wire positioned on the grid metal layer.
When the array substrate is in the second structure, the structure shown in fig. 16 can be formed; the second electrode layer pattern includes a second bridge electrode 109a2(ii) a Since the second via hole serves to connect the common electrode CE with the gate metal layer pattern 101Thus, the second bridge electrode 109a2Is a unitary structure connected to the common electrode CE even though the second bridge electrode 109a2And the area completely covers the second through hole and is connected with the common electrode wire positioned on the grid metal layer.
In summary, the array substrate in the second embodiment of the present invention can be manufactured by only five photolithography processes (i.e., the gate metal layer, the active layer, the source drain layer, the first electrode layer, the first insulating layer, the planarization layer, the second insulating layer, and the second electrode layer), and compared with the prior art, since the via holes in the first insulating layer thin film and the planarization layer thin film can be formed by only one photolithography process in the present invention, the influence caused by insufficient alignment precision due to different photolithography processes can be reduced, which not only reduces the photolithography process, but also does not reduce the yield of the product.
Similar to the embodiments, the following description only takes the array substrate with the first structure as an example, and the array substrate with the second structure is similar to the first structure, and the description thereof will not be repeated.
In a specific implementation, a second insulating film may be further disposed between the gate insulating layer 102 and the planarization layer 105 in the second embodiment of the present invention. As shown in fig. 19, which is a schematic cross-sectional structure corresponding to fig. 15 and including the second insulating layer according to the embodiment of the present invention, after step 141 is performed and before step 142 is performed, the method further includes: a second insulating layer 110 film is formed on the gate insulating layer 102 pattern.
The specific process of forming the second insulating layer 110 and then forming the via hole of the second through hole is similar to that of the first embodiment, and reference may be made to the description of the first embodiment, which is not repeated herein.
So far, the basic step flow of the manufacturing method for forming the second through hole on the array substrate is described, but in the specific implementation process, the first insulating layer film and the planarization layer film are subjected to the dry etching process, because the first shielding electrode 106a is adopted2Masking is performed, and thus the planarization layer 105 may be made thinThe aperture of the etching on the film is too large, so that the first shielding electrode 106a2Over-etched via 106v2Is smaller than the via hole 105v etched on the planarization layer 1052The aperture of (2) can make the first shielding electrode 106a at the area of the via hole2Protruding from the planarization layer 105, a protruding portion is formed.
As in the first embodiment, the second embodiment of the present invention may also use a wet etching process to remove the protruding portion. After step 143, before step 144, further comprising: and removing part of the exposed second shielding electrode by adopting a wet etching process so as to enable the aperture of the via hole in the second shielding electrode to be larger than that of the via hole in the planarization layer film. For details, reference may be made to the description of the first embodiment, and details are not repeated herein.
In order to clearly illustrate the method for forming the second through hole on the array substrate according to the embodiment of the present invention, as shown in fig. 20, an overall step flowchart of the method for forming the second through hole on the array substrate according to the embodiment of the present invention is applicable to an array substrate with a first structure and is also applicable to an array substrate with a second structure, and the overall step flowchart specifically includes the following steps:
step 2001, forming a gate metal layer pattern, a gate insulating layer film, an active layer pattern and a source drain metal layer pattern on a substrate;
step 2002, sequentially forming a planarization layer film, a first electrode layer pattern, a first insulation layer film and a photoresist pattern on the source/drain electrode metal layer pattern;
step 2003, forming a first through hole, and forming a via hole for forming a second through hole in the first insulating layer film by using the photoresist pattern as a shielding layer and adopting a dry etching process for the first insulating layer film, wherein a part of the second shielding electrode can be exposed from the via hole formed in the first insulating layer film;
step 2004, forming a via hole for forming a second via hole in the planarization layer film by using the photoresist pattern and the exposed part of the second shielding electrode as shielding and adopting a dry etching process for the planarization layer film;
step 2005, forming a via hole for forming a second via hole in the gate insulating layer film by dry etching the gate insulating layer film with the photoresist pattern and the exposed portion of the second shielding electrode as shielding;
step 2006, removing a part of the exposed second shielding electrode by using a wet etching process, so that the aperture of the via hole in the second shielding electrode is larger than that of the via hole in the planarization layer film;
step 2007, a dry etching process is adopted for the first insulating layer film and/or the gate insulating layer film;
step 2008, forming a second electrode layer pattern including a first bridging electrode on the first insulating layer film, and enabling the first bridging electrode to at least completely cover the region of the first through hole and be connected with the source drain metal layer pattern.
Example three: and forming a first through hole and a second through hole in a non-display area on the array substrate.
In a specific implementation, in the non-display area of the array substrate, the first through hole and the second through hole are formed in the same structure regardless of the first structure or the second structure. In addition, the first through hole and the second through hole may be disposed in the bonding region, and the specific manufacturing process flow is similar to that of the first embodiment and the second embodiment, which can be referred to in the above two embodiments.
As shown in fig. 21a, a top view of forming a first through hole in a non-display area of an array substrate according to an embodiment of the present invention is provided; fig. 21b is a schematic cross-sectional view taken along GG' in fig. 21a according to an embodiment of the present invention.
As shown in fig. 22a, a top view of forming a second through hole in a non-display area of an array substrate according to an embodiment of the present invention is provided; fig. 22b is a schematic cross-sectional view taken along HH' in fig. 22a according to an embodiment of the present invention.
Specifically, the second electrode layer 109 pattern generally provided in the non-display region is a separate structure provided in the same layer as the common electrode pattern or the pixel electrode pattern and disconnected from each other. And is disposed in the non-display areaA shielding electrode 106a1The pattern is only a circle of shielding structure surrounding the first through hole and is arranged in the same layer with the common electrode pattern or the pixel electrode pattern; similarly, the second shielding electrode 106a disposed in the non-display region2The pattern is only a circle of shielding structures surrounding the second through hole and is arranged in the same layer with the common electrode pattern or the pixel electrode pattern.
In addition, the first via and the second via may also be used to perform layer change jumpers in the non-display area, as shown in fig. 23a, which is a top view of forming the second via in the non-display area of the array substrate according to the embodiment of the present invention; fig. 23b is a schematic cross-sectional view along direction II' in fig. 23a according to an embodiment of the present invention.
For the dry etching processes mentioned in the first to third embodiments, different etching gases may be used for etching, which will be described in detail below. In addition, the following description of the etching gas is applicable to the above three embodiments.
When the first through hole and the second through hole are formed, a dry etching process needs to be performed on part or all of the first insulating layer film, the planarization layer film, the second insulating layer film and the gate insulating layer film, and then through holes for forming the first through hole and the second through hole are formed on the film layers. According to the difference of the film materials, two types of etching gases are respectively adopted for dry etching, wherein the first insulating layer film, the second insulating layer film and the grid insulating layer film adopt the same type of etching gas (namely, a first etching gas), and the planarization layer film adopts the other type of etching gas (namely, a second etching gas).
Specifically, since the first insulating layer film, the second insulating layer film and the gate insulating layer film are generally made of silicon nitride materials, preferably, the first etching gas includes carbon tetrafluoride and oxygen; alternatively, the first etching gas comprises sulfur hexafluoride and oxygen. The silicon nitride material is reacted with oxygen to form silicon oxide material, which may be etched with carbon tetrafluoride or sulfur hexafluoride gas.
In addition, the three film layers can be etched separately or simultaneously by using the same type of etching gas, preferably, the first etching gas is used for carrying out one-time dry etching process on the first insulating layer film, and the first etching gas is used for carrying out one-time dry etching process on the second insulating layer film and the grid insulating layer film simultaneously; or, simultaneously carrying out one-time dry etching process on the first insulating layer film, the second insulating layer film and the grid insulating layer film by using the first etching gas.
Since the planarization layer film provided by the embodiment of the invention is made of the organic silicon resin, the carbon tetrafluoride or the sulfur hexafluoride is not required to be introduced, the carbon tetrafluoride or the sulfur hexafluoride is directly used for dry etching the planarization layer film, and preferably, the second etching gas is used for dry etching the planarization layer film. The second etching gas comprises carbon tetrafluoride or sulfur hexafluoride.
In summary, the first etching gas provided by the embodiment of the present invention only adds more oxygen than the second etching gas, so that it is actually equivalent to sequentially forming via holes on the first insulating layer thin film, the planarization layer thin film, the second insulating layer thin film and the gate insulating layer thin film through one dry etching process, and only carbon tetrafluoride (or sulfur hexafluoride) and oxygen need to be introduced when etching the first insulating layer thin film, the second insulating layer thin film and the gate insulating layer thin film, and only carbon tetrafluoride (or sulfur hexafluoride) needs to be introduced when etching the planarization layer thin film; meanwhile, the selective etching ratio can be adjusted by adjusting the flow of the introduced oxygen.
As will be understood by those skilled in the art, in the manufacturing process of the array substrate, besides the process steps disclosed in the embodiments of the present invention, other well-known process steps (for example, a process for specifically forming various film layers on the array substrate, etc.) are also included. In describing the method of fabricating the array substrate of the present embodiment, descriptions of these well-known process steps are omitted so as not to obscure the core process steps of the embodiments of the present invention.
Based on the same inventive concept, embodiments of the present invention further provide an array substrate, and since the principle of solving the problem of the array substrate is similar to the method for manufacturing the array substrate provided by the embodiments of the present invention, the implementation of the array substrate may refer to the implementation of the method for manufacturing the array substrate, and repeated details are not repeated.
As shown in fig. 6 or 7, the array substrate includes: a gate metal layer 101 pattern, a gate insulating layer 102, an active layer 103 pattern, a source drain metal layer 104 pattern, a planarization layer 105 film, a first electrode layer 106 pattern, a first insulating layer 104 film, and a second electrode layer 108 pattern, which are sequentially disposed on a substrate 100; wherein, the first shielding electrode 106a is arranged in the first insulating layer 104 film and the first electrode layer 106 pattern1And the via hole formed in the planarization layer 105 film constitute a first through hole; a first bridge electrode 109a included in the second electrode layer 109 pattern1At least completely cover the first through hole T1(or T)1') and the first shielding electrode 106a respectively1Pattern-connected to the source and drain metal layer 104.
In addition to the first through-holes shown in fig. 6 and 7, second through-holes may be formed. As shown in FIGS. 15 and 16, it is preferable that the second shielding electrode 106a is formed in the first insulating layer 107 film, the first electrode layer 106 pattern2The second via hole is formed by the via holes formed in the planarization layer 105 film and the gate insulating layer 102 film; a second bridge electrode 109a included in the second electrode layer 109 pattern2At least completely covering the second via hole region and respectively connected with the second shielding electrode 106a2And pattern-connected to the gate metal layer 101.
In implementation, since the array substrate generally has two structures (i.e., the first structure and the second structure), the structures of the first through hole and the second through hole formed on the array substrate of each structure are different.
When the first through hole (as shown in fig. 6) and the second through hole (as shown in fig. 15) are formed on the array substrate having the first structure, it is preferable that the first electrode layer 106 includes a common electrode CE pattern and a first shielding electrode 106a1Pattern and second shielding electrode 106a2A pattern; the second electrode layer 109 pattern includes a pixel electrode PE pattern, a first bridge electrode 109a1Pattern and second bridge electrode 109a2A pattern; the common electrode CE pattern has a first opening region KK and a first shielding electrode 106a1The pattern is disposed in the first opening region KK, and the aperture of the first opening region is larger than that of the first shielding electrode 106a1Vias in pattern 106v1The diameter of the hole; second shielding electrode 106a2The pattern is an integral structure connected with the common electrode CE pattern, and the second shielding electrode 106a2The pattern includes via holes 106v constituting second through holes2(ii) a The first bridge electrode 109a1The pattern is an integral structure connected with the PE pattern of the pixel electrode; the second bridge electrode 109a2The pattern is disconnected from the common electrode CE pattern.
In the prior art, a structure as shown in fig. 1a is generally formed, a shielding electrode is not disposed on the first electrode layer 13, and in order to prevent the edge of the first electrode layer 13 from being overlapped with the second electrode layer 18, an opening on the first electrode layer 13 is generally disposed to be larger, and the larger opening is not conducive to climbing of an electrode material when the second electrode layer 18 is subsequently fabricated. In the present invention, the first electrode layer pattern includes a common electrode pattern, a first shielding electrode pattern and a second shielding electrode pattern, i.e. the structures shown in fig. 4 a-4 c, and the first electrode layer pattern includes a circular ring-shaped shielding electrode 106a1Because of the first shielding electrode 106a1The aperture of the via hole arranged in the pattern does not need to be very large, and the stepped first through hole can be better formed.
When the first through hole (as shown in fig. 7) and the second through hole (as shown in fig. 16) are formed on the array substrate having the second structure, it is preferable that the first electrode layer 106 includes a pixel electrode PE pattern and a first shielding electrode 106a1Pattern and second shielding electrode 106a2A pattern; the second electrode layer 109 pattern includes a common electrode CE pattern, a first bridge electrode 109a1Pattern and second bridge electrode 109a2A pattern; first shielding electrode 106a1The pattern is an integral structure connected with the pixel electrode PE pattern, and the first shielding electrode 106a1The pattern includes via holes 106v constituting first through holes1(ii) a Second shielding electrode 106a2The pattern is disconnected from the pattern of the pixel electrode PE, and the second shielding electrode 106a2The pattern includes via holes 106v constituting second through holes2(ii) a The first bridge electrode 109a1The pattern is disconnected from the common electrode PE pattern; the second bridge electrode 109a2The pattern is an integral structure connected to the common electrode CE pattern.
In the prior art, in the array substrate with the second structure, the pixel electrode is not generally provided with an opening above the source/drain metal layer, but the pixel electrode is directly connected with the source/drain metal layer. In the present invention, the structure shown in fig. 5a to 5c is formed, and since the pixel electrode is not directly connected to the source-drain metal layer in the present invention, but is connected to the source-drain metal layer through the first bridging electrode included in the common electrode, an opening needs to be provided above the source-drain metal layer in the pixel electrode, so that the first bridging electrode can directly contact with the source-drain metal layer.
Based on the same inventive concept, the embodiment of the invention further provides a display device, and the display device comprises any one of the array substrates provided by the embodiment of the invention. Because the principle of the display device for solving the problems is similar to that of the array substrate provided by the embodiment of the invention, the implementation of the display device can refer to the implementation of the array substrate, and repeated details are not repeated.
In summary, the embodiments of the present invention have the following beneficial effects:
1. the manufacturing method of the array substrate is optimized, the manufacturing process of a plurality of film layers needing to be etched with through holes to form through holes in the array substrate is improved, a whole layer of planarization layer film is required to be formed on a source drain electrode metal layer pattern, a first electrode layer pattern comprising a first shielding electrode is formed on the planarization layer film through a photoetching process, then a photoresist pattern is formed through a photoetching process, the photoresist pattern and the first shielding electrode in the first electrode layer pattern are used as shielding, and the first insulating layer film and the planarization layer film are sequentially subjected to a dry etching process And the shielding electrode is arranged, so that the manufacturing method can meet the etching requirement without increasing the aperture of the via hole in the planarization layer, and further can improve the aperture opening ratio and the yield of subsequent processing.
2. Compared with the prior art, the array substrate can be manufactured only by five photoetching processes (namely the gate metal layer, the active layer, the source drain layer, the first electrode layer, the first insulating layer, the planarization layer, the second insulating layer and the second electrode layer).
3. In the manufacturing method of the array substrate provided by the embodiment of the invention, after the whole layer of the first insulating layer film is formed on the first electrode layer pattern, the first through hole is etched, and after the first through hole is etched, a wet etching process is adopted for the protruding part of the first shielding electrode protruding out of the planarization layer, so that the protruding part can be effectively removed, and the effects of the first shielding electrode and the first electrode cannot be influenced.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (17)

1. A manufacturing method of an array substrate comprises the following steps:
forming a grid metal layer pattern, a grid insulation layer film, an active layer pattern and a source drain metal layer pattern on a substrate;
sequentially forming a planarization layer film, a first electrode layer pattern, a first insulating layer film and a photoresist pattern on the source drain metal layer pattern;
performing a dry etching process on the first insulating layer film by taking the photoresist pattern as a mask, performing a dry etching process on the planarization layer film by taking the photoresist pattern and a first shielding electrode in the first electrode layer pattern as a mask, and forming a first through hole in the first insulating layer film, the first shielding electrode and a via hole formed in the planarization layer film;
and forming a second electrode layer pattern comprising a first bridging electrode on the first insulating layer film, wherein the first bridging electrode at least completely covers the region of the first through hole and is connected with the source drain metal layer pattern.
2. The method of manufacturing of claim 1, wherein after forming the photoresist pattern, before forming the second electrode layer pattern, the method further comprises:
while forming a first through hole, carrying out a dry etching process on the first insulating layer film by taking the photoresist pattern as a shield, carrying out a dry etching process on the planarization layer film and the gate insulating layer film by taking the photoresist pattern and a second shield electrode in the first electrode layer pattern as a shield, and forming a second through hole by using via holes formed in the first insulating layer film, the second shield electrode, the planarization layer film and the gate insulating layer film;
forming a second electrode layer pattern, further comprising:
and forming a second electrode layer pattern comprising a second bridging electrode on the first insulating layer film, wherein the second bridging electrode at least completely covers the area of the second through hole and is connected with the gate metal layer pattern.
3. The method according to claim 2, wherein the dry etching process is performed on the first insulating film using the photoresist pattern as a mask and the dry etching process is performed on the planarization layer film and the gate insulating film using the photoresist pattern and the second mask electrode in the first electrode layer pattern as a mask while forming the first via hole, and the method comprises:
forming a first through hole, and forming a via hole for forming the second through hole in the first insulating layer film by using the photoresist pattern as a shield and adopting a dry etching process on the first insulating layer film, wherein part of the second shielding electrode can be exposed from the via hole formed in the first insulating layer film;
forming a through hole for forming the second through hole in the planarization layer film by taking the photoresist pattern and the exposed part of the second shielding electrode as shielding and adopting a dry etching process for the planarization layer film;
and forming a through hole for forming the second through hole in the gate insulating layer film by using the photoresist pattern and the exposed part of the second shielding electrode as shielding materials and adopting a dry etching process for the gate insulating layer film.
4. The method of manufacturing according to claim 3, further comprising, after performing a dry etching process on the first insulating layer film, the planarization layer film, and the gate insulating layer film, before forming the second electrode layer pattern:
and removing part of the exposed second shielding electrode by adopting a wet etching process so as to enable the aperture of the via hole in the second shielding electrode to be larger than that of the via hole in the planarization layer film.
5. The method of claim 1, wherein the dry etching the first insulating layer film using the photoresist pattern as a mask and the dry etching the planarization layer film using the first mask electrode of the photoresist pattern and the first electrode layer pattern as a mask comprises:
forming a via hole for forming the first through hole in the first insulating layer film by using the photoresist pattern as a shield and adopting a dry etching process for the first insulating layer film, wherein the via hole formed in the first insulating layer film can expose part of the first shielding electrode;
and forming a through hole for forming the first through hole in the planarization layer film by taking the photoresist pattern and the exposed part of the first shielding electrode as shielding and adopting a dry etching process for the planarization layer film.
6. The method of manufacturing according to claim 5, further comprising, after performing a dry etching process on the first insulating layer film and the planarization layer film, before forming the second electrode layer pattern:
and removing part of the exposed first shielding electrode by adopting a wet etching process so as to enable the aperture of the via hole in the first shielding electrode to be larger than that of the via hole in the planarization layer film.
7. The method of manufacturing according to claim 4 or 6, further comprising, after the wet etching process is used and before the forming of the second electrode layer pattern:
and adopting a dry etching process for the first insulating layer film and/or the gate insulating layer film.
8. The method of any of claims 1-6, wherein after patterning the source and drain metal layers and before forming the planarization layer film, the method further comprises:
and forming a second insulating layer film on the source/drain electrode metal layer pattern.
9. The method of claim 8, wherein after the dry etching process is performed on the planarization layer film, the method further comprises: performing a dry etching process on the second insulating layer film to form the first through hole by using the via holes formed in the first insulating layer film, the first shielding electrode, the planarization layer film and the second insulating layer film;
performing a dry etching process on the first insulating layer thin film, the second insulating layer thin film, and the gate insulating layer thin film, specifically including:
performing a one-time dry etching process on the first insulating layer film by using first etching gas, and performing a one-time dry etching process on the second insulating layer film and the gate insulating layer film by using the first etching gas;
or, simultaneously carrying out a one-time dry etching process on the first insulating layer film, the second insulating layer film and the grid insulating layer film by using the first etching gas.
10. The method of claim 9, wherein the first etching gas comprises carbon tetrafluoride and oxygen; or, the first etching gas comprises sulfur hexafluoride and oxygen.
11. The method of any of claims 1-6, wherein a dry etching process is performed on the planarization layer film using a second etching gas.
12. The manufacturing method according to claim 11, wherein a material of the planarization layer film includes a silicone resin; the second etching gas comprises carbon tetrafluoride or sulfur hexafluoride.
13. The method of manufacturing according to claim 2, wherein the first electrode layer pattern includes a common electrode, a first shielding electrode, and a second shielding electrode, and the second electrode layer pattern includes a pixel electrode, a first bridge electrode, and a second bridge electrode;
the first shielding electrode is an independent structure which is arranged on the same layer as the common electrode and is mutually disconnected; the second shielding electrode is of an integral structure connected with the common electrode; the first bridge electrode is an integral structure connected with the pixel electrode; the second bridge electrode is an independent structure which is arranged on the same layer as the pixel electrode and is mutually disconnected;
or, the first electrode layer pattern includes a pixel electrode, a first shielding electrode and a second shielding electrode, and the second electrode layer pattern includes a common electrode, a first bridge electrode and a second bridge electrode;
the first shielding electrode is of an integral structure connected with the pixel electrode; the second shielding electrode is an independent structure which is arranged on the same layer as the pixel electrode and is mutually disconnected; the first bridge electrode is an independent structure which is arranged on the same layer as the common electrode and is mutually disconnected; the second bridge electrode is an integral structure connected to the common electrode.
14. An array substrate, comprising: the substrate comprises a grid metal layer pattern, a grid insulating layer, an active layer pattern, a source drain metal layer pattern, a planarization layer film, a first electrode layer pattern, a first insulating layer film and a second electrode layer pattern which are sequentially arranged on a substrate;
wherein a first through hole is formed by the first insulating layer film, the first shielding electrode in the first electrode layer pattern and the via hole formed in the planarization layer film;
and the first bridging electrode included in the second electrode layer pattern at least completely covers the area of the first through hole and is respectively connected with the first shielding electrode and the source drain metal layer pattern.
15. The array substrate of claim 14, wherein the via holes formed in the first insulating layer film, the second shielding electrode in the first electrode layer pattern, the planarization layer film, and the gate insulating layer film constitute a second via hole;
the second bridging electrode included in the second electrode layer pattern at least completely covers the area of the second through hole and is respectively connected with the second shielding electrode and the grid metal layer pattern.
16. The array substrate of claim 15, wherein the first electrode layer pattern comprises a common electrode pattern, a first shielding electrode pattern and a second shielding electrode pattern; the second electrode layer pattern comprises a pixel electrode pattern, a first bridge electrode pattern and a second bridge electrode pattern;
the common electrode pattern has a first open region in which the first shielding electrode pattern is disposed, and an aperture of the first open region is larger than a via hole aperture in the first shielding electrode pattern; the second shielding electrode pattern is of an integral structure connected with the common electrode pattern, and the second shielding electrode pattern comprises a through hole forming a second through hole; the first bridge electrode pattern is an integral structure connected with the pixel electrode pattern; the second bridge electrode pattern is disconnected from the common electrode pattern;
or the first electrode layer pattern comprises a pixel electrode pattern, a first shielding electrode pattern and a second shielding electrode pattern; the second electrode layer pattern comprises a common electrode pattern, a first bridge electrode pattern and a second bridge electrode pattern;
the first shielding electrode pattern is of an integral structure connected with the pixel electrode pattern, and the first shielding electrode pattern comprises a through hole forming a first through hole; the second shielding electrode pattern is disconnected from the pixel electrode pattern, and the second shielding electrode pattern comprises a through hole forming a second through hole; the first bridge electrode pattern is disconnected from the common electrode pattern; the second bridge electrode pattern is an integral structure connected to the common electrode pattern.
17. A display device comprising the array substrate of any one of claims 14 to 16.
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CN111244116B (en) 2020-03-23 2022-06-28 京东方科技集团股份有限公司 Half-via-hole structure, manufacturing method thereof, array substrate and display panel
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