KR100984823B1 - Array Panel for Liquid Crystal Display Device and Method for fabricating the same - Google Patents

Abstract

In the present invention, in order to provide a liquid crystal display device having a simplified process and a method of manufacturing the same, the semiconductor layer and the data wiring are simultaneously formed in one mask process by using the diffraction exposure method, and the contacts are lifted off. By eliminating the hole process and directly contacting the pixel electrode and the drain electrode, by providing a three-mask array process in which two mask processes are shorter than before, the process can be simplified, manufacturing costs can be reduced, and productivity The improvement has the advantage of increasing the production yield.

Description

Array substrate for liquid crystal display device and manufacturing method thereof {Array Panel for Liquid Crystal Display Device and Method for fabricating the same}             

1 is a three-dimensional view of a portion of a general liquid crystal display device.

2, 3A to 3E, 4A to 4E, and 5A to 5E are views of an array substrate for a liquid crystal display device according to a conventional five mask process, and FIG. 2 is a plan view, and FIGS. 3A to 3E and 4A to FIG. 4E, FIGS. 5A to 5E are cross-sectional views shown step by step according to the manufacturing process for sections cut along the cut lines " IIIa-IIIa ", " IIIb-IIIb " and " IIIc-IIIc "

6 and 7A to 7C are views of an array substrate for a liquid crystal display according to a first embodiment of the present invention. FIG. 6 is a plan view, and FIGS. 7A to 7C are cut lines “VIIa-VIIa” of FIG. 6. , Cross-sections showing the respective cross sections cut according to "VIIb-VIIb", "VIIc-VIIc".

8A to 8K, 9A to 9K, 10A to 10K, and 11A to 11K are process diagrams illustrating, in stages, a manufacturing process of an array substrate for a three mask liquid crystal display device according to a second exemplary embodiment of the present invention. 8J are plan views, and FIGS. 9A to 9K, 10A to 10K, and 11A to 11K are cross-sectional views cut along the cutting lines "IX-IX", "XX", and "XI-XI" of FIGS. 8A to 8J. Shown cross section.

<Brief description of the main parts of the drawing>

110: substrate 116: gate pad

120: gate insulating film 138: drain electrode

140: data pad 146: protective layer

154: open portion 156: gate pad contact hole

158: data pad contact hole 162: pixel electrode

164: gate pad electrode 166: data pad electrode

P: pixel area T: thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to an array substrate for a liquid crystal display device having a reduced number of mask steps and a method of manufacturing the same.

Recently, liquid crystal displays have been spotlighted as next-generation advanced display devices with low power consumption, good portability, technology-intensive, and high added value.

The liquid crystal display device is formed by injecting liquid crystal between two substrates on which transparent electrodes are formed, and placing upper and lower polarizers on the upper and lower substrates, and changing the polarization characteristics of light according to the anisotropy of the liquid crystal molecules. It corresponds to the non-light emitting element obtained.

1 is a stereoscopic view of a part of a general liquid crystal display device.

As shown in the figure, the upper and lower substrates 10 and 30 face each other with a predetermined distance therebetween, and the liquid crystal layer 50 is interposed between the upper and lower substrates 10 and 30.

A plurality of gates and data lines 32 and 34 cross each other on the lower substrate 30, and a thin film transistor T is formed at a point where the gates and data lines 32 and 34 cross each other. A pixel electrode 46 connected to the thin film transistor T is formed in the pixel area P defined as an area where the gate and the data lines 32 and 34 intersect.

Although not shown in detail in the drawing, the thin film transistor T is a channel for controlling voltage on / off by a gate electrode receiving a gate voltage, a source and drain electrode receiving a data voltage, and a difference between the gate voltage and the data voltage. (ch; channel).

The color filter layer 12 and the common electrode 16 are sequentially formed below the upper substrate 10.

Although not shown in detail in the drawing, the color filter layer 12 is composed of a color filter for transmitting only light of a specific wavelength band and a black matrix positioned at a boundary of the color filter to block light on an area where the arrangement of liquid crystals is not controlled.                         

In addition, upper and lower polarizers 52 and 54 for transmitting only light parallel to the polarization axis are positioned on each outer surface of the upper and lower substrates 10 and 30, and a backlight, which is a separate light source, is provided below the lower polarizer 54. light) is placed.

In the liquid crystal display having the stacked structure, the array elements of the array substrate to which the main signal for implementing the screen is applied are formed by a photolithography process, that is, a mask process, which can be defined as a patterning process using a photosensitive material.

2, 3A to 3E, 4A to 4E, and 5A to 5E are views of an array substrate for a liquid crystal display device according to a conventional five mask process, and FIG. 2 is a plan view and FIGS. 3A to 3E and FIG. 4A to 4E and FIGS. 5A to 5E are cross-sectional views of the cross sections cut along the cutting lines "IIIa-IIIa", "IIIb-IIIb", and "IIIc-IIIc" of FIG.

2, the gate wiring 62 and the data wiring 72 are formed to cross each other, and the thin film transistor T which is a switching element is formed at the intersection of the gate wiring 62 and the data wiring 72. In FIG. In the pixel region P defined as the intersection region of the gate wiring 62 and the data wiring 72, a pixel electrode 88 connected to the thin film transistor T is formed.

In addition, a gate pad 66 and a data pad 84 connected to an external circuit (not shown) are formed at each end of the gate line 62 and the data line 72, and the gate pad 66 and The gate pad electrode 90 and the data pad electrode 92 each having an island pattern structure are formed in an area covering each of the data pads 84.                         

In addition, the pixel electrode 88 is positioned to overlap the front gate line 62 at a predetermined interval, and the overlap region of the pixel electrode 88 and the gate line 62 has a storage capacitance C _ST with an insulating film interposed therebetween. To achieve.

Hereinafter, a manufacturing process of the array substrate for a liquid crystal display device according to FIG. 2 will be described based on a mask process.

3A, 4A, and 5A are steps for forming the gate wiring 62, the gate electrode 64, and the gate pad 66 on the substrate 60 by a first mask process.

A portion of the gate line 62 forms a storage electrode 67.

Although not shown in the drawings, the gate electrode 64 is branched from the gate line 62, and the gate pad 66 is formed at one end of the gate line 62.

3B, 4B, and 5B illustrate forming a gate insulating film 68 on the entire surface of the substrate covering the gate wiring 62, the gate electrode 64, and the gate pad 66, and performing a second mask process. (68) The semiconductor layer 70 is formed in the region covering the gate electrode 64 above.

For example, the semiconductor layer 70 has a structure in which an active layer 70a made of pure amorphous silicon material and an ohmic contact layer 70b made of impurity amorphous silicon material are sequentially stacked.

3C, 4C, and 5C are connected to the source electrode 74 and the drain electrode 76 positioned to be spaced apart from each other above the semiconductor layer 70 by a third mask process, and to the source electrode 74. In this step, the data line 72 and the data pad 84 are formed.

Although not shown in the drawings, the data pad 84 is formed at one end of the data line 72.

In this step, the ohmic contact layer 70b positioned in the interval between the source electrode 74 and the drain electrode 76 is removed, and the active layer 70a constituting the lower layer is exposed to expose the exposed active layer ( 70a) forming a region with a channel ch.

The gate electrode 64, the semiconductor layer 70, the source electrode 74, and the drain electrode 76 form a thin film transistor T.

3D, 4D, and 5D are positioned on the entire surface of the substrate covering the thin film transistor T and the data pad 84 by a fourth mask process, and the drain electrode 76, the gate pad 66, and the data pad are disposed on the substrate. A protective layer 86 having a drain contact hole 80, a gate pad contact hole 82, and a data pad contact hole 84 that partially exposes 84 is formed.

In this case, the gate pad contact hole 82 corresponds to a contact hole simultaneously formed by the protective layer 86 and the gate insulating layer 68.

3E, 4E, and 5E show a pixel region P defined as an intersection region of the above-described gate wiring 62 and data wiring 72 by the fifth mask process, through the drain contact hole 80. The pixel electrode 88 connected to the drain electrode 76, the gate pad electrode 90 connected to the gate pad 66 through the gate pad contact hole 82, and the data pad contact hole 84. In this step, the data pad electrodes 92 connected to the data pad 84 are respectively formed.

The pixel electrode 88, the gate pad electrode 90, and the data pad electrode 92 are selected from a transparent conductive material, and the gate pad electrode 90 and the data pad electrode 92 are the gate pad 66 and the data, respectively. It forms in a kind of island pattern in the area | region which covers the pad 84. FIG.

As described above, a mask process of a conventional array substrate for a liquid crystal display device is performed by a five mask process. As the mask process is repeated with chemical and physical processes, the longer the number of mask processes, the more facility investment and equipment investment cost for manufacturing. As it increases, the reduction of the number of mask processes is urgently needed in relation to the production yield.

In order to solve the above problems, it is an object of the present invention to provide a liquid crystal display device and a method of manufacturing the simplified process.

To this end, in the present invention, the semiconductor layer and the data wiring are simultaneously formed in one mask process using a diffraction exposure method, the contact hole process is omitted by a lift off process, and the pixel electrode and the drain electrode are directly contacted. By the process of making, it is to provide a three-mask array process in which two mask processes are shortened than conventional.

In the aforementioned lift-off process, a desired pattern material is entirely formed in an area covering a PR pattern made of a photoresist material, which is a photosensitive material, and then the pattern material of an area covering the PR pattern is formed through a strip process of the PR pattern. Lifting off and using the remaining pattern material as a pattern, wherein the formation range of the PR pattern corresponds to the spaced area between the patterns.

In contrast, in the general mask process, the entirety of the pattern material is formed to form a PR pattern, the exposed pattern material region is etched using the PR pattern as a mask, and the pattern is formed by stripping the PR pattern. That is, the aforementioned lift-off process is simpler than the mask process, and has an advantage of shortening the entire mask process by adjusting process conditions.

In order to achieve the above object, in a first aspect of the present invention, there is provided a semiconductor device comprising: a gate wiring formed on a substrate with a gate pad at one end thereof; A data line formed in a direction crossing the gate line and having a data pad at one end thereof; A thin film transistor formed at the intersection of the gate wiring and the data wiring, the thin film transistor comprising a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; An intersection area of the gate line and the data line is defined as a pixel area, and an open part is formed in an area exposing the substrate surface and a part of the drain electrode partially exposed at a position corresponding to the pixel area, the gate pad and the data. An insulating layer each having a gate pad contact hole and a data pad contact hole exposing the pad; In the open area, the substrate is directly connected to the drain electrode, and is formed through a lift-off process of patterning a lift-off method through a strip process of a photosensitive material pattern. A pixel electrode in contact with the pixel electrode; A gate pad electrode formed of the same material in the same process as the pixel electrode and positioned in the gate pad contact hole region and connected to the gate pad, and a data pad positioned in the data pad contact hole region and connected to the data pad Provided is a substrate for a liquid crystal display device including an electrode.

The pixel electrode, the gate pad electrode, and the data pad electrode are made of a transparent conductive material, and the pixel electrode is positioned to overlap the front gate wiring at a predetermined interval, and the gate wiring region overlapping the pixel electrode is a storage electrode. The overlapped region between the pixel electrode and the storage electrode forms a storage capacitance with an insulator interposed therebetween, and the semiconductor layer is connected to a semiconductor material layer having a pattern structure corresponding to the data line, the source electrode, the drain electrode, and the data pad. The data line, the source electrode, the drain electrode, the data pad, the semiconductor layer, and the semiconductor material layer are made of the same material in the same process.

According to a second aspect of the present invention, a gate electrode and a gate at one end are formed by a first mask process, which is a photolithography process defined as a process of patterning a photosensitive material using an exposure, development, and etching process on a substrate. Forming a gate wiring having a pad; By a second mask process, the semiconductor material layer having a semiconductor layer, a semiconductor material layer having a semiconductor layer, a data electrode having a source electrode, and a data pad positioned at one end thereof is spaced apart from the source electrode by a second mask process. Forming a channel comprising a region of a pure semiconductor material between the drain electrode positioned and a gap between the source electrode and the drain electrode; The crossing region of the gate wiring and the data wiring is defined as a pixel region, and the gate electrode, the semiconductor layer, the source electrode, and the drain electrode form a thin film transistor, and form a protective layer on the entire surface of the substrate covering the thin film transistor, Forming a first PR pattern having a first open portion exposing a protective layer on a region covering the pixel region and the drain electrode, and second and third open portions exposing the protective layers of the gate pad and the data pad on the layer; Wow; The pixel opening part exposing the substrate surface and the drain electrode at a position corresponding to the first opening part by collectively etching the protective layer and the gate insulating film in the exposed area by a third mask process using the first PR pattern. Forming a gate pad contact hole and a data pad contact hole respectively exposing the gate pad and the data pad at positions corresponding to the second and third openings; Forming a transparent conductive material on the entire surface of the substrate covering the first PR pattern; Stripping the first PR pattern, lifting off a transparent conductive material region on a region covering the first PR pattern; The transparent conductive material left after the lift-off process is connected to the drain electrode in direct contact manner, the pixel electrode in direct contact with the substrate in the pixel opening, and the gate in the gate pad contact hole. A method of manufacturing an array substrate for a liquid crystal display device comprising forming a pad electrode and a data pad electrode connected to a data pad electrode connected to a data pad in the data pad contact hole.

In the second mask process, the second mask process may be performed using a second PR pattern formed at a position corresponding to the data line, the source electrode, the drain electrode, the data pad, and the channel forming unit. The PR pattern has a first thickness at a position corresponding to the channel forming portion by a diffraction exposure method, and a second thickness thicker than the first thickness at a position corresponding to the data line, the source electrode, the drain electrode, and the data pad. The pixel electrode is positioned to overlap the front gate wiring at a predetermined interval, and the gate wiring region overlapping the pixel electrode forms a storage electrode, and the overlapping region of the storage electrode and the pixel electrode includes a gate insulating film and a protective layer interposed therebetween. Form a storage capacitance, and the first PR pattern has a first thickness in an area covering the storage electrode. And a second thickness thicker than the first thickness in all regions on the substrate other than the regions covering the storage electrodes and the first, second and third open portions, and between the third mask process and the lift-off process. And etching the thickness of the first PR pattern covering the storage electrode.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment

6 and 7A to 7C are views of an array substrate for a liquid crystal display according to a first embodiment of the present invention. FIG. 6 is a plan view, and FIGS. 7A to 7C are cut lines “VIIa-VIIa” of FIG. 6. , VIIb-VIIb, and VIIc-VIIc, respectively.

FIG. 6 shows that the gate wiring 112 is formed on the substrate 110 in the first direction, the data wiring 134 is formed in the second direction crossing the first direction, and the gate wiring 112 and At a point where the data lines 134 intersect, the gate electrode 114 branched from the gate line 112, the source electrode 136 branched from the data line 134, and the source electrode 136 are spaced apart from each other. The thin film transistor T is formed of a drain electrode 138, a gate electrode 114, a source electrode 136, and a semiconductor layer 144 positioned in a region overlapping the drain electrode 138. The gate pad 116 and the data pad 140 are formed at one end of the gate line 112 and the data line 134, respectively.

The open portion 154 exposing the pixel region P, the gate pad contact hole 156 and the data pad contact hole 158 exposing the gate pad 116 and the data pad 140 are partially exposed. The passivation layer 146 is formed, and the open portion 154 includes a region partially exposing the drain electrode 138. The pixel electrode 162 is formed in the open portion 154 by a direct connection method without a separate contact hole with the drain electrode 138. The gate pad contact hole 156 and the data pad contact hole 158 are formed. In the region, a gate pad electrode and a data pad electrode are formed, respectively.

The gate pad electrode 164 and the data pad electrode 166 are made of the same material in the same process as the pixel electrode 162. In the present embodiment, the gate pad electrode 164 is formed by a lift-off process using a transparent conductive material. The data pad electrode 166 and the pixel electrode 162 are formed at the same time.

In addition, the semiconductor layer 144 may be included in the semiconductor material layer 142 having a pattern structure corresponding to the data line 134, the source electrode 136, the drain electrode 138, and the data pad 140. The semiconductor material layer 142 and the data line 134 are formed in the same mask process using a diffraction exposure method.

The pixel electrode 162 is positioned to overlap the front gate line 112 at a predetermined interval, and the region of the gate line 112 overlapping the pixel electrode 162 forms a storage electrode 118. The 162 and the storage electrode 118 form a storage capacitance C _ST with an insulator interposed therebetween.

Hereinafter, the stacked structure of the array substrate according to FIG. 6 will be described in detail with reference to FIGS. 7A to 7C.

As illustrated, a gate wiring 112, a gate electrode 114, and a gate pad 116 are formed on the substrate 110, and a portion of the gate wiring 112 forms a storage electrode 118. .

A gate insulating film 120 is formed in an area covering the gate wiring 112, the gate electrode 114, and the gate pad 116, and in an area covering the gate electrode 114 on the gate insulating film 120. The semiconductor layer 144 and the source electrode 136 and the drain electrode 138 which are spaced apart from each other on the semiconductor layer 144 are sequentially formed in a pattern structure corresponding to each other. The semiconductor material layer 142 is connected to the semiconductor layer 144, and the data line 134 is formed to be connected to the source electrode 136. The data pad 140 formed of the same material in the same process as the data line 134 is formed using the semiconductor material layer 142 as a lower layer.

The gate electrode 114, the semiconductor layer 144, the source electrode 136, and the drain electrode 138 form a thin film transistor T, and are positioned on a front surface of the substrate covering the thin film transistor T and the data pad 140. In addition, a passivation layer 146 having an open portion 154 exposing the pixel region P together with the gate insulating layer 120 is formed. The opening 154 includes a region in which the drain electrode 138 is partially exposed. The protective layer 146 has a data pad contact hole 158 partially exposing the data pad 140, and the protective layer 146 and the gate insulating layer 120 partially expose the gate pad 116. The gate pad contact hole 156 is provided.

The pixel electrode 162 is formed in direct contact with the drain electrode 138 exposed through the open part 154. In this case, the pixel electrode 162 is formed to include an area overlapping the storage electrode 118. The overlapped region of the pixel electrode 162 and the storage electrode 118 forms a storage capacitance C _ST with the gate insulating layer 120 and the protective layer 146 interposed therebetween.

The gate pad electrode 164 is connected to the gate pad 116 through the gate pad contact hole 156, and the data pad electrode is connected to the data pad 140 through the data pad contact hole 158. 166 are formed, respectively.

The pixel electrode 162, the gate pad electrode 164, and the data pad electrode 166 may be formed through a lift-off process, and the gate pad electrode 164 and the data pad electrode 166 may be formed in a process characteristic. The gate pad contact hole 156 and the data pad contact hole 158 have a structure formed therein.

In addition, since the pixel electrode 162 is formed in the pixel region P from which the protective layer 146 and the gate insulating layer 120 are completely removed, the pixel electrode 162 may be formed directly on the substrate surface. Have.

Hereinafter, a three mask array process according to the present embodiment will be described in detail with reference to the drawings.

Second Embodiment

This embodiment is an embodiment of a manufacturing process of an array substrate for a liquid crystal display device according to the first embodiment, and relates to a three mask process including a lift-off process.

8A to 8K, 9A to 9K, 10A to 10K, and 11A to 11K are process diagrams illustrating, in stages, a manufacturing process of an array substrate for a three mask liquid crystal display device according to a second exemplary embodiment of the present invention. 8J are plan views, and FIGS. 9A to 9K, 10A to 10K, and 11A to 11K are cross-sectional views cut along the cutting lines "IX-IX", "XX", and "XI-XI" of FIGS. 8A to 8J. It is sectional drawing.

In the present embodiment, the process conditions using the PR pattern will be described based on the characteristics of the process of reducing the mask process by changing the thickness value of the PR pattern.

8A, 9A, 10A, and 11A illustrate forming a gate wiring 212 in a first direction by a first mask process using a first metal material on a substrate 210 and branching from the gate wiring 212. The gate electrode 214 and the gate pad 216 positioned at the end of the gate wiring 212 are formed.

The forming of the gate wiring 212 includes forming a storage electrode 218 forming a portion of the gate wiring 212.

8B, 9B, 10B, and 11B illustrate a gate insulating film 220, a pure amorphous silicon material layer 222, and an impurity amorphous silicon in a region covering the gate wiring 212, the gate electrode 214, and the gate pad 216. The material layer 224 and the second metal material layer 226 are sequentially formed, and a first PR pattern 228 is formed in a second direction crossing the first direction by a second mask process.

The first PR pattern 228 may include a first a PR pattern 228a formed in the second direction and a first b PR pattern that is branched into an area covering the gate electrode 214 in the first a PR pattern 228b ( 228b) and a first c PR pattern 228c positioned at one end of the first a PR pattern 228a. In particular, the first b PR pattern 228b has a concave portion 232 in the channel formation region XII.

8C, 9C, 10C, and 11C show the second metal material layer 226, the impurity amorphous silicon material layer 224, and the pure water, which are located in the exposed region using the first PR pattern 228 as a kind of mask. The etching of the amorphous silicon material layer 222 is performed, and FIGS. 8D, 9D, 10D, and 11D illustrate the second metal material layer 226 at a position corresponding to the recess 232 of the first b PR pattern 228b. In order to expose, the first PR pattern 228 is ashed. An edge thickness of the first PR pattern 228 corresponds to a thickness of the recess 232 of the first PR pattern 228.

8E, 9E, 10E, and 11E remove the second metal material layer 226 and the impurity amorphous silicon layer 224 exposed from the channel forming region (XII of FIG. 8B), and form a lower layer. The pure amorphous silicon layer 222 is exposed. In this step, an over etching process is performed to completely expose the pure amorphous silicon layer 222.

8F, 9F, 10F, and 11F are stripping and removing the first PR pattern 228 of FIG. 8E. The second metal material layer (226 of FIG. 9E) corresponding to the first pattern of the first PR pattern (228a of FIG. 8E) forms a data line 234, and the first pattern of the PR pattern (228b of FIG. 8E). The second metal material layer 226 of FIG. 9E corresponds to the source electrode 236 and the drain electrode 238 spaced apart from each other based on the channel forming region XII, and the first c PR The second metal material layer 226 in the region corresponding to the pattern 228c forms the data pad 240.

In addition, an impurity amorphous silicon layer (224 of FIG. 8E) and a pure amorphous silicon layer formed of a pattern corresponding to the data line 234, the source electrode 236, the drain electrode 238, and the data pad 240. Referring to 222 of FIG. 8E, a semiconductor material layer 242 is formed, and the semiconductor material layer 242 in a region overlapping the source electrode 236 and the drain electrode 238 corresponds to the semiconductor layer 244. The semiconductor layer 244 includes an active layer 244a made of a pure amorphous silicon material layer 222 and an ohmic contact layer 244b made of an impurity amorphous silicon material layer 224.

In addition, an area of the pure amorphous silicon material layer 222 between the source electrode 236 and the drain electrode 238 forms a channel ch.                     

The gate electrode 214, the semiconductor layer 244, the source electrode 236, and the drain electrode 238 form a thin film transistor (T).

Next, FIGS. 8G, 9G, 10G and 11G form a protective layer 246 on the entire surface of the substrate covering the thin film transistor T and the data pad 240, and the pixel region P on the protective layer 246. The second PR pattern 248 is formed to cover the region except for the following.

In this case, in order to directly connect the pixel electrode and the drain electrode 238 in a subsequent process, the second PR pattern 248 has a pattern structure in which a portion of the drain electrode 238 is exposed.

In particular, the second PR pattern 248 has a diffraction region XIII having a low thickness in the region corresponding to the storage electrode 218 forming portion, and is part of the gate pad 216 and the data pad 240. It characterized in that it has a first, second openings 250, 252 to expose.

8H, 9H, 10H, and 11H use the second PR pattern 248 as a kind of mask to etch regions of the protective layer 246 and the gate insulating film 220 exposed by the third mask process. Step.

Through the etching process, the passivation layer 246 and the gate insulating layer 220 may have a third open portion 254 exposing the surface of the base substrate 210 in the pixel region P, and the first open portion described above. The protective layer 246 and the gate insulating layer 220 at the position corresponding to 250 have a gate pad contact hole 256 exposing the gate pad 216, and at a position corresponding to the second opening 252. The protective layer 246 has a data pad contact hole 258 exposing the data pad 240.

8I, 9i, 10i, and 11i are steps of etching the second PR pattern 248 by the thickness value of the second PR pattern 248 positioned in the diffraction region XIII. 9j, 10j, and 11j are steps of forming the transparent conductive material layer 260 on the entire surface of the substrate covering the etched second PR pattern 248.

For example, the transparent conductive material layer 260 may be selected from any one of ITO, ITZO, and IZO.

8K, 9K and 10K strip the second PR pattern 248 and lift off the transparent conductive material layer (260 of FIG. 8J) covering the second PR pattern (248 of FIG. 8J). The remaining transparent conductive material layer 260 is formed of the pixel electrode 262, the gate pad electrode 264, and the data pad electrode 266.

In more detail, the transparent conductive material layer 260 positioned in the third open portion 254 and in contact with the exposed drain electrode 238 forms the pixel electrode 262, and the gate pad contact hole. A portion connected to the gate pad 216 through 256 forms a gate pad electrode 264, and a portion connected to the data pad 240 through a data pad contact hole 258 forms a data pad electrode 266. Achieve.

An area of the storage electrode 218 overlapping the pixel electrode 262 forms a storage capacitance C _ST with a gate insulating layer 220 and a protective layer 246 interposed therebetween.

However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention.

For example, the present invention includes a liquid crystal display device including an array substrate for liquid crystal display devices according to the first and second embodiments, another opposing substrate, and a liquid crystal layer interposed between the two substrates.

As described above, according to the liquid crystal display and the method of manufacturing the same according to the three mask process according to the present invention, the process can be simplified, the manufacturing cost can be reduced, and the productivity can be improved by increasing the productivity.

Claims (8)

A gate wiring formed on the substrate and having a gate pad at one end thereof; A data line formed in a direction crossing the gate line and having a data pad at one end thereof; A thin film transistor formed at the intersection of the gate wiring and the data wiring, the thin film transistor comprising a gate electrode, a semiconductor layer, a source electrode, and a drain electrode; An intersection area of the gate line and the data line is defined as a pixel area, and an open part is formed in an area exposing the substrate surface and a part of the drain electrode partially exposed at a position corresponding to the pixel area, the gate pad and the data. An insulating layer each having a gate pad contact hole and a data pad contact hole exposing the pad; In the open area, the substrate is directly connected to the drain electrode, and is formed through a lift-off process of patterning a lift-off method through a strip process of a photosensitive material pattern. A pixel electrode in contact with the pixel electrode; A gate pad electrode formed of the same material in the same process as the pixel electrode and positioned in the gate pad contact hole region and connected to the gate pad, and a data pad positioned in the data pad contact hole region and connected to the data pad electrode Liquid crystal display substrate comprising a. The method of claim 1, The pixel electrode, the gate pad electrode, and the data pad electrode are made of a transparent conductive material. The method of claim 1, The pixel electrode is positioned to overlap the front gate wiring at a predetermined interval, and the gate wiring region overlapping the pixel electrode forms a storage electrode, and the overlapping region between the pixel electrode and the storage electrode forms a storage capacitance with an insulator interposed therebetween. A liquid crystal display substrate. The method of claim 1, The semiconductor layer is connected to a semiconductor material layer having a pattern structure corresponding to the data line, the source electrode, the drain electrode, and the data pad, and the data line, the source electrode, the drain electrode, the data pad, the semiconductor layer, and the semiconductor material layer. Silver substrate for a liquid crystal display device made of the same material in the same process. Forming a gate electrode and a gate wiring having a gate pad at one end thereof by a first mask process, which is a photolithography process defined as a process of patterning the photosensitive material through exposure, development, and etching processes using a photosensitive material; Steps; By a second mask process, the semiconductor material layer having a semiconductor layer, a semiconductor material layer having a semiconductor layer, a data electrode having a source electrode, and a data pad positioned at one end thereof is spaced apart from the source electrode by a second mask process. Forming a channel comprising a region of a pure semiconductor material between the drain electrode positioned and a gap between the source electrode and the drain electrode; The crossing region of the gate wiring and the data wiring is defined as a pixel region, and the gate electrode, the semiconductor layer, the source electrode, and the drain electrode form a thin film transistor, and form a protective layer on the entire surface of the substrate covering the thin film transistor, Forming a first PR pattern having a first open portion exposing a protective layer on a region covering the pixel region and the drain electrode, and second and third open portions exposing the protective layers of the gate pad and the data pad on the layer; Wow; The pixel opening part exposing the substrate surface and the drain electrode at a position corresponding to the first opening part by collectively etching the protective layer and the gate insulating film in the exposed area by a third mask process using the first PR pattern. Forming a gate pad contact hole and a data pad contact hole respectively exposing the gate pad and the data pad at positions corresponding to the second and third openings; Forming a transparent conductive material on the entire surface of the substrate covering the first PR pattern; Stripping the first PR pattern, lifting off a transparent conductive material region on a region covering the first PR pattern; The transparent conductive material left after the lift-off process is connected to the drain electrode in direct contact manner, the pixel electrode in direct contact with the substrate in the pixel opening, and the gate in the gate pad contact hole. Forming a pad electrode and a data pad electrode connected to a data pad electrode connected to the data pad in the data pad contact hole Method of manufacturing an array substrate for a liquid crystal display device comprising a. The method of claim 5, The second mask process is performed using a second PR pattern formed at a position corresponding to the data line, the source electrode, the drain electrode, the data pad, and the channel forming unit, and the second PR pattern is subjected to a diffraction exposure method. Thereby having a first thickness at a position corresponding to the channel forming portion, and a second thickness thicker than the first thickness at a position corresponding to the data line, the source electrode, the drain electrode, and the data pad. Method of preparation. The method of claim 5, The pixel electrode is positioned to overlap the front gate wiring at a predetermined interval, and the gate wiring region overlapping the pixel electrode forms a storage electrode, and the overlapping region of the storage electrode and the pixel electrode is interposed with a gate insulating film and a protective layer. A method of manufacturing an array substrate for a liquid crystal display device having a storage capacitance. The method according to any one of claims 5 to 7, The first PR pattern has a first thickness in a region covering the storage electrode, and is thicker than the first thickness in all regions on the substrate other than the region covering the storage electrode and the first, second, and third open portions. And etching the thickness of the first PR pattern covering the storage electrode between the third mask process and the lift-off process, having a second thickness.

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