CN107294362A - Spm - Google Patents
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- CN107294362A CN107294362A CN201610190441.1A CN201610190441A CN107294362A CN 107294362 A CN107294362 A CN 107294362A CN 201610190441 A CN201610190441 A CN 201610190441A CN 107294362 A CN107294362 A CN 107294362A
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- spm
- igbt
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- frd
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
Abstract
The invention discloses a kind of SPM, including HVIC chips, multiple IGBT pipe and FRD pipes；It is characterized in that：Adaptive circuit is provided with the HVIC chips, the PFCINP ends of HVIC chips connect the first input end of adaptive circuit；First output end of adaptive circuit as the HVIC chips PFCC ends；Second output end of adaptive circuit as the HVIC chips PFCO ends；In the rising edge of PFCINP signals, the first output end output permanent High level of adaptive circuit；In the trailing edge of PFCINP signals, the first output end of adaptive circuit is exported after the preheating setting time Tj of interval continues low level；The output of the second output end and signals of the PFCINP with phase of the adaptive circuit.The SPM of the present invention obtains electrostatic discharge protection mechanism on the premise of normal work is not influenceed, and maintains the stability, availability, robustness of system.
Description
Technical field
The present invention relates to the design of a kind of SPM, the more particularly to protection circuit of SPM and electrostatic suppression circuit.
Background technology
SPM, i.e. IPM（Intelligent
Power Module）, it is a kind of power drive class product for combining power electronics and integrated circuit technique.SPM integrates device for power switching and high-voltage driving circuit, and is built-in with the failure detector circuits such as overvoltage, overcurrent and overheat.On the one hand SPM receives MCU control signal, and on the other hand driving subsequent conditioning circuit work send the state detection signal of system back to MCU.Compared with traditional discrete scheme, SPM wins increasing market with advantages such as its high integration, high reliability, it is particularly suitable for the frequency converter and various inverters of motor, is frequency control, metallurgical machinery, electric propulsion, servo-drive, a kind of preferable power electronic devices of frequency-conversion domestic electric appliances.
The existing circuit structure for SPMs 100 in field such as convertible frequency air-conditioners, referring to shown in accompanying drawing 1 and accompanying drawing 2：
The VCC ends of HVIC chips 101 are generally 15V as low-pressure area power supply the anode VDD, VDD of the SPM 100；
There is boostrap circuit inside the HVIC chips 101, boostrap circuit structure is as follows：
VCC ends are connected with the anode of bootstrap diode 102, bootstrap diode 103, bootstrap diode 104；
The negative electrode of the bootstrap diode 102 is connected with the VB1 of the HVIC chips 101；
The negative electrode of the bootstrap diode 103 is connected with the VB2 of the HVIC chips 101；
The negative electrode of the bootstrap diode 104 is connected with the VB3 of the HVIC chips 101；
The HIN1 ends of the HVIC chips 101 are used as bridge arm input UHIN in the press U phases of the SPM 100；
The HIN2 ends of the HVIC chips 101 are used as bridge arm input VHIN in the press V phases of the SPM 100；
The HIN3 ends of the HVIC chips 101 are used as bridge arm input WHIN in the press W phases of the SPM 100；
The LIN1 ends of the HVIC chips 101 are used as bridge arm input ULIN under the press U phases of the SPM 100；
The LIN2 ends of the HVIC chips 101 are used as bridge arm input VLIN under the press V phases of the SPM 100；
The LIN3 ends of the HVIC chips 101 are used as bridge arm input WLIN under the press W phases of the SPM 100；
The PFCINP ends of the HVIC chips 101 as the SPM 100 PFC control signals PFCIN；
Here, the tunnel of UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six input of the SPM 100 and PFCIN ends receive 0V or 5V input signal；
The GND ends of the HVIC chips 101 as the SPM 100 low-pressure area power supply negative terminal COM；
The ITRIP ends of the HVIC chips 101 as the SPM 100 current detecting vb end MTRIP；
The VB1 ends of the HVIC chips 101 connect one end of electric capacity 131, and are used as the press U phases higher-pressure region power supply anode UVB of the SPM 100；
The HO1 ends of the HVIC chips 101 are connected with the grid of bridge arm IGBT pipes 121 in press U phases；
The VS1 ends of the HVIC chips 101 are connected with the other end of the colelctor electrode of bridge arm IGBT pipes 124 under the emitter-base bandgap grading of the IGBT pipes 121, the anode of FRD pipes 111, press U phases, the negative electrode of FRD pipes 114, the electric capacity 131, and are used as the press U phases higher-pressure region power supply negative terminal UVS of the SPM 100；
The VB2 ends of the HVIC chips 101 connect one end of electric capacity 132, are used as the press U phases higher-pressure region power supply anode VVB of the SPM 100；
The HO3 ends of the HVIC chips 101 are connected with the grid of bridge arm IGBT pipes 123 in press V phases；
The VS2 ends of the HVIC chips 101 are connected with the other end of the colelctor electrode of bridge arm IGBT pipes 125 under the emitter-base bandgap grading of the IGBT pipes 122, the anode of FRD pipes 112, press V phases, the negative electrode of FRD pipes 115, the electric capacity 132, and are used as the press V phases higher-pressure region power supply negative terminal VVS of the SPM 100；
The VB3 ends of the HVIC chips 101 connect one end of electric capacity 133, are used as the press W phases higher-pressure region power supply anode WVB of the SPM 100；
The HO3 ends of the HVIC chips 101 are connected with the grid of bridge arm IGBT pipes 123 in press W phases；
The VS3 ends of the HVIC chips 101 are connected with the other end of the colelctor electrode of bridge arm IGBT pipes 126 under the emitter-base bandgap grading of the IGBT pipes 123, the anode of FRD pipes 113, press W phases, the negative electrode of FRD pipes 116, the electric capacity 133, and are used as the press W phases higher-pressure region power supply negative terminal WVS of the SPM 100；
The LO1 ends of the HVIC chips 101 are connected with the grid of the IGBT pipes 124；
The LO2 ends of the HVIC chips 101 are connected with the grid of the IGBT pipes 125；
The LO3 ends of the HVIC chips 101 are connected with the grid of the IGBT pipes 126；
The emitter-base bandgap grading of the IGBT pipes 124 is connected with the anode of the FRD pipes 114, and the emitter-base bandgap grading with the IGBT pipes 125 is connected with the anode of the FRD pipes 115, and the emitter-base bandgap grading with the IGBT pipes 126 is connected with the anode of the FRD pipes 116, and be connected with one end of sampling resistor 138, the other end of the sampling resistor 138 as the SPM 100 low reference voltage end N；
The PFCO ends of the HVIC chips 101 are connected with the grid of IGBT pipes 127；
The emitter-base bandgap grading of the IGBT pipes 127 is connected with the anode of FRD pipes 117, and is used as the PFC low reference voltages end-VP of the SPM 100；
The colelctor electrode of the IGBT pipes 127 is connected with the negative electrode of the FRD pipes 117, the anode of FRD pipes 118, and is used as the PFC ends of the SPM 100；
The negative electrode of the FRD pipes 118, the colelctor electrode of the IGBT pipes 121, the negative electrode of the FRD pipes 111, the colelctor electrode of the IGBT pipes 122, the negative electrode of the FRD pipes 112, the colelctor electrode of the IGBT pipes 123, the negative electrode of the FRD pipes 113 are connected, and typically meet 300V as high voltage the input P, P of the SPM 100.
The effect of the HVIC chips 101 is：
VDD is the power supply anode of the HVIC chips 101, and GND is the power supply negative terminal of the HVIC chips 101；VDD-GND voltages are generally 15V；
VB1 and VS1 are respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO1 is the output end of U phases higher-pressure region；
VB2 and VS2 are respectively the positive pole and negative pole of the power supply of V phases higher-pressure region, and HO2 is the output end of V phases higher-pressure region；
VB3 and VS3 are respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO3 is the output end of W phases higher-pressure region；
LO1, LO2, LO3 are respectively U phases, V phases, the output end of W phase low-pressure areas；
PFCO is the output end of PFC drive circuits；
The 0 of input HIN1, HIN2, HIN3 or 5V logic input signal are passed into output end HO1, HO2, HO3 respectively, LIN1, LIN2, LIN3 signal pass to output end LO1, LO2, LO3 respectively, PFCINP signal passes to output end PFCO, wherein HO1 be VS1 or VS1+15V logic output signal, HO2 be VS2 or VS2+15V logic output signal, HO3 be VS3 or VS3+15V logic output signal, LO1, LO2, LO3, PFCO are 0 or 15V logic output signals.
The input signal of same phase can not be that high level, i.e. HIN1 and LIN1, HIN2 and LIN2, HIN3 and LIN3 can not be high level simultaneously simultaneously.
Described UVS, VVS, WVS and PFC connect inductive load.
PFCINP then presses certain frequency frequent switching between low and high level, make that the IGBT pipes 127 are continuously on off state and the FRD pipes 118 are continuously in freewheeling state, the frequency be generally LIN1 ~ LIN3,2 ~ 4 times of HIN1 ~ HIN3 switching frequencies, and do not contacted directly with LIN1 ~ LIN3, HIN1 ~ HIN3 switching frequency.
In the prior art, the grid of IGBT pipes in SPM 100 is to be easiest to by the part of electrostatic discharges, understood for existing circuit topology, if there is static discharge between COM and N, because the IGBT pipes 124, the IGBT pipes 125, the IGBT pipes 126 are in parallel and have the presence of the resistance 138, electrostatic is to the IGBT pipes 124, the IGBT pipes 125, the influence of the grid of the IGBT pipes 126 is alleviated, but for the IGBT pipes 127, if there is static discharge between COM and-VP, the oxygen composition of deleting of the IGBT pipes 127 will be directly affected, this destruction is possible from production process and causes the IGBT pipes 127 directly destruction, this destruction can be typically detected in the whole link of surveying of producing line, to avoid coming into the market.But if the IGBT pipes 127 simply there occurs micro-damage, just it can not necessarily be detected surveying link eventually, just occur IGBT tube failures in user's application process, in general, IGBT pipes need to bear high-voltage great-current, the overvoltage of the IGBT pipes of failure and excessively stream destruction often caused thermal explosion, were destroyed whole SPM, can also make to burn using the other parts on plate or even cause fire when serious.The antistatic effect of the IGBT pipes 127 how is improved, is the important topic for improving SPM reliability.
The content of the invention
The goal of the invention of the present invention is to provide a kind of high reliability, the SPM of high-adaptability, by voluntarily judging application environment, and IGBT pipes are constituted and protected, under the premise of SPM availability is ensured, improves the antistatic effect of SPM.
To achieve the above object of the invention, the technical solution adopted by the present invention is：
A kind of SPM, including HVIC chips, the first IGBT pipes, the first FRD pipes, the 2nd IGBT pipes, the 2nd FRD pipes, the 3rd IGBT pipes, the 3rd FRD pipes, the 4th IGBT pipes, the 4th FRD pipes, the 5th IGBT pipes, the 5th FRD pipes, the 6th IGBT pipes, the 6th FRD pipes, the 7th IGBT pipes, the 7th FRD pipes, the 8th FRD pipes, the VCC ends of HVIC chips as the SPM low-pressure area power supply anode VDD；
Adaptive circuit is provided with the HVIC chips, the PFCINP ends of HVIC chips connect the first input end of the adaptive circuit；VCC ends connect the power supply anode of the adaptive circuit；GND ends connect the power supply negative terminal of the adaptive circuit；First output end of the adaptive circuit as the HVIC chips PFCC ends；Second output end of the adaptive circuit as the HVIC chips PFCO ends；
In the rising edge of PFCINP signals, the first output end output permanent High level of the adaptive circuit；In the trailing edge of PFCINP signals, the first output end of the adaptive circuit is exported after the preheating setting time Tj of interval continues low level；The output of the second output end and signals of the PFCINP with phase of the adaptive circuit.
In above-mentioned technical proposal, the preheating setting time Tj is selected according to test.Preheating setting time Tj can not be too short, otherwise may cause the 7th IGBT pipe abnormal shutdowns, and time Tj can not be oversize, does not otherwise reach the protecting effect of the 7th IGBT pipes.
Further technical scheme, provided with adjustment circuit, the PFCO ends of the HVIC chips are connected with the first input/output terminal of adjustment circuit；Second input/output terminal of the adjustment circuit is connected with the grid of the 7th IGBT pipes；The PFCC ends of the HVIC chips are connected with the control end of the adjustment circuit；VCC as the adjustment circuit power supply anode；COM as the adjustment circuit power supply negative terminal；It is gate driving circuit characteristic between the first input/output terminal and the second input/output terminal of the adjustment circuit when the control end of the adjustment circuit is high level；It is electrostatic protection characteristic between the first input/output terminal and the second input/output terminal of the adjustment circuit when the control end of the adjustment circuit is low level.
In above-mentioned technical proposal, boostrap circuit is provided with the HVIC chips, structure is：
VCC ends are connected with the anode of the first bootstrap diode, the second bootstrap diode, the 3rd bootstrap diode；
The negative electrode of first bootstrap diode is connected with the VB1 of the HVIC chips；
The negative electrode of second bootstrap diode is connected with the VB2 of the HVIC chips；
The negative electrode of 3rd bootstrap diode is connected with the VB3 of the HVIC chips.
In above-mentioned technical proposal, the HIN1 ends of the HVIC chips are bridge arm input UHIN in the U phases of SPM；
The HIN2 ends of the HVIC chips are bridge arm input VHIN in the V phases of SPM；
The HIN3 ends of the HVIC chips are bridge arm input WHIN in the W phases of SPM；
The LIN1 ends of the HVIC chips are bridge arm input ULIN under the U phases of SPM；
The LIN2 ends of the HVIC chips are bridge arm input VLIN under the V phases of SPM；
The LIN3 ends of the HVIC chips are bridge arm input WLIN under the W phases of SPM；
The PFCINP ends of the HVIC chips are the PFC control signals PFCIN of the SPM；
Here, the tunnel of UHIN, VHIN, WHIN, ULIN, VLIN, WLIN six input of the SPM and PFCIN ends receive 0V or 5V input signal；
The ITRIP ends of the HVIC chips are the MTRIP ends of SPM；
The GND ends of the HVIC chips as SPM low-pressure area power supply negative terminal COM；
The VB1 ends of the HVIC chips connect one end of electric capacity, and are used as the press U phases higher-pressure region power supply anode UVB of SPM；
The HO1 ends of the HVIC chips are connected with the grid of the IGBT pipes of bridge arm the first in press U phases；
The VS1 ends of the HVIC chips are connected with the other end of the colelctor electrode of the IGBT pipes of bridge arm the 4th under the emitter-base bandgap grading, the anode of the first FRD pipes, press U phases of the first IGBT pipes, the negative electrode of the 4th FRD pipes, the electric capacity, and are used as the press U phases higher-pressure region power supply negative terminal UVS of SPM；
The VB2 ends of the HVIC chips connect one end of electric capacity, are used as the press U phases higher-pressure region power supply anode VVB of SPM；
The HO2 ends of the HVIC chips are connected with the grid of the IGBT pipes of bridge arm the 2nd in press V phases；
The VS2 ends of the HVIC chips are connected with the other end of the colelctor electrode of the IGBT pipes of bridge arm the 5th under the emitter-base bandgap grading, the anode of the 2nd FRD pipes, press V phases of the 2nd IGBT pipes, the negative electrode of the 5th FRD pipes, the electric capacity, and are used as the press V phases higher-pressure region power supply negative terminal VVS of SPM；
The VB3 ends of the HVIC chips connect one end of electric capacity, are used as the press W phases higher-pressure region power supply anode WVB of SPM；
The HO3 ends of the HVIC chips are connected with the grid of the IGBT pipes of bridge arm the 3rd in press W phases；
The VS3 ends of the HVIC chips are connected with the other end of the colelctor electrode of the IGBT pipes of bridge arm the 6th under the emitter-base bandgap grading, the anode of the 3rd FRD pipes, press W phases of the 3rd IGBT pipes, the negative electrode of the 6th FRD pipes, the electric capacity, and are used as the press W phases higher-pressure region power supply negative terminal WVS of SPM；
The LO1 ends of the HVIC chips are connected with the grid of the 4th IGBT pipes；
The LO2 ends of the HVIC chips are connected with the grid of the 5th IGBT pipes；
The LO3 ends of the HVIC chips are connected with the grid of the 6th IGBT pipes；
The emitter-base bandgap grading of the 4th IGBT pipes is connected with the anode of the 4th FRD pipes, and is used as the press U phase low reference voltages end UN of SPM；
The emitter-base bandgap grading of the 5th IGBT pipes is connected with the anode of the 5th FRD pipes, and is used as the press V phase low reference voltages end VN of SPM；
The emitter-base bandgap grading of the 6th IGBT pipes is connected with the anode of the 6th FRD pipes, and is used as the press W phase low reference voltages end WN of SPM；
The emitter-base bandgap grading of the 7th IGBT pipes is connected with the anode of the 7th FRD pipes, and is used as the PFC low reference voltages end-VP of SPM；
The colelctor electrode of the 7th IGBT pipes is connected with the negative electrode of the 7th FRD pipes, the anode of the 8th FRD pipes, and is used as the PFC ends of SPM；
Negative electrode, the colelctor electrode of the first IGBT pipes, the negative electrode of the first FRD pipes, the colelctor electrode of the 2nd IGBT pipes, the negative electrode of the 2nd FRD pipes, the colelctor electrode of the 3rd IGBT pipes, the negative electrode of the 3rd FRD pipes of the 8th FRD pipes are connected, and typically meet 300V as high voltage the input P, P of SPM.
In the HVIC chips：
VDD is the HVIC chip power supplies power positive end, and GND is the power supply negative terminal of the HVIC chips；VDD-GND voltages are generally 15V；
VB1 and VS1 are respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO1 is the output end of U phases higher-pressure region；
VB2 and VS2 are respectively the positive pole and negative pole of the power supply of V phases higher-pressure region, and HO2 is the output end of V phases higher-pressure region；
VB3 and VS3 are respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO3 is the output end of W phases higher-pressure region；
LO1, LO2, LO3 are respectively U phases, V phases, the output end of W phase low-pressure areas；
PFCO is the output end of PFC drive circuits；
The 0 of input HIN1, HIN2, HIN3 or 5V logic input signal is passed into output end HO1, HO2, HO3 respectively, LIN1, LIN2, LIN3 signal pass to output end LO1, LO2, LO3 respectively, and PFCINP signal passes to output end PFCO.Wherein HO1 be VS1 or VS1+15V logic output signal, HO2 be VS2 or VS2+15V logic output signal, HO3 be VS3 or VS3+15V logic output signal, LO1, LO2, LO3, PFCO are 0 or 15V logic output signals.
Because above-mentioned technical proposal is used, the present invention has following advantages compared with prior art：
1st, in the present invention; the grid of 7th IGBT pipes accesses different circuits according to the situation of drive signal; when PFCINP is high level; the 7th IGBT pipes i.e. will be in the conduction state; it is now hardly possible to have electrostatic appearance, therefore be a gate driving circuit, when PFCINP is low level; the 7th IGBT pipes will be in nonconducting state, now obtain electrostatic discharge protective circuit protection；So that the SPM of the present invention obtains electrostatic discharge protection mechanism on the premise of normal work is not influenceed; maintain the stability, availability, robustness of system; the user satisfaction of product is improved, reduction product is complained, and the brand image to maintenance terminal product is greatly facilitated effect.
2nd, in terms of the external function pin of the SPM of the present invention, SPM of the invention and existing SPM are completely compatible, directly can be replaced with existing SPM.
Brief description of the drawings
Fig. 1 is the circuit diagram of SPM in the prior art.
Fig. 2 is the pin schematic diagram of SPM in the prior art.
Fig. 3 is the circuit diagram of the SPM of the embodiment of the present invention.
Fig. 4 is the circuit structure diagram of the embodiment of the present invention.
Fig. 5 is the key signal timing diagram of the embodiment of the present invention.
Embodiment
Below in conjunction with the accompanying drawings and embodiment the invention will be further described：
Embodiment one：It is shown in Figure 3, a kind of SPM 1100, including HVIC chips 1101, the first IGBT pipes 1121, the first FRD pipes 1111, the 2nd IGBT pipes 1122, the 2nd FRD pipes 1112, the 3rd IGBT pipes 1123, the 3rd FRD pipes 1113, the 4th IGBT pipes 1124, the 4th FRD pipes 1114, the 5th IGBT pipes 1125, the 5th FRD pipes 1115, the 6th IGBT pipes 1126, the 6th FRD pipes 1116, the 7th IGBT pipes 1127, the 7th FRD pipes 1117, the 8th FRD pipes 1118, the VCC ends of HVIC chips 1101 as the SPM low-pressure area power supply anode VDD.Adaptive circuit 1105 is provided with the HVIC chips 1101.
Referring to Fig. 4, the structure of the adaptive circuit 1105 is as follows：
PFCINP is connected with the input of level shifting circuit 2010；
VDD is the power supply anode of the level shifting circuit 2010；
COM is the power supply negative terminal of the level shifting circuit 2010
The input of the output end NAND gate 2001 of the level shifting circuit 2010, the input of NOT gate 2003, the input of NOT gate 2011, the input of NOT gate 2013, the input of NOT gate 2024, one end of electric capacity 2028 are connected；
Another termination COM of the electric capacity 2028；
The input of the output end NAND gate 2002 of the NOT gate 2001 is connected；
The input of the output end NAND gate 2004 of the NOT gate 2003, one end of electric capacity 2008 are connected；
Another termination COM of the electric capacity 2008；
The input of the output end NAND gate 2012 of the NOT gate 2011 is connected；
The input of the output end NAND gate 2014 of the NOT gate 2013, one end of electric capacity 2018 are connected；
Another termination COM of the electric capacity 2018；
The input of the output end NAND gate 2005 of the NOT gate 2004, one end of electric capacity 2009 are connected；
Another termination COM of the electric capacity 2009；
The input of the output end NAND gate 2015 of the NOT gate 2014, one end of electric capacity 2019 are connected；
Another termination COM of the electric capacity 2019；
The output end of the NOT gate 2002 connects one of input of NAND gate 2006；
The output end of the NOT gate 2005 connects another input of the NAND gate 2006；
The output end of the NOT gate 2012 connects one of input of NAND gate 2016；
The output end of the NOT gate 2015 connects another input of the NAND gate 2016；
The output end of the NAND gate 2006 connects the input of NOT gate 2007；
The output end connection of the nor gate 2016 takes 2017 input；
The output end of the NOT gate 2007 is connected with the S ends of rest-set flip-flop 2023；
The input of the output end connection NOT gate 2021 of the NOT gate 2017, one end of electric capacity 2020；
Another termination COM of the electric capacity 2020；
The output end of the NOT gate 2021 connects the input of NOT gate 2022；
The R ends of the output termination rest-set flip-flop 2023 of the NOT gate 2022；
The Q ends of the rest-set flip-flop 2023 are the first output end of the adaptive circuit 1105；
The input of the output termination NOT gate 2025 of the NOT gate 2024, one end of electric capacity 2029；
Another termination COM of the electric capacity 2029；
The input of the output termination NOT gate 2026 of the NOT gate 2025, one end of electric capacity 2030；
Another termination COM of the electric capacity 2030；
The input of the output termination NOT gate 2027 of the NOT gate 2026, one end of electric capacity 2031；
Another termination COM of the electric capacity 2031；
The output end of the NOT gate 2027 is the second output end of the adaptive circuit 1105；
First output end of the adaptive circuit 1105 connects the control end of the adjustment circuit 1141；
Second output end of the adaptive circuit 1105 connects the first input/output terminal of the adjustment circuit 1141；
The control end of the adjustment circuit 1141 is connected in the inside of the adjustment circuit 1141 with the control end of analog switch 2032, the control end of analog switch 2041；
First input/output terminal of the adjustment circuit 1141 is connected with the fixing end of the analog switch 2032；
1 selection end of the analog switch 2032 is connected with the grid of PMOS 2033, the grid of NMOS tube 2035；
The source electrode and substrate of the PMOS 2033 are connected with VDD；
The source electrode of the NMOS tube 2035 is connected with substrate with COM；
The drain electrode of the PMOS 2033 is connected with the drain electrode of the NMOS tube 2035 and is connected in the negative electrode of one end of resistance 2036, diode 2034；
The other end of the resistance 2036, which is connected with the anode of the diode 2034 and is connected the 1 of the analog switch 2041, selects end；
0 selection end of the analog switch 2031 is connected with one end of resistance 2037；
The other end of the resistance 2037 is connected with the drain electrode of one end of resistance 2038, NMOS tube 2040；
Grid, the substrate of the NMOS tube 2040 are connected with source electrode and meet COM；
The draining of another termination PMOS 2039 of the resistance 2038,0 selection end of the analog switch 2041；
Grid, the source electrode of the PMOS 2039 are connected with substrate and meet VDD；
The fixing end of the analog switch 2041 is the second input/output terminal of the adjustment circuit 1141.
Illustrate the principle and each key parameter value of the present embodiment below：
The level shifting circuit 2010 is the logical signal that PFCINP 0 ~ 5V or 0 ~ 3.3V logical signal is converted to 0 ~ 15V；
The effect of PLUSEON parts is rising edge one high level pulse signal of generation in PFCINP in Fig. 4；
The effect of PLUSEOFF parts is trailing edge one high level pulse signal of generation in PFCINP in Fig. 4；
Usually the width of pulse signal can be designed as 100ns or so, 2 times or so of the minimum dimension of technique permission may be selected in so described NOT gate 2003, the NOT gate 2004, the NOT gate 2005, the NOT gate 2013, the NOT gate 2014, the NOT gate 2015, the electric capacity 2008, the electric capacity 2009 may be designed as 1 ~ 2pF, the electric capacity 2018, the electric capacity 2019 may be designed as 2 ~ 3pF, then at A and B, 90ns ~ 120ns pulse signal can be obtained respectively in PFCINP rising edge and trailing edge；
B signal reaches the R ends of the rest-set flip-flop 2023 after the delay for the time delay network that the electric capacity 2020, the NOT gate 2021, the NOT gate 2022 are constituted；
So as to,
In PFCINP rising edge, the S ends of the rest-set flip-flop 2023 are high level and R ends are low level, so that the Q ends of the rest-set flip-flop 2023 are set to high level, i.e., the first output end output high level of described adaptive circuit 1105；
In PFCINP trailing edge, the S ends of the rest-set flip-flop 2023 are low level and R ends are high level, so that the Q ends of the rest-set flip-flop 2023 are reset to low level, i.e., the first output end output low level of described adaptive circuit 1105；
The electric capacity 2028, the electric capacity 2029, the electric capacity 2030, the capacitance of the electric capacity 2031 may be designed as 1pF, and the electric capacity 2020 can be designed as 10pF, so design be in order to
PFCINP from low transition be high level when, the set signal of the rest-set flip-flop 2023 reaches the first output end of the adaptive circuit 1105, is designated as COUT1, signal of the time prior to PFCINP be transferred to the second output end of the adaptive circuit 1105, be designated as COUT2, time；
When PFCINP is converted to low level from high level, the time of the first output end of the reset signal arrival adaptive circuit 1105 of the rest-set flip-flop 2023 is transferred to the time of the second output end of the adaptive circuit 1105 after PFCINP signal；
So as to which the signal for first input/output terminal of the control signal prior to the adjustment circuit 1141 for ensureing the adjustment circuit 1141 reaches the adjustment circuit 1141；
Timing diagram such as Fig. 5；
When the control signal of the adjustment circuit 1141 is high level, the fixing end of the analog switch 2032 is connected with 1 selection end, and the fixing end of the analog switch 2041 is connected with 1 selection end, so that：
The PMOS 2033, the composition drive circuit of the NMOS tube 2035, the size of the PMOS 2033, which is contemplated that, is designed to 1000 μm/10 μm of breadth length ratio, the size of the NMOS tube 2035, which is contemplated that, is designed to 500 μm/10 μm of breadth length ratio, so as to obtain 500mA or so driving force；
The resistance, which is contemplated that, is designed as the Ω of 10 Ω ~ 50, the switching speed for adjusting the follow-up IGBT pipes 1127；The diode that current capacity is 0.1mA or so may be selected in the diode, the shut-off hangover for improving the follow-up IGBT pipes 1127；
When the control signal of the adjustment circuit 1141 is low level, the fixing end of the analog switch 2032 is connected with 0 selection end, and the fixing end of the analog switch 2041 is connected with 0 selection end, so that：
Negative electrostatic protection is carried out using the body diode characteristic of the NMOS tube 2037, positive electrostatic protection is carried out using the body diode characteristic of the PMOS 2038；The NMOS tube size, which is contemplated that, is designed as 800 μm/50 μm, and the PMOS size, which is contemplated that, is designed as 1200 μm/60 μm；
The resistance 2037 and the resistance 2038 are it is contemplated that use BASE resistance, P-WELL sizes, which are contemplated that, is designed to 200 μm/50 μm, for lifting conveyance capacity when electrostatic arrives.
Claims (5)
1. a kind of SPM, including HVIC chips (1101), first IGBT manages (1121), first FRD manages (1111), 2nd IGBT manages (1122), 2nd FRD manages (1112), 3rd IGBT manages (1123), 3rd FRD manages (1113), 4th IGBT manages (1124), 4th FRD manages (1114), 5th IGBT manages (1125), 5th FRD manages (1115), 6th IGBT manages (1126), 6th FRD manages (1116), 7th IGBT manages (1127), 7th FRD manages (1117), 8th FRD manages (1118), the VCC ends of HVIC chips (1101) as the SPM low-pressure area power supply anode VDD；It is characterized in that：
Adaptive circuit (1105) is provided with the HVIC chips (1101), the PFCINP ends of HVIC chips (1101) connect the first input end of the adaptive circuit (1105)；VCC ends connect the power supply anode of the adaptive circuit (1105)；GND ends connect the power supply negative terminal of the adaptive circuit (1105)；First output end of the adaptive circuit (1105) as the HVIC chips (1101) PFCC ends；Second output end of the adaptive circuit (1105) as the HVIC chips (1101) PFCO ends；
In the rising edge of PFCINP signals, the first output end output permanent High level of the adaptive circuit (1105)；In the trailing edge of PFCINP signals, the first output end of the adaptive circuit (1105) is exported after the preheating setting time Tj of interval continues low level；The output of the second output end and signals of the PFCINP with phase of the adaptive circuit (1105).
2. SPM according to claim 1, it is characterised in that：Provided with adjustment circuit (1141), the PFCO ends of the HVIC chips (1101) are connected with the first input/output terminal of adjustment circuit (1141)；Second input/output terminal of the adjustment circuit (1141) is connected with the 7th IGBT grids for managing (1127)；The PFCC ends of the HVIC chips (1101) are connected with the control end of the adjustment circuit (1141)；VCC as the adjustment circuit (1141) power supply anode；COM as the adjustment circuit (1141) power supply negative terminal；It is gate driving circuit characteristic between the first input/output terminal and the second input/output terminal of the adjustment circuit (1141) when the control end of the adjustment circuit (1141) is high level；It is electrostatic protection characteristic between the first input/output terminal and the second input/output terminal of the adjustment circuit (1141) when the control end of the adjustment circuit (1141) is low level.
3. SPM according to claim 1, it is characterised in that：
Boostrap circuit is provided with the HVIC chips (1101), structure is：
VCC ends are connected with the anode of the first bootstrap diode (1102), the second bootstrap diode (1103), the 3rd bootstrap diode (1104)；
The negative electrode of first bootstrap diode (1102) is connected with the VB1 of the HVIC chips (1101)；
The negative electrode of second bootstrap diode (1103) is connected with the VB2 of the HVIC chips (1101)；
The negative electrode of 3rd bootstrap diode (1104) is connected with the VB3 of the HVIC chips (1101).
4. SPM according to claim 1, it is characterised in that：
The HIN1 ends of the HVIC chips (1101) are bridge arm input UHIN in the U phases of SPM；
The HIN2 ends of the HVIC chips (1101) are bridge arm input VHIN in the V phases of SPM；
The HIN3 ends of the HVIC chips (1101) are bridge arm input WHIN in the W phases of SPM；
The LIN1 ends of the HVIC chips (1101) are bridge arm input ULIN under the U phases of SPM；
The LIN2 ends of the HVIC chips (1101) are bridge arm input VLIN under the V phases of SPM；
The LIN3 ends of the HVIC chips (1101) are bridge arm input WLIN under the W phases of SPM；
The PFCINP ends of the HVIC chips (1101) are the PFC control signals PFCIN of the SPM；
The ITRIP ends of the HVIC chips (1101) are the MTRIP ends of SPM；
The GND ends of the HVIC chips (1101) as SPM low-pressure area power supply negative terminal COM；
One end of the VB1 ends connection electric capacity (1131) of the HVIC chips (1101), and it is used as the press U phases higher-pressure region power supply anode UVB of SPM；
The HO1 ends of the HVIC chips (1101) are connected with the grids for managing (1121) of the IGBT of bridge arm the first in press U phases；
The colelctor electrode of the IGBT of bridge arm the 4th pipes (1124), the negative electrode of the 4th FRD pipes (1114), the other end of the electric capacity (1131) under the emitter-base bandgap grading of (1121), the anode of the first FRD pipes (1111), press U phases are managed with the first IGBT and is connected, and is used as the press U phases higher-pressure region power supply negative terminal UVS of the SPM in the VS1 ends of the HVIC chips (1101)；
One end of the VB2 ends connection electric capacity (1132) of the HVIC chips (1101), is used as the press U phases higher-pressure region power supply anode VVB of the SPM；
The HO2 ends of the HVIC chips (1101) are connected with the grids for managing (1122) of the IGBT of bridge arm the 2nd in press V phases；
The colelctor electrode of the IGBT of bridge arm the 5th pipes (1125), the negative electrode of the 5th FRD pipes (1115), the other end of the electric capacity (1132) under the emitter-base bandgap grading of (1122), the anode of the 2nd FRD pipes (1112), press V phases are managed with the 2nd IGBT and is connected, and is used as the press V phases higher-pressure region power supply negative terminal VVS of SPM in the VS2 ends of the HVIC chips (1101)；
One end of the VB3 ends connection electric capacity (1133) of the HVIC chips (1101), is used as the press W phases higher-pressure region power supply anode WVB of SPM；
The HO3 ends of the HVIC chips (1101) are connected with the grids for managing (1123) of the IGBT of bridge arm the 3rd in press W phases；
The colelctor electrode of the IGBT of bridge arm the 6th pipes (1126), the negative electrode of the 6th FRD pipes (1116), the other end of the electric capacity (1133) under the emitter-base bandgap grading of (1123), the anode of the 3rd FRD pipes (1113), press W phases are managed with the 3rd IGBT and is connected, and is used as the press W phases higher-pressure region power supply negative terminal WVS of SPM in the VS3 ends of the HVIC chips (1101)；
The LO1 ends of the HVIC chips (1101) are connected with the 4th IGBT grids for managing (1124)；
The LO2 ends of the HVIC chips (1101) are connected with the 5th IGBT grids for managing (1125)；
The LO3 ends of the HVIC chips (1101) are connected with the 6th IGBT grids for managing (1126)；
The emitter-base bandgap grading of the 4th IGBT pipes (1124) is connected with the 4th FRD anodes for managing (1114), and is used as the press U phase low reference voltages end UN of SPM；
The emitter-base bandgap grading of the 5th IGBT pipes (1125) is connected with the 5th FRD anodes for managing (1115), and is used as the press V phase low reference voltages end VN of SPM；
The emitter-base bandgap grading of the 6th IGBT pipes (1126) is connected with the 6th FRD anodes for managing (1116), and is used as the press W phase low reference voltages end WN of SPM；
The emitter-base bandgap grading of the 7th IGBT pipes (1127) is connected with the 7th FRD anodes for managing (1117), and is used as the PFC low reference voltages end-VP of SPM；
The colelctor electrode of the 7th IGBT pipes (1127) manages the negative electrode of (1117), the anode of the 8th FRD pipes (1118) with the 7th FRD and is connected, and is used as the PFC ends of SPM；
Negative electrode, the colelctor electrode of the first IGBT pipes (1121), the negative electrode of the first FRD pipes (1111), the colelctor electrode of the 2nd IGBT pipes (1122), the negative electrode of the 2nd FRD pipes (1112), the colelctor electrode of the 3rd IGBT pipes (1123), the negative electrode of the 3rd FRD pipes (1113) of the 8th FRD pipes (1118) are connected, and are used as the high voltage input P of SPM.
5. SPM according to claim 1, it is characterised in that：
In the HVIC chips (1101)：
VDD is HVIC chips (1101) the power supply anode, and GND is the power supply negative terminal of the HVIC chips (1101)；
VB1 and VS1 are respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO1 is the output end of U phases higher-pressure region；
VB2 and VS2 are respectively the positive pole and negative pole of the power supply of V phases higher-pressure region, and HO2 is the output end of V phases higher-pressure region；
VB3 and VS3 are respectively the positive pole and negative pole of the power supply of U phases higher-pressure region, and HO3 is the output end of W phases higher-pressure region；
LO1, LO2, LO3 are respectively U phases, V phases, the output end of W phase low-pressure areas；
PFCO is the output end of PFC drive circuits；
The 0 of input HIN1, HIN2, HIN3 or 5V logic input signal is passed into output end HO1, HO2, HO3 respectively, LIN1, LIN2, LIN3 signal pass to output end LO1, LO2, LO3 respectively, and PFCINP signal passes to output end PFCO.
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN109921675A (en) * | 2019-04-29 | 2019-06-21 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
| CN110061632A (en) * | 2019-04-29 | 2019-07-26 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
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| CN204179925U (en) * | 2014-10-20 | 2015-02-25 | 广东美的集团芜湖制冷设备有限公司 | Intelligent power module and air conditioner |
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| CN203278686U (en) * | 2013-05-20 | 2013-11-06 | 广东美的制冷设备有限公司 | Intelligent power module |
| CN103606901A (en) * | 2013-11-25 | 2014-02-26 | 广东美的制冷设备有限公司 | Electrostatic protection device, intelligent power module and frequency conversion household appliance |
| CN204179925U (en) * | 2014-10-20 | 2015-02-25 | 广东美的集团芜湖制冷设备有限公司 | Intelligent power module and air conditioner |
| CN105322822A (en) * | 2015-11-30 | 2016-02-10 | 重庆美的制冷设备有限公司 | Intelligent power module and air conditioner |
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| CN109921675A (en) * | 2019-04-29 | 2019-06-21 | 广东美的制冷设备有限公司 | Intelligent power module and air conditioner |
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