CN107274855A - Gate drive circuit and drive method thereof - Google Patents
Gate drive circuit and drive method thereof Download PDFInfo
- Publication number
- CN107274855A CN107274855A CN201710726273.8A CN201710726273A CN107274855A CN 107274855 A CN107274855 A CN 107274855A CN 201710726273 A CN201710726273 A CN 201710726273A CN 107274855 A CN107274855 A CN 107274855A
- Authority
- CN
- China
- Prior art keywords
- clock signal
- switch
- signal
- coupled
- shift register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 238000000034 method Methods 0.000 title claims description 17
- 230000000087 stabilizing effect Effects 0.000 claims abstract description 33
- 230000000737 periodic effect Effects 0.000 claims abstract description 4
- 238000010408 sweeping Methods 0.000 claims description 20
- 210000001367 artery Anatomy 0.000 claims description 8
- 230000008878 coupling Effects 0.000 claims description 8
- 238000010168 coupling process Methods 0.000 claims description 8
- 238000005859 coupling reaction Methods 0.000 claims description 8
- 210000003462 vein Anatomy 0.000 claims description 8
- 230000002457 bidirectional effect Effects 0.000 abstract description 3
- 238000010586 diagram Methods 0.000 description 19
- 230000008859 change Effects 0.000 description 12
- 230000000694 effects Effects 0.000 description 7
- 230000005611 electricity Effects 0.000 description 6
- 238000006073 displacement reaction Methods 0.000 description 5
- 239000004973 liquid crystal related substance Substances 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000013499 data model Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 1
- 230000002452 interceptive effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 230000001960 triggered effect Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
- G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Shift Register Type Memory (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
- Liquid Crystal Display Device Control (AREA)
Abstract
The invention discloses a grid driving circuit, which comprises a plurality of stages of shift registers, wherein the shift registers can receive a first clock pulse signal, a second clock pulse signal, a third clock pulse signal and a fourth clock pulse signal, and each stage of shift registers respectively comprises a first switch, a voltage stabilizing module and a bidirectional input module. The first switch is coupled to the first clock signal, the current stage shift register output terminal and the first node. The voltage stabilizing module selectively conducts the first node to a previous stage shift register output end or a next stage shift register output end according to the second clock signal, the fourth clock signal and the scanning sequence signal. The bidirectional input module is coupled to the first node and is used for receiving a scanning sequence signal. In addition, the first clock signal, the second clock signal and the fourth clock signal are periodic clock signals with different phases respectively.
Description
Technical field
The present invention on a kind of drive circuit and its driving method, espespecially a kind of drive circuit for display panel and its
Driving method.
Background technology
With the progress of science and technology, the volume and weight of display are little by little lightening, with response to modern Man's Demands.With
Exemplified by liquid crystal display, Array gate driving (GOA, gate driver on array) technology is applied to liquid crystal display
On, furthermore, it is understood that Array gate actuation techniques are directly by the gate driving circuit system for driving liquid crystal display pixel
Make on the substrate of array, therefore production process can be reduced, cost is reduced, and then make it that the volume and weight of liquid crystal display can
It is lightening.
The gate driving circuit of existing use Array gate actuation techniques is only supported unidirectionally due to the reason of circuit structure
Scanning.However, different panels due to the position of its soft board (FPC, flexible print circuit) it is different the reason for, only
Support the gate driving circuit of simple scanning and various panels can not be applied to.
The content of the invention
One embodiment of this case discloses a kind of gate driving circuit, comprising stages shift buffer, can receive the first clock pulse
Signal, the second clock signal, the 3rd clock signal and the 4th clock signal, it is central per one-level shift registor each self-contained first
Switch, Voltage stabilizing module and two directions' inputing module.The first end of first switch receives the first clock signal, the second of first switch
End is coupled to when level shift register output end, and the control end of first switch is coupled to first node.When Voltage stabilizing module receives second
Arteries and veins signal, the 4th clock signal and scanning sequence signal, Voltage stabilizing module are coupled to first node, and Voltage stabilizing module is according to scanning
Order signal, the second clock signal and the 4th clock signal, are optionally conducted to previous stage shift register defeated by first node
Go out end or rear stage shift register output end.Two directions' inputing module receives scanning sequence signal, and two directions' inputing module couples are extremely
First node, wherein the first clock signal, the second clock signal and the 4th clock signal are respectively the different periodicity of phase
Clock signal.
One embodiment of this case discloses a kind of gate driving circuit, and gate driving circuit includes stages shift buffer, often
Each self-contained first switch of one-level shift registor, the 3rd switch, the 4th switch and two directions' inputing module.The first of first switch
End receives clock signal, and the second end of first switch is coupled to when level shift register output end, the control end coupling of first switch
It is connected to first node.The first end of second switch is coupled to the output end of shift registor.The electrical coupling of first end of 3rd switch
First node is connected to, the second end of the 3rd switch is electrically coupled to previous stage shift register output end, the control end of the 3rd switch
It is coupled to the 4th clock signal.The first end of 4th switch is electrically coupled to first node, the electrical coupling in the second end of the 4th switch
Rear stage shift register output end is connected to, the control end of the 4th switch is coupled to the second clock signal.Two directions' inputing module couples
To first node.
This case discloses a kind of driving method, and driving method is used for driving stages shift buffer, per one-level shift registor
The first clock signal, the second clock signal are received respectively, the 3rd clock signal, the 4th clock signal, are just being swept signal and counter are being swept
Signal, driving method is comprised the steps of.When just sweeping signal for high level, the first clock signal, second are opened in sequentially circulation
Clock signal, the 3rd clock signal and the 4th clock signal, wherein the first clock signal, the second clock signal, the 3rd clock pulse
The overlapping pulses of two adjacent clock signals among signal and the 4th clock signal, before the 4th clock signal is to trigger
One-level shift register is exported, and the first two grade of shift register output and the first clock signal work as the output of level shift register to trigger.
When it is counter sweep signal for high level when, the 4th clock signal, the 3rd clock signal, the second clock signal and the are opened in sequentially circulation
One clock signal, wherein two among the 4th clock signal, the 3rd clock signal, the second clock signal and the first clock signal
The overlapping pulses of adjacent clock signal, the second clock signal is to trigger the output of rear stage shift register, rear two grades of displacements
Temporary output and the first clock signal work as the output of level shift register to trigger.
Brief description of the drawings
For the above and other purpose, feature, advantage and embodiment of this disclosure can be become apparent, institute's accompanying drawings
Be described as follows：
Fig. 1 is the functional block diagram of the gate driving circuit according to depicted in one embodiment of the invention.
Fig. 2A in gate driving circuit according to Fig. 1 when the circuit diagram of level shift registor.
Fig. 2 B for the previous stage shift registor in gate driving circuit according to Fig. 1 circuit diagram.
The method stream of many shift registors of gate driving circuits of the Fig. 3 for driving according to depicted in one embodiment of the invention
Cheng Tu.
Fig. 4 A perform the timing diagram during operation of forward scan for the gate driving circuit according to Fig. 1.
Fig. 4 B perform the timing diagram during operation of reverse scan for the gate driving circuit according to Fig. 1.
Fig. 5 in gate driving circuit according to Fig. 1 when level shift registor another implementation aspect circuit diagram.
Fig. 6 is timing diagram of shift registor when forward scan according to Fig. 5.
Fig. 7 in gate driving circuit according to Fig. 1 when level shift registor another implementation aspect circuit diagram.
Fig. 8 in gate driving circuit according to Fig. 1 when level shift registor another implementation aspect circuit diagram.
Wherein, reference：
100 gate driving circuits
110 Voltage stabilizing modules
110' Voltage stabilizing modules
110 " Voltage stabilizing modules
110 " ' Voltage stabilizing modules
120 two directions' inputing modules
120' two directions' inputing modules
120 " two directions' inputing modules
120 " ' two directions' inputing modules
The clock signals of CK1 first
The clock signals of CK2 second
The clock signals of CK3 the 3rd
The clock signals of CK4 the 4th
The first two grade of shift register output end of Gn-2
Gn-1 previous stage shift register output ends
Gn works as level shift register output end
Gn+1 rear stage shift register output ends
Two grades of shift register output ends after Gn+2
The first two grade of shift registor of SRn-2
SRn-1 previous stage shift registors
SRn works as level shift registor
SRn' works as level shift registor
SRn " is when level shift registor
SRn " ' is when level shift registor
SRn+1 rear stage shift registors
Two grades of shift registors after SRn+2
T1 first switches
T2 second switches
T3 the 3rd is switched
T4 the 4th is switched
T5 the 5th is switched
T8 the 8th is switched
T9 the 9th is switched
T10 the tenth is switched
T11 the 11st is switched
T12 the 12nd is switched
The electric capacity of C1 first
D2U is counter to sweep signal
U2D just sweeps signal
ND1 first nodes
The discharge paths of P1 first
The discharge paths of P2 second
RST reset signals
Vss the first system voltages
VGH second system voltages
T0~t6 periods
Embodiment
Hereafter institute's accompanying drawings are coordinated to elaborate for embodiment, to more fully understand the aspect of this case, but provided
Embodiment simultaneously is not used to limit the scope that this case is covered, and the description of structure operation is not used to limit the order of its execution, appoints
What structure for being reconfigured by element, it is produced with it is equal the effects such as device, be all the scope that this case is covered.
Fig. 1 is refer to, it is the functional block diagram of the gate driving circuit 100 according to depicted in one embodiment of the invention.
Gate driving circuit 100 includes stages shift buffer SRn-1, SRn, SRn+1 ... etc..For convenience of description, in Fig. 1
Only show previous stage shift registor SRn-1, as level shift registor SRn and rear stage shift registor SRn+1.Practical application
In, gate driving circuit 100 can include more stages shift registor, for example, work as grid according to the number of required gate lines
When the number of gate lines corresponding to pole drive circuit 100 is 256, gate driving circuit 100 can be temporary comprising 256 grades of displacements
Storage, previous stage shift registor SRn-1 herein, is used to as level shift registor SRn and rear stage shift registor SRn+1
Wherein adjacent continuous three-level shift registor is shown, the electricity that n is any positive integer can be deduced by above-mentioned three-level shift registor
Road framework, this can know about for the people of existing skill, does not repeat separately herein.
By exemplified by level shift registor SRn, when level shift registor SRn input receives scanning sequence signal respectively
(in this embodiment comprising just sweep signal U2D and counter sweep signal D2U) and the first clock signal CK1, the second clock signal CK2,
3rd clock signal CK3 and the 4th clock signal CK4, and each input is electrically coupled to the first two grade of shift register output respectively
Hold Gn-2, previous stage shift register output end Gn-1, rear stage shift register output end Gn+1, rear two grades of shift register output ends
Gn+2 and the first system voltage Vss.
As level shift registor SRn when level shift register output end Gn is electrically coupled to the first two grade of shift registor SRn-
Input, previous stage shift registor SRn-1 input, the rear stage shift registor SRn+1 input of 2 (not shown)
And the input of rear two grades of shift registors SRn+2 (not shown).
In this embodiment, scanning sequence signal comprising just sweep signal U2D and it is counter sweep signal D2U, just sweeping signal U2D and instead
Sweep signal D2U has opposite level respectively, to represent the current scanning sequence of gate driving circuit 100 (by prime backward
Level is scanned or scanned from rear class to prime).First clock signal CK1, the second clock signal CK2, the 3rd clock signal CK3 with
And the 4th clock signal CK4 be respectively the different periodic clock signal of phase.
Shift registor (such as previous stage shift registor SRn-1 and rear stage shift registor SRn+1 of other grades
Deng) then follow when level shift registor SRn configuration mode, therefore be not repeated here.
Fig. 2A and Fig. 3 is refer to again.Fig. 2A is works as level shift register in gate driving circuit 100 according to Fig. 1
Device SRn circuit diagram, Fig. 3 is a kind of flow chart of driving method in the embodiment according to this disclosure of documents.Drive shown in Fig. 3
Dynamic method can work as level shift registor SRn for driving Fig. 2A.
As shown in Figure 2 A, when level shift registor SRn comprising first switch T1, second switch T2, Voltage stabilizing module 110 and
Two directions' inputing module 120.In the present embodiment, first switch T1 first end receives the first clock signal CK1, first switch T1
The second end be coupled to when level shift register output end Gn, first switch T1 control end are coupled to first node ND1.Second opens
The first end for closing T2 is coupled to when level shift register output end Gn, second switch T2 the second end are electrically coupled to the first system electricity
Vss is pressed, second switch T2 control end receives the 3rd clock signal CK3.
Voltage stabilizing module 110 receives the second clock signal CK2, the 4th clock signal CK4 and scanning sequence signal and (just swept
Signal U2D and counter sweep signal D2U), Voltage stabilizing module 110 is coupled to first node ND1, and Voltage stabilizing module 110 is according to scanning sequence
First node ND1, is optionally conducted to previous by signal U2D, D2U, the second clock signal CK2 and the 4th clock signal CK4
Level shift register output end Gn-1 or rear stage shift register output end Gn+1.
In an embodiment, is electrically coupled to when level shift registor SRn further includes the first electric capacity C1, the first electric capacity C1
One node ND1 and between level keeps in output end Gn.
In an embodiment, Voltage stabilizing module 110 is opened comprising the 3rd switch T3, the 4th switch T4, the 8th switch T8 and the 9th
Close T9.3rd switch T3 first end is electrically coupled to first node ND1, and it is defeated that the second end is electrically coupled to previous stage shift register
Go out and hold Gn-1, control end then receives the 4th clock signal CK4.In addition, the 4th switch T4 first end is electrically coupled to first segment
Point ND1, the second end is electrically coupled to rear stage shift register output end Gn+1, and control end then receives the second clock signal CK2.This
Outside, the 8th switch T8 is coupled between the switches of first node ND1 and the 3rd T3.Furthermore, the 8th switch T8 first end
First node ND1 is electrically coupled to, the second end is electrically coupled to the 3rd switch T3 first end, and control end then receives and just sweeps signal
U2D.9th switch T9 is coupled between the switches of first node ND1 and the 4th T4.In detail, the 9th switch T9 first end is electrical
It is coupled to first node ND1, the second end is electrically coupled to the 4th switch T4 first end, control end, which is then received, counter sweeps signal D2U.
In the present embodiment, two directions' inputing module 120 receives scanning sequence signal and (is just sweeping signal U2D and counter sweeping signal
), and two directions' inputing module 120 is coupled to first node ND1 D2U.Specifically, two directions' inputing module 120 includes the 6th switch
The switches of T6 and the 7th T7.Wherein, the 6th switch T6 first end, which is received, is just sweeping signal U2D, and the second end is coupled to first node
ND1, and control end is then coupled to the first two grade of shift register output end Gn-2.7th switch T7 first end reception is counter to sweep signal
D2U, and the second end is coupled to first node ND1, and control end is coupled to rear two grades of shift register output end Gn+2.
Then when level shift registor SRn operation, (driving method refers to Fig. 3 step S110, S120 to explanation
And S130)：
It refer to Fig. 1, Fig. 2A, Fig. 3 and Fig. 4 A, Fig. 4 A and perform forward direction for the gate driving circuit 100 according to Fig. 1
The timing diagram during operation of scanning, and using shown in Fig. 2A when level shift registor SRn is illustrated as example.
When gate driving circuit 100 performs forward scan (as shown in Fig. 3 step S120), it is height just to sweep signal U2D
Level, the anti-signal D2U that sweeps is low levels；In addition, the first clock signal CK1, the second clock signal CK2, the 3rd clock signal CK3
And the 4th clock signal CK4 sequentially circulate unlatching, the first clock signal CK1 the second clock signal of phase-lead CK2 phase
Position, the second clock signal CK2 clock signal CK3 of phase-lead the 3rd phase, the 3rd clock signal CK3 phase-lead the
Four clock signal CK4 phase, the 4th clock signal CK4 the first clock signal of phase-lead CK1 phase, wherein in first
Among clock signal CK1, the second clock signal CK2, the 3rd clock signal CK3 and the 4th clock signal CK4, two it is adjacent when
The overlapping pulses of arteries and veins signal.
In the timing diagram of Fig. 4 A embodiment, output is produced when level shift register output end Gn is in period t3 and t4
Signal.When period t1 is originated, the first two grade of shift register output end Gn-2 is then changed to high level by low level, consequently, it is possible to
Fig. 2A's can then receive the first two grade of shift register output end Gn-2 high level letter as level shift registor SRn the 6th switch T6
Number, and make the 6th switch T6 conductings.Meanwhile, according to the high level for just sweeping signal U2D first node ND1 can be made to pass through the 6th switch
T6 is charged.Then, when period t3 is originated, first node ND1 has charged to the first level so that first switch T1 is
Conducting state.First switch T1 can then receive the first clock signal CK1 and send to as level shift register output end Gn, therefore work as level
Shift register output end Gn level will be changed to high level with the first clock signal CK1.That is, when level shift register is defeated
Go out to hold Gn to produce the first clock signal CK1 of correspondence when level shift register is exported, (figure is not to drive corresponding transistor
Show) and reach the purpose of scanning.When period t5 is originated, the first clock signal CK1 is changed to low level, therefore, when level displacement
Temporary output end Gn switches to low level with the first clock signal CK1.Now, the 3rd clock signal CK3 then changes paramount electricity
It is flat, and second switch T2 is turned on, also it can will be pulled down to low level as level shift register output end Gn.
In Fig. 4 A embodiment, first node ND1 to being held in high level between period t5, and continues in period t1
Turn on first switch T1.Therefore, as level shift register output end Gn when the output of level shift register is followed in the first clock pulse letter
Number CK1 is produced in period t1 to period t5 change.
At the end of period t5, the 4th clock signal CK4 is changed to high level from low level so that the 3rd switch T3 is to lead
Logical state, and just sweeping signal U2D also makes the 8th switch T8 be conducting state for high level.Consequently, it is possible to which Voltage stabilizing module 110 is then
The first discharge path P1 is formed, first node ND1 is discharged and low level is pulled down to, and then causes first switch T1 to close.
That is, the first discharge path P1 is by being all located at the 4th clock signal CK4 of high level and just sweeping signal U2D and the shape that is triggered
Into.Now, when level shift register output end Gn by second switch T2 conductings because being maintained low level.
By above-described embodiment, it can be realized that to for level shift registor SRn, first node ND1 is in period t1
To chargeable in high level between t5, and turn on first switch T1 so that when level shift register output end Gn substantially follows first
Clock signal CK1 is produced in period t1 to the level change between t5.In other words, the first clock signal CK1 works as to trigger
Level shift register output end Gn's works as the output of level shift register.Specifically, the first two grade of shift register output end Gn-2 and
The level shift register of working as that one clock signal CK1 works as level shift register output end Gn to trigger is exported.
Similarly, the shift registor of other grades also has corresponding signal intensity relation, also referring to Fig. 2 B, its
Illustrate the circuit diagram according to previous stage shift registor SRn-1 in an embodiment.As shown in Figure 2 B, previous stage shift register
What device SRn-1 framework was substantially similar to Fig. 2A works as level shift registor SRn, and difference is, previous stage shift registor
Clock signal (the first clock signal CK1, the second clock signal CK2, the 3rd clock signal corresponding to SRn-1 each switch
CK3 and the 4th clock signal CK4) with when level shift registor SRn it is different, in addition, adjacent front stage shift registor
Annexation also have corresponding change, previous stage shift registor SRn-1 is compared to being in when level shift registor SRn differences
It is described in detail in the following passage.
In the previous stage shift registor SRn-1 shown in Fig. 2 B, first switch T1 first end receives the 4th clock pulse letter
Number CK4, and the second end is coupled to previous stage shift register output end Gn-1.Second switch T2 first end is coupled to previous stage shifting
The temporary output end Gn-1 in position, and its control end receives the second clock signal CK2.In addition, Voltage stabilizing module 110 then receives the first clock pulse
Signal CK1, the 3rd clock signal CK3 and scanning sequence signal (just sweeping signal U2D and counter sweep signal D2U).In voltage stabilizing mould
In block 110, the 3rd switch T3 the second end is electrically coupled to the first two grade of shift register output end Gn-2, and control end then receives the 3rd
Clock signal CK3.4th switch T4 the second end is electrically coupled to as level shift register output end Gn, and control end receives first
Clock signal CK1.In two directions' inputing module 120, three-level shift register output end before the 6th switch T6 control end is coupled to
Gn-3, the 7th switch T7 control end is coupled to previous stage shift register output end Gn-1.In addition, previous stage shift registor
The annexations of wherein each switch elements of SRn-1 as shown in Figure 2 B, in Fig. 2A when level shift registor SRn is similar.It is previous
Being can refer in detail as flowing mode in preceding embodiment and Fig. 2A for level shift registor SRn-1 works as level shift registor SRn's
Complete explanation.
Refer to Fig. 2 B embodiment, first node ND1 is to chargeable in high level between t4, and to turn in period t0
First switch T1 so that previous stage shift register output end Gn-1 substantially follow the 4th clock signal CK4 period t0 to t4 it
Between level change and produce.In other words, the 4th clock signal CK4 is to trigger before previous stage shift register output end Gn-1
One-level shift register is exported.Specifically, preceding three-level shift register output end Gn-3 preceding three-level shift register output and the
Four clock signal CK4 are exported to trigger previous stage shift register output end Gn-1 previous stage shift register.
The rest may be inferred, and rear stage shift register output end Gn+1 substantially follows the second clock signal CK2 in period t2 to t6
Between level change and produce.Therefore, by above-mentioned Fig. 2 B and Fig. 2A previous stage shift registor SRn-1 being described in detail and
When level shift registor SRn can analogize the detailed connected mode for obtaining other per one-levels, therefore do not repeat separately herein.
Further, since it is that high level, the anti-signal D2U that sweeps are low level just to sweep signal U2D, therefore, in Voltage stabilizing module 110
In, the first discharge path P1 as formed by the 3rd switch T3 and the 8th switch T8 series connection will be turned on periodically, and the 9th
Second discharge path P2 formed by the switch T4 series connection of switch T9 and the 4th will be closed.In other words, in gate driving circuit 100
When performing forward scan, first node ND1 level change need not consider the influence that the second discharge path P2 is caused.
Further, it is ready for subsequently sweeping when level shift register is exported when level shift registor SRn completes to send out
When retouching, when level shift registor SRn first node ND1 level will be shifted according to the 4th clock signal CK4 and previous stage
Keep in output end Gn-1 level and periodically change.In the present embodiment, please refer to Fig. 2A and Fig. 4 A, pass through first
Switch T1 and produce the first clock signal CK1 as level shift registor output end Gn.However, the first clock signal CK1 is
The signal switched with periodic low and high level, therefore for the defeated of other shift registors at different levels for receiving the first clock signals
Interference can be formed by going out end and first node ND1.In detail, by taking Fig. 4 A as an example, the first clock signal CK1 is height in period t3~t4
Level, except correspondence n-th grade shift registor it is exportable work as level shift registor output end Gn in addition to, the first clock signal CK1
Also the shift registor of other grades is input into simultaneously, and then the shift registor of other grades is interfered.In the present embodiment
When just sweeping pattern, then the startup of mu balanced circuit 110 is controlled by the 3rd clock signal CK3, and the 3rd clock signal CK3 is neck
Prior to the first clock signal CK1, and then it is used as effect of voltage stabilizing in advance, reduction interference.
Similarly, when the present embodiment counter sweeps pattern, then mu balanced circuit 110 is controlled by the second clock signal CK2
Startup, and the second clock signal CK2 is leads over the first clock signal CK1, so as voltage stabilizing in advance, reduce the work(that disturbs
Effect.
Again please with reference to Fig. 4 B, Fig. 4 B perform the operation of reverse scan for the gate driving circuit 100 according to Fig. 1
When timing diagram, and using shown in Fig. 2A when level shift registor SRn is illustrated as example.
When gate driving circuit 100 performs reverse scan (as shown in Fig. 3 step S130), it is low just to sweep signal U2D
Level, the anti-signal D2U that sweeps is high level；In addition, the 4th clock signal CK4, the 3rd clock signal CK3, the second clock signal CK2
And first clock signal CK1 sequentially circulate unlatching, the 4th clock signal CK4 clock signal CK3 of phase-lead the 3rd phase
Position, the 3rd clock signal CK3 the second clock signal of phase-lead CK2 phase, the second clock signal CK2 phase-lead the
One clock signal CK1 phase, the first clock signal CK1 clock signal CK4 of phase-lead the 4th phase, wherein in the 4th
Among clock signal CK4, the 3rd clock signal CK3, the second clock signal CK2 and the first clock signal CK1 two it is adjacent when
The overlapping pulses of arteries and veins signal.
In the timing diagram of Fig. 4 B embodiment, produced when level shift register output end Gn is in period t3' and t4' defeated
Go out signal.When period t1' is originated, rear two grades of shift register output ends Gn+2 is then changed to high level, such one by low level
Come, Fig. 2A two grades of shift register output end Gn+2 height electricity after level shift registor SRn the 7th switch T7 can then be received
Ordinary mail number, and make the 7th switch T7 conductings.Meanwhile, first node ND1 is opened by the 7th according to the anti-high level for sweeping signal D2U
T7 is closed to be charged.Then, when period t3' is originated, first node ND1 has charged to the first level so that first switch
T1 is conducting state.First switch T1 can then receive the first clock signal CK1 and send to as level shift register output end Gn, therefore
When level shift register output end Gn level will be changed to high level with the first clock signal CK1.That is, when level displacement is temporary
Output end Gn is deposited to produce the first clock signal CK1 of correspondence when level shift register is exported, to drive corresponding transistor (figure
Do not show) and reach the purpose of scanning.When period t5' is originated, the first clock signal CK1 is changed to low level, therefore, when level is moved
The temporary output end Gn in position switches to low level with the first clock signal CK1.Now, the 3rd clock signal CK3 then changes paramount
Level, and second switch T2 is turned on, also it can will be pulled down to low level as level shift register output end Gn.
In Fig. 4 B embodiment, first node ND1 to being held in high level between period t5', and is held in period t1'
Continuous conducting first switch T1.Therefore, as level shift register output end Gn when the output of level shift register is followed in the first clock pulse
Signal CK1 is produced in period t1' to period t5' change.
At the end of period t5', the second clock signal CK2 is changed to high level from low level so that the 4th, which switchs T4, is
Conducting state, and it is counter sweep signal D2U also for high level make the 9th switch T9 be conducting state.Consequently, it is possible to Voltage stabilizing module 110
The second discharge path P2 is then formed, first node ND1 is discharged and low level is pulled down to, and then causes first switch T1 to close
Close.That is, the second discharge path P2 is by being all located at the second clock signal CK2 of high level and counter sweeping signal D2U and touched
Hair is formed.Now, when level shift register output end Gn by second switch T2 conductings because being maintained low level.
By above-described embodiment, it can be realized that to for level shift registor SRn, first node ND1 is in period t1'
To between t5' turn on first switch T1, therefore, when level shift register output end Gn substantially follow the first clock signal CK1 when
Section t1' is produced to the level change between t5'.
Similarly, the shift registor of other grades also has corresponding signal intensity relation；In addition, in raster data model electricity
When road 100 performs reverse scan, the second clock signal CK2 is similarly can be derived to trigger rear stage shift register output end Gn
+ 1 rear stage shift register output, rear two grades of shift register output ends Gn+2 rear two grades of shift registers output and this first
Clock signal CK1 deserves level shift register output Gn+2 to trigger.
Further, since it is that low level, the anti-signal D2U that sweeps are high level just to sweep signal U2D, therefore, in Voltage stabilizing module 110
In, the first discharge path P1 will be closed, and the second discharge path P2 will be turned on periodically.In other words, in raster data model
When circuit 100 performs reverse scan, first node ND1 level change need not consider the influence that the first discharge path P1 is caused.
Further, after completing to send out and exporting when level shift register and carry out follow up scan as level shift registor SRn,
When level shift registor SRn first node ND1 level will be defeated according to the second clock signal CK2 and rear stage shift register
Go out to hold Gn+1 level and periodically change.In the present embodiment when just sweeping pattern, then controlled by the 3rd clock signal CK3
The startup of mu balanced circuit 110 processed, and the 3rd clock signal CK3 is leads over the 4th clock signal CK4, and then as steady in advance
Pressure, the effect for reducing interference.Similarly, when the present embodiment counter sweeps pattern, then controlled by the first clock signal CK1 steady
The startup of volt circuit 110, and the first clock signal CK1 is leads over the 4th clock signal CK4, and then be used as voltage stabilizing in advance, subtract
The effect disturbed less.
Fig. 5 and Fig. 6 is referred to again.Fig. 5 is works as level shift registor in gate driving circuit 100 according to Fig. 1
Another implementation aspect circuit diagram, Fig. 6 is the sequential when level shift registor SRn' is in forward scan according to Fig. 5
Figure.
Shown in Fig. 5 when shown in level shift registor SRn' configuration and Fig. 1 when level shift registor SRn configuration is big
Cause is identical, and different part is when level shift registor SRn' further includes the 5th switch T5 and the 12nd switch T12.In Fig. 5's
In embodiment, the 5th switch T5 first end is coupled to first node ND1, and the second end receives the first system voltage Vss, control
End then receives reset signal RST.12nd switch T12 first end is coupled to as level shift register output end Gn, and the second end
The first system voltage Vss is received, control end then receives reset signal RST.
Further, collocation the first system voltage Vss and reset signal RST the 5th switch T5 is to provide when first
When arteries and veins signal CK1 just starts to produce, first node ND1 level is driven in low level.In detail, due to when the first clock signal
When CK1 just starts to produce, the 4th clock signal CK4 is not yet produced, therefore first node ND1 is not yet discharged, and will be to follow-up
Scanning interfere；Accordingly, it would be desirable to pass through the 5th switch T5 and reset signal RST collocation so that first node ND1 can quilt
Electric discharge.Consequently, it is possible to which first node ND1 level can be maintained at low level, and avoid interfering follow-up scanning, use
Reach effect of voltage stabilizing in advance.
Similarly, collocation the first system voltage Vss and reset signal RST the 12nd switch T12 is to provide when first
When clock signal CK1 just starts to produce, drive when level shift register output end Gn is when the level of level shift register output is in low
Level.In detail, in order to ensure when level shift register output end Gn is not by noise jamming, therefore the 12nd switch can be passed through
T12 and reset signal RST collocation, when level shift registor SRn' starts forward scan, even if proper level shift register
The output end Gn level for working as the output of level shift register is maintained at low level, to avoid working as level as level shift register output end Gn
There is noise in the level of shift register output, and disturb follow-up scanning.
In other words, collocation the first system voltage Vss and reset signal RST the 5th switch T5 and the 12nd switch T12 are used
First to remove first node ND1 and making an uproar as level shift register output end Gn when level shift registor SRn' starts scanning
Sound, to ensure that follow up scan is interference-free.
Refer to Fig. 7, its in gate driving circuit 100 according to Fig. 1 when the another reality of level shift registor
Apply the circuit diagram of aspect.Wherein, shown in Fig. 7 when shown in level shift registor SRn " configuration and Fig. 2A work as level shift register
Device SRn configuration is roughly the same, and different part is the configuration of Voltage stabilizing module internal circuit.
In Fig. 7 embodiment, when in level shift registor SRn " Voltage stabilizing module 110 ", the 8th switchs T8 control end coupling
The 4th clock signal CK4 is connected to, the 3rd switch T3 control end, which is coupled to, just sweeps signal U2D, the 9th switch T9 control end coupling
It is connected to the second clock signal CK2, the 4th switch T4 control end, which is coupled to, counter sweeps signal D2U.When level shift registor SRn's "
Operation principles and operation with shown in Fig. 2A when level shift registor SRn operation principles and operation are roughly the same,
Therefore be not repeated here.
Refer to Fig. 8, its in gate driving circuit 100 according to Fig. 1 when another reality of level shift registor
Apply the circuit diagram of aspect.Wherein, shown in Fig. 8 when shown in level shift registor SRn " ' configuration and Fig. 2A when level displacement is temporary
Storage SRn configuration is roughly the same, and different part is the configuration of Voltage stabilizing module internal circuit.
In Fig. 8 embodiment, when level shift registor SRn " ' Voltage stabilizing module 110 " ' include the 3rd switch T3, the 4th open
Close T4, the 8th switch T8, the 9th switch T9, the tenth switch T10 and the 11st switch T11.Specifically, the of the 3rd switch T3
One end is electrically coupled to first node ND1, and the second end is electrically coupled to previous stage shift register output end Gn-1, and control end is then
Receive the 4th clock signal CK4.4th switch T4 first end is electrically coupled to first node ND1, and the second end electric property coupling
To rear stage shift register output end Gn+1, and control end receives the second clock signal CK2.8th switch T8 is coupled to first segment
Between the switches of point ND1 and the 3rd T3 first end, and control end receives and is just sweeping signal U2D.In addition, the 9th switch T9 is coupled to the
Between the switches of one node ND1 and the 4th T4 first end.Tenth switch T10 first end and control end all receives second system electricity
VGH is pressed, and the second end is coupled to the 9th switch T9 control end.
When shown in level shift registor SRn " ' operation principles and process and Fig. 2A when level shift registor SRn fortune
Make principle and process is roughly the same, therefore be not repeated here.
In summary, gate driving circuit 100 is reached by the configuration mode of said elements with bidirectional operation function
And effect of voltage stabilizing in advance.
Certainly, the present invention can also have other various embodiments, ripe in the case of without departing substantially from spirit of the invention and its essence
Various corresponding changes and deformation, but these corresponding changes and change ought can be made according to the present invention by knowing those skilled in the art
Shape should all belong to the protection domain of appended claims of the invention.
Claims (13)
1. a kind of gate driving circuit, it is characterised in that include：
Stages shift buffer, can receive one first clock signal, one second clock signal, one the 3rd clock signal and one the 4th
Clock signal, it is central each self-contained per one-level shift registor：
One first switch a, first end of the first switch receives first clock signal, one second end coupling of the first switch
It is connected to one and works as level shift register output end, a control end of the first switch is coupled to a first node；
One Voltage stabilizing module, receives second clock signal, the 4th clock signal and scan order signal, the Voltage stabilizing module
The first node is coupled to, and the Voltage stabilizing module is believed according to the scanning sequence signal, second clock signal and the 4th clock pulse
Number, the first node is optionally conducted to a previous stage shift register output end or a rear stage shift register output end；
And
One two-way input module, receives the scanning sequence signal, and the two directions' inputing module couples are to the first node,
Wherein first clock signal, second clock signal and the 4th clock signal are respectively the different periodicity of phase
Clock signal.
2. gate driving circuit as claimed in claim 1, it is characterised in that each further included per one-level shift registor：
One second switch, a first end of the second switch, which is coupled to, deserves level shift register output end, the one of the second switch
Second end is electrically coupled to a first system voltage, and a control end of the second switch receives the 3rd clock signal, wherein should
First clock signal, second clock signal, the 3rd clock signal and the 4th clock signal are respectively that phase is different
Periodic clock signal.
3. gate driving circuit as claimed in claim 2, it is characterised in that the scanning sequence signal has one just to sweep letter respectively
Number with one it is counter sweep signal, and this is just sweeping signal when being high level, when first clock signal, the second clock signal, the 3rd
Arteries and veins signal and the 4th clock signal sequentially circulate unlatching, the phase-lead of first clock signal second clock signal
Phase, the phase of the clock signal of phase-lead the 3rd of second clock signal, the phase-lead of the 3rd clock signal should
The phase of 4th clock signal, the phase of the phase-lead of the 4th clock signal first clock signal, first clock pulse letter
Number, among second clock signal, the 3rd clock signal and the 4th clock signal two adjacent clock signals pulse
Partly overlap.
4. gate driving circuit as claimed in claim 2, it is characterised in that the scanning sequence signal has one just to sweep letter respectively
Number with one it is counter sweep signal, and this is anti-when to sweep signal be high level, the 4th clock signal, the 3rd clock signal, this second when
Arteries and veins signal and first clock signal sequentially circulate unlatching, the clock signal of phase-lead the 3rd of the 4th clock signal
Phase, the phase of the phase-lead of the 3rd clock signal second clock signal, the phase-lead of second clock signal should
The phase of first clock signal, the phase of the clock signal of phase-lead the 4th of first clock signal, the 4th clock pulse letter
Number, among the 3rd clock signal, second clock signal and first clock signal two adjacent clock signals pulse
Partly overlap.
5. a kind of gate driving circuit, it is characterised in that include：
Stages shift buffer, it is each self-contained per one-level shift registor：
One first switch a, first end of the first switch receives one first clock signal, one second end coupling of the first switch
It is connected to one and works as level shift register output end, a control end of the first switch is coupled to a first node；
One the 3rd switch a, first end of the 3rd switch is electrically coupled to the first node, one second end of the 3rd switch
A previous stage shift register output end is electrically coupled to, a control end of the 3rd switch is coupled to the 4th clock signal；
One the 4th switch a, first end of the 4th switch is electrically coupled to the first node, one second end of the 4th switch
A rear stage shift register output end is electrically coupled to, a control end of the 4th switch is coupled to second clock signal；With
And
One two-way input module, is coupled to first node.
6. gate driving circuit as claimed in claim 5, it is characterised in that further include：
One second switch a, first end of the second switch is coupled to the output end of the shift registor, the second switch
One second end receives a first system voltage, and a control end of the second switch receives one the 3rd clock signal.
7. gate driving circuit as claimed in claim 5, it is characterised in that this is each further included per one-level shift registor：
One the 5th switch a, first end of the 5th switch is coupled to the first node, and one second end of the 5th switch is received
One the first system voltage a, control end of the 5th switch receives a reset signal.
8. gate driving circuit as claimed in claim 5, it is characterised in that this is each further included per one-level shift registor：
One first electric capacity, a first end of first electric capacity, which is coupled to, deserves level shift register output end, the one of first electric capacity
Second end is coupled to the first node.
9. gate driving circuit as claimed in claim 5, it is characterised in that the scanning sequence signal has one just to sweep letter respectively
Number with one it is counter sweep signal, the two directions' inputing module is included：
One the 6th switch a, first end of the 6th switch receives this and is just sweeping signal, and one second end of the 6th switch is coupled to
The first node a, control end of the 6th switch is coupled to the first two a grade of shift register output end；And
One the 7th switch, a first end of the 7th switch receive this it is counter sweep signal, the 7th one second end switched is coupled to
The first node, two grades of shift register output ends after a control end of the 7th switch is coupled to one.
10. gate driving circuit as claimed in claim 5, it is characterised in that this is each further included per one-level shift registor：
One the 8th switch, the 8th switch is coupled between the first end of the first node and the 3rd switch；And
One the 9th switch, the 9th switch is coupled between the first end of the first node and the 4th switch；
Wherein the scanning sequence signal have one just sweeping signal with one it is counter sweep signal, the 8th control end switched is receiving this just
Sweep signal, a control end of the 9th switch receives this and counter sweeps signal.
11. gate driving circuit as claimed in claim 5, it is characterised in that this is each further included per one-level shift registor：
One the 8th switch, the 8th switch be coupled to the 3rd switch second end and the previous stage shift register output end it
Between；And
One the 9th switch, the 9th switch be coupled to the 4th switch second end and the rear stage shift register output end it
Between；
Wherein the scanning sequence signal have sweep signal with one it is counter sweep signal, the 8th control end switched receives this and just swept
Signal, and a control end of the 9th switch receives this and counter sweeps signal.
12. gate driving circuit as claimed in claim 5, it is characterised in that the scanning sequence signal has one just to sweep signal,
This is each further included per one-level shift registor：
One the 8th switch, the 8th switch is coupled between the first end of the first node and the 3rd switch, and the 8th opens
The control end closed receives this and just sweeps signal；
One the 9th switch, the 9th switch is coupled between the first end of the first node and the 4th switch；
The tenth switch, the first end and a control end of the tenth switch receive a second system voltage, the tenth switch
One second end is coupled to a control end of the 9th switch；And
The 11st switch a, first end of the 11st switch is coupled to the control end of the 9th switch, and the 11st opens
One second end closed receives a first system voltage, and a control end of the 11st switch receives this and just sweeps signal.
13. it is every among a kind of driving method, it is characterised in that for driving stages shift buffer, the stages shift buffer
One-level shift registor receives one first clock signal, one second clock signal, one the 3rd clock signal, one the 4th clock pulse respectively
Signal, one just sweeping signal and one it is counter sweep signal, the driving method is included：
When this is just sweeping signal for high level, when sequentially first clock signal, the second clock signal, the 3rd are opened in circulation
Arteries and veins signal and the 4th clock signal, wherein first clock signal, second clock signal, the 3rd clock signal and
The overlapping pulses of two adjacent clock signals among 4th clock signal, the 4th clock signal is previous to trigger one
Level shift register output, the first two a grade of shift register output and first clock signal are to trigger one when level shift register is defeated
Go out；And
When this is counter sweep signal for high level when, sequentially circulation open the 4th clock signal, the 3rd clock signal, this second when
Arteries and veins signal and first clock signal, wherein the 4th clock signal, the 3rd clock signal, second clock signal and
The overlapping pulses of two adjacent clock signals among first clock signal, second clock signal is latter to trigger one
Level shift register output, to deserve level shift register defeated to trigger for two grades of shift registers outputs and first clock signal after one
Go out.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW106121458A TWI622036B (en) | 2017-06-27 | 2017-06-27 | Gate driving circuit and driving method thereof |
| TW106121458 | 2017-06-27 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107274855A true CN107274855A (en) | 2017-10-20 |
| CN107274855B CN107274855B (en) | 2019-10-18 |
Family
ID=60076441
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710726273.8A Active CN107274855B (en) | 2017-06-27 | 2017-08-22 | Gate drive circuit and drive method thereof |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN107274855B (en) |
| TW (1) | TWI622036B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109345999A (en) * | 2018-05-28 | 2019-02-15 | 友达光电股份有限公司 | Gate driver circuit |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110738953B (en) * | 2018-07-20 | 2022-12-06 | 深超光电（深圳）有限公司 | Gate driver and display device having the same |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130169609A1 (en) * | 2011-12-30 | 2013-07-04 | Hydis Technologies Co., Ltd. | Shift Register and Gate Driving Circuit Using the Same |
| US20140159999A1 (en) * | 2012-12-07 | 2014-06-12 | Hefei Boe Optoelectronics Technology Co., Ltd. | Gate Driving Circuit, Switching Control Circuit and Shift Register of Display Device |
| US20140320386A1 (en) * | 2013-04-26 | 2014-10-30 | Chunghwa Picture Tubes, Ltd. | Display panel |
| US20150109353A1 (en) * | 2013-10-22 | 2015-04-23 | Hannstar Display Corporation | Liquid crystal display and bidirectional shift register device thereof |
| CN105280134A (en) * | 2015-07-02 | 2016-01-27 | 友达光电股份有限公司 | Shift register circuit and operation method thereof |
| CN106128392A (en) * | 2016-08-29 | 2016-11-16 | 武汉华星光电技术有限公司 | GOA drive circuit and embedded type touch control display floater |
| CN106782280A (en) * | 2016-12-30 | 2017-05-31 | 友达光电股份有限公司 | Shift register and grid drive circuit |
-
2017
- 2017-06-27 TW TW106121458A patent/TWI622036B/en active
- 2017-08-22 CN CN201710726273.8A patent/CN107274855B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20130169609A1 (en) * | 2011-12-30 | 2013-07-04 | Hydis Technologies Co., Ltd. | Shift Register and Gate Driving Circuit Using the Same |
| US20140159999A1 (en) * | 2012-12-07 | 2014-06-12 | Hefei Boe Optoelectronics Technology Co., Ltd. | Gate Driving Circuit, Switching Control Circuit and Shift Register of Display Device |
| US20140320386A1 (en) * | 2013-04-26 | 2014-10-30 | Chunghwa Picture Tubes, Ltd. | Display panel |
| US20150109353A1 (en) * | 2013-10-22 | 2015-04-23 | Hannstar Display Corporation | Liquid crystal display and bidirectional shift register device thereof |
| CN105280134A (en) * | 2015-07-02 | 2016-01-27 | 友达光电股份有限公司 | Shift register circuit and operation method thereof |
| CN106128392A (en) * | 2016-08-29 | 2016-11-16 | 武汉华星光电技术有限公司 | GOA drive circuit and embedded type touch control display floater |
| CN106782280A (en) * | 2016-12-30 | 2017-05-31 | 友达光电股份有限公司 | Shift register and grid drive circuit |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109345999A (en) * | 2018-05-28 | 2019-02-15 | 友达光电股份有限公司 | Gate driver circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| TWI622036B (en) | 2018-04-21 |
| TW201905879A (en) | 2019-02-01 |
| CN107274855B (en) | 2019-10-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104103244B (en) | Liquid-crystal display and bi-directional shift apparatus for temporary storage thereof | |
| CN106128403B (en) | Shift register cell, gate scanning circuit | |
| CN104050935B (en) | Shift register, bi-directional shift apparatus for temporary storage and apply its display panels | |
| CN104392686B (en) | Shift register unit, drive circuit, and display apparatus | |
| CN101996684B (en) | Shift register and touch controller | |
| CN104049796A (en) | Touch display screen and time-sharing drive method thereof | |
| CN106531112A (en) | Shifting register unit and driving method thereof, shifting register and display apparatus | |
| CN107134268B (en) | Shift register, gate driving circuit and driving method and liquid crystal display | |
| CN104575409A (en) | Liquid crystal display and bidirectional shift register thereof | |
| US10522065B2 (en) | Transmitting electrode scan driving unit, driving circuit, driving method and array substrate | |
| CN105957470B (en) | Shift register cell, gate driving circuit and its driving method, display device | |
| CN110969976A (en) | Display device driving method and display device | |
| CN108877624A (en) | special-shaped display panel and display device | |
| CN109994143B (en) | Shift register unit, grid driving circuit, display device and driving method | |
| CN106448536A (en) | Shifting register, grid driving circuit, display panel and driving method | |
| CN103413531A (en) | Shifting register unit, gate driving circuit and display device | |
| CN103956133B (en) | shift register circuit and shift register | |
| CN105702196A (en) | Grid electrode driving circuit and driving method thereof and display device | |
| TWI529731B (en) | Display panel and bi-directional shift register circuit | |
| CN103489391A (en) | Grid driving circuit, grid line driving method and displaying device | |
| CN104123905B (en) | Shift register and gate driver circuit | |
| CN107274855B (en) | Gate drive circuit and drive method thereof | |
| CN100538813C (en) | Circuit structure for dual resolution design reaches display panel and the electronic installation of using it | |
| CN113554970B (en) | GOA driving circuit, display panel and display device | |
| CN107967904A (en) | Scanning driving circuit, display panel and display device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |