CN107273602A

CN107273602A - A kind of emulation mode of lifting PCIE eye pattern allowances

Info

Publication number: CN107273602A
Application number: CN201710437205.XA
Authority: CN
Inventors: 李永翠
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2017-06-09
Filing date: 2017-06-09
Publication date: 2017-10-20

Abstract

The present invention relates to PCIE design fields, and in particular to a kind of emulation mode of lifting PCIE eye pattern allowances.The emulation mode sets (Pre cursor, Cursor, Post cursor) to set by adjusting TX ends, reduces TX Vswing, so as to reduce link crosstalk size, ensures the integrality of designed system link signal with this.The emulation mode avoids the space waste that brings of optimization link design, it is to avoid the increase of design time and cost, succinct efficiently easily realize.

Description

A kind of emulation mode of lifting PCIE eye pattern allowances

Technical field

The present invention relates to PCIE design fields, and in particular to a kind of emulation mode of lifting PCIE eye pattern allowances.The emulation Method sets (Pre-cursor, Cursor, Post-cursor) to set by adjusting TX ends, TX Vswing is reduced, so as to drop Low link crosstalk size, ensures the integrality of designed system link signal with this.The emulation mode avoids optimization chain The road design space waste that brings, it is to avoid the increase of design time and cost, it is succinct efficiently easily to realize.

Background technology

In server master board design, PCIE (peripheral component interconnect often occur A kind of high speed serialization computer expansion bus standards of express) cabling line length is shorter, and crosstalk is excessive, situations such as impedance discontinuity. Such case can cause signal because being influenceed by crosstalk and reflection, the integrality reduction of signal.

Shorter for bus cabling line length, crosstalk is excessive, situations such as impedance discontinuity, and designer can use up under normal circumstances Optimization design is measured, cabling space increase is avoided to crosstalk, line length avoids signal reflex too serious around long, but if increase is walked Space of lines and winding space, can cause the increase of plank size again, and in practical situations both, typically not enough spaces or Time carrys out optimization design.Therefore such case inevitably increases the time of design, increases design cost.

In view of the above-mentioned problems, a kind of emulation mode of lifting PCIE eye pattern allowances of the present application, by using emulation Method, reduces TX Vswing energy, to reduce link crosstalk size, to ensure link design signal integrity.

The content of the invention

The present invention sets (Pre-cursor, Cursor, Post- using by adjusting TX (Transmit transmitting terminals) ends Cursor) set, TX Vswing are reduced, so as to reduce link crosstalk size, it is ensured that system link model integrality.

The emulation mode of the present application realizes that step is as follows：

1), determine that PCIE bus links are short (below 5inch), crosstalk is than larger, the simulation result under normal TX Vswing Can not pass；

2), adjustment reduction TX Vswing, so as to reduce link crosstalk, find out the optimized parameter for meeting simulating decision result Arranges value；

3), by the parameter value feedback test, test checking is carried out.

By above step, you can eliminate link signal integrality risk.

Specifically, a kind of emulation mode of lifting PCIE eye pattern allowances is claimed in the application, it is characterised in that the emulation Method is specifically included：

It is short out and satisfaction, by adjusting parameter, can not be found by the PCIE buses of test under normal state simulation for chain The optimized parameter arranges value of simulating decision result；

By the parameter value feedback test, test checking is carried out, until passing through test.

The emulation mode of lifting PCIE eye pattern allowances as described above, is further characterized in that, chain is short out refer to 5inch with Under.

The emulation mode of lifting PCIE eye pattern allowances as described above, is further characterized in that, the adjustable parameter includes TX ends set (Pre-cursor, Cursor, Post-cursor) to set.

The emulation mode of lifting PCIE eye pattern allowances as described above, is further characterized in that, the adjustable parameter includes Adjust TX Vswing.

Embodiment

Emulation mode of the present invention is done below in conjunction with specific embodiment and is further described in detail：

By shorter to PCIE buses cabling on mainboard, the larger link of crosstalk carries out simulation analysis, the standard judged as Margin is greater than 9, and link signal integrality is only just can guarantee that more than 9.

Wherein, TX ends set (Pre-cursor, Cursor, Post-cursor) sum 0x3F (63), at this Under amplitude, even if preset0-9 is traveled through, eye pattern is (when eye pattern refers to that profit is experimentally estimated and improves systematic function It was observed that a kind of figure) margin unsatisfactory (High, low, right, left represent eye pattern margin), test result with Exemplified by (0x0b, 0x29,0x0b), concrete outcome is as shown in table 1.

Lane	Pre-cursor	Cursor	Post-cursor	High	Low	Right	Left	RxCtle
									0	0x0b	0x29	0x0b	12	-12	0	-13	8
1	0x0b	0x29	0x0b	11	-11	14	-14	8
									2	0x0b	0x29	0x0b	6	-8	11	-11	8
3	0x0b	0x29	0x0b	12	-12	15	-14	8
									4	0x0b	0x29	0x0b	12	-10	13	-13	8
5	0x0b	0x29	0x0b	12	-10	10	-14	8
									6	0x0b	0x29	0x0b	10	-6	2	-14	8
7	0x0b	0x29	0x0b	9	-10	14	-3	8

Before table 1 is improved (simulation result under normal TX Vswing)

Result for table 1 is adjusted.

Reduce TX ends and (Pre-cursor, Cursor, Post-cursor) sum 0x33 (51), reduction TX Vswing are set Energy, so as to reduce the influence of crosstalk, therefore, it is possible to obtain preferable simulation result, concrete outcome is as shown in table 2.

Due to that according to different links, several groups of parameter setting values can be tested more, optimal parameter setting is found, by the parameter Preserve offer test to use, for carrying out test checking.

After table 2 is improved (simulation result under reduction TX Vswing)

It is that the optimization to PCIE signal quality can be achieved according to above operating process, it is to avoid PCIE link signal integrality wind Danger.

It should be evident that only one embodiment of the present of invention shown in above-mentioned, for those of ordinary skill in the art For, on the premise of not paying creative work, other technical schemes can also be obtained according to above-described embodiment, are belonged to The scope of protection of the invention.

Emulation mode described herein, in the case where PCIE link cablings are short, crosstalk is larger, reflect seriously, can lead to Crossing adjustment TX ends sets (Pre-cursor, Cursor, Post-cursor) to set, and TX Vswing is reduced, so as to reduce link Crosstalk size, it is final to ensure system link signal integrity.

The space waste that optimization link design is brought is avoided by using the emulation mode of the present application, it is to avoid design Time and the increase of cost, obvious technical effects, are widely used in practice.

Claims

1. a kind of emulation mode of lifting PCIE eye pattern allowances, it is characterised in that the emulation mode is specifically included：

It is short out and can not find satisfaction emulation by the PCIE buses of test, by adjusting parameter under normal state simulation for chain The optimized parameter arranges value of result of determination；

2. the emulation mode of lifting PCIE eye pattern allowances, is further characterized in that, chain is short out to be referred to as claimed in claim 1 Below 5inch.

3. the emulation mode of lifting PCIE eye pattern allowances, is further characterized in that, the adjustable parameter as claimed in claim 2 (Pre-cursor, Cursor, Post-cursor) is set to set including TX ends.

4. the emulation mode of lifting PCIE eye pattern allowances, is further characterized in that, the adjustable parameter as claimed in claim 3 Including adjustment TX Vswing.