CN103995942A - Package pin area wiring method capable of reducing impedance abrupt change - Google Patents
Package pin area wiring method capable of reducing impedance abrupt change Download PDFInfo
- Publication number
- CN103995942A CN103995942A CN201410251991.0A CN201410251991A CN103995942A CN 103995942 A CN103995942 A CN 103995942A CN 201410251991 A CN201410251991 A CN 201410251991A CN 103995942 A CN103995942 A CN 103995942A
- Authority
- CN
- China
- Prior art keywords
- transmission line
- bga
- interconnected
- change
- routing method
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
The invention discloses a package pin area wiring method capable of reducing the impedance abrupt change. A width-variable wiring mode is adopted for an interconnected transmission line in the BGA area of a board card, wiring is conducted on the interconnected transmission line through a narrow transmission line in a BGA passing hole area, and wiring is conducted on the interconnected transmission line through a wide transmission line in other areas expect for the BGA passing hole area. Through the wiring method, the phenomenon that the distance between the interconnected transmission line and passing holes is too small when the interconnected transmission line passes through the BGA passing hole area can be avoided, the problem that the impedance abrupt change is caused due to the fact that the interconnected transmission line is too narrow can be solved, the impedance curve is more smooth, and the influences on information transmission quality are reduced.
Description
Technical field
The present invention relates to electronic applications, PCB LAYOUT design and emulation field, specifically a kind of packaging pin area routing method that reduces change in the instantaneous impedance.
Background technology
Along with the transmission speed of signal is more and more faster, SMI bus is up to 3.2Gbps, and following DDR4 more can be up to 4.2Gpbs.Be accompanied by the raising of signal rate, high speed signal has also proposed higher performance requirement to the various key elements on many plates transmission link.To the influence factor of signal integrity as change in the instantaneous impedance, crosstalk, conductor losses, spillage of material etc. require more strictly, need in each factor, accomplish optimum, for system reserves more surplus as far as possible.
Signal quality signal effectively in transmission shared position more and more important, for the principle of design of signal quality, be that the impedance that signal is experienced during through interconnection line should be identical.Any one section of interconnection line, regardless of line length and shape, no matter also the rise time of signal how, is all a transmission line consisting of signal path and return path.A signal, in each step of advancing along interconnection line, all can be experienced a transient impedance.If transient impedance is constant, just as transmission line has the xsect all having, its signal quality can obtain miraculous improvement.
The bus interconnecting between general chip chamber and plate, interlinked transfer line need to enter chip pin region, or interconnected for plate level, enters connector pinout region.Because chip pin region and connector pinout regional space are narrow and small, in order to guarantee production technology, and use the least possible wiring aspect, need to before entering this narrow zone, transmission line physical width be attenuated, can change transmission line impedance like this, bring the problem of change in the instantaneous impedance, this impact of effectively transmitting for high speed signal is huge.
Summary of the invention
The weak point existing for current technology, the present invention proposes a kind of packaging pin area routing method that reduces change in the instantaneous impedance.
A kind of packaging pin area routing method that reduces change in the instantaneous impedance of the present invention, the technical scheme that solves the problems of the technologies described above employing is as follows: this reduces the packaging pin area routing method of change in the instantaneous impedance, in the BGA region of board, interconnected transmission line adopts the wire laying mode of width conversion, in BGA via area, interconnected transmission line adopts narrower transmission line to connect up, between via hole, interconnected transmission line adopts narrower transmission line, other BGA regions outside BGA via area, interconnected transmission line adopts wider transmission line to connect up; In the time of can avoiding so interconnected transmission line through BGA via area and the too small phenomenon of via pitch, can reduce again, due to the narrow problem that causes change in the instantaneous impedance of interconnected transmission line, to make impedance curve more level and smooth, reduce the impact on transmission information quality.
The beneficial effect that a kind of packaging pin area routing method that reduces change in the instantaneous impedance of the present invention has:
The described packaging pin area routing method that reduces change in the instantaneous impedance, in the BGA region of board, interconnected transmission line adopts the wire laying mode of width conversion, in the time of can avoiding interconnected transmission line through BGA via area and the too small phenomenon of via pitch, can reduce again due to the narrow problem that causes change in the instantaneous impedance of interconnected transmission line, make impedance curve more level and smooth, reduced the impact on transmission information quality, to the effect of having greatly improved and directive significance in the problem of high-speed transmission line assurance signal transmission, there is good actual use value and the market competitiveness.
Accompanying drawing explanation
Accompanying drawing 1 is the bus topolopy schematic diagram of chip A to chip B;
Accompanying drawing 2 is the schematic diagram of 6Mil transmission line through BGA region;
Accompanying drawing 3 is the schematic diagram of 3.5Mil transmission line through BGA region;
Accompanying drawing 4 is the wire laying mode schematic diagram of transmission line width conversion;
Accompanying drawing 5 is the comparison diagram of 3.5Mil transmission line and two kinds of wire laying mode change in the instantaneous impedances of width conversion transmission line.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, hereinafter in connection with accompanying drawing, a kind of packaging pin area routing method that reduces change in the instantaneous impedance of the present invention is elaborated.
On the board of server system, on the path of interconnected transmission line, there are encapsulation welding tray, via hole, the change of transmission line physical arrangement etc. to affect the factor of transmission line impedance.In an interacted system, contain chip A and chip B, accompanying drawing 1 is the bus topolopy schematic diagram of chip A to chip B, as shown in Figure 1, to chip B, interconnected by the single-ended bus of high speed by chip A.Because BGA region layer-exchange hole-through gathers, use pad is 20Mil, boring is the via hole of 10Mil, via pitch is 11.5Mil, therefore interconnected transmission line needs special setting when through BGA via area, while passing between via hole, interconnected transmission line is arranged on the centre position between via hole, and interconnected transmission line can not adopt wider transmission line, otherwise wider transmission line is with interporal lacuna is too small excessively, so little transmission line has been pitch-row from not meeting existing processing technology, and transmission line is easily connected to via hole pin simultaneously increases product fraction defective; Interconnected transmission line can not adopt narrower transmission line, if adopt narrower transmission line, can guarantee the suitable spacing of ideal between transmission line and via hole, but the phenomenon that interconnected transmission line narrows down and there will be impedance to increase after entering BGA region like this, cause change in the instantaneous impedance problem, have a strong impact on signal transmission quality.
Under to the analysis of above-mentioned technical matters, the present invention proposes a kind of packaging pin area routing method that reduces change in the instantaneous impedance, in the BGA region of board, interconnected transmission line adopts the wire laying mode of width conversion, in BGA via area, interconnected transmission line adopts narrower transmission line to connect up, between via hole, interconnected transmission line adopts narrower transmission line, other BGA regions outside BGA via area, and interconnected transmission line adopts wider transmission line to connect up; In the time of can avoiding so interconnected transmission line through BGA via area and the too small phenomenon of via pitch, can reduce again, due to the narrow problem that causes change in the instantaneous impedance of interconnected transmission line, to make impedance curve more level and smooth, reduce the impact on transmission information quality.
Interconnection line impedance Control is 40 ohm, according to the stepped construction of design, uses material, and 40 ohm transmission line width should be 6Mil; Accompanying drawing 2 is the schematic diagram in 6Mil transmission line process BGA region, and as shown in Figure 2, but BGA region layer-exchange hole-through is densely covered, and use pad is 20Mil, holes as the via hole of 10Mil, and via pitch is 11.5Mil.The transmission line of width 6Mil is through this BGA via area, transmission line is 2.75Mil with crossing interporal lacuna, transmission line has been pitch-row from the little existing processing technology that do not meet like this, and transmission line is according to this kind of live width process BGA via area, easily be connected to via hole pin, can increase greatly product fraction defective, and then increase production cost.
By to 6Mil transmission line shown in accompanying drawing 2 through the analysis in BGA region, at the interconnected transmission line of BGA via area, need to adopt narrower transmission line; Accompanying drawing 3 is the schematic diagram of 3.5Mil transmission line through BGA region, as shown in Figure 3, use 3.5Mil width transmission lines, can meet the safe distance of transmission line and via pitch 4Mil, but this kind of method can increase impedance at transmission line narrow part, cause change in the instantaneous impedance problem, thereby greatly reduce the quality of signal transmission.
Accompanying drawing 4 is the wire laying mode schematic diagram of transmission line width conversion, as shown in Figure 4, the packaging pin area routing method that reduces change in the instantaneous impedance of the present invention, proposes to use 3.5Mil transmission line in BGA via area, uses the interconnected transmission line wire laying mode of 6Mil cabling outside via hole; In view of the analysis to transmission line wire laying mode shown in accompanying drawing 2 and accompanying drawing 3, in BGA region, use merely 3.5Mil cabling, impedance obviously increases, the method of the invention adopts and only changes transmission line in the mode of BGA via area live width, reduced change in the instantaneous impedance, make impedance curve more level and smooth, as shown in Figure 5.For the narrow zone such as connector, wiring also can adopt the method for the invention, and in high-speed transfer link, it is comparatively obvious that the method is improved effect to change in the instantaneous impedance and loss aspect.
Embodiment:
Below by an embodiment, to advantage and the design content that reduces the packaging pin area routing method of change in the instantaneous impedance of the present invention, be elaborated:
Described in this enforcement, reduce in the packaging pin area routing method of change in the instantaneous impedance, in blade server system, a board is designed with SMI bus, and bus path is through 0.8 millimeter of BGA; Interlinked transfer line enters BGA via area, changes transmission line live width, uses the wiring of 3.5Mil transmission line between via hole, and outside via hole, the wiring of 6Mil transmission line is used in region.The cabling mode of this variation of the present embodiment BGA region transmission line wiring width, reduce the impact that change in the instantaneous impedance brings, improved the signal quality of the SMI high-speed transmission line of 3.2Gbps, also guaranteed technological requirement, so packaging pin area routing method that reduces change in the instantaneous impedance of the present invention, to the effect of having greatly improved and directive significance in the problem of high-speed transmission line assurance signal transmission, there is the good market competitiveness and actual use value.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; suitable variation or replacement that person of an ordinary skill in the technical field any claims according to the invention and any does it, all should fall into scope of patent protection of the present invention.
Claims (3)
1. a packaging pin area routing method that reduces change in the instantaneous impedance, it is characterized in that, this reduces the packaging pin area routing method of change in the instantaneous impedance, in the BGA region of board, interconnected transmission line adopts the wire laying mode of width conversion, and in BGA via area, interconnected transmission line adopts narrower transmission line to connect up, and between via hole, interconnected transmission line adopts narrower transmission line, other BGA regions outside BGA via area, interconnected transmission line adopts wider transmission line to connect up.
2. a kind of packaging pin area routing method that reduces change in the instantaneous impedance according to claim 1, it is characterized in that, this reduces the packaging pin area routing method of change in the instantaneous impedance, in the BGA region of board, interconnected transmission line adopts the wire laying mode of width conversion, in BGA via area, use 3.5Mil transmission line, outside via hole, use the interconnected transmission line of 6Mil cabling to connect up.
3. a kind of packaging pin area routing method that reduces change in the instantaneous impedance according to claim 1, it is characterized in that, this reduces the packaging pin area routing method of change in the instantaneous impedance, in the BGA region of board, or in blade server system, one board is designed with SMI bus, bus path is through 0.8 millimeter of BGA, and interlinked transfer line enters BGA via area, changes transmission line live width, between via hole, use the wiring of 3.5Mil transmission line, outside via hole, use the wiring of 6Mil transmission line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410251991.0A CN103995942A (en) | 2014-06-10 | 2014-06-10 | Package pin area wiring method capable of reducing impedance abrupt change |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410251991.0A CN103995942A (en) | 2014-06-10 | 2014-06-10 | Package pin area wiring method capable of reducing impedance abrupt change |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103995942A true CN103995942A (en) | 2014-08-20 |
Family
ID=51310106
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410251991.0A Pending CN103995942A (en) | 2014-06-10 | 2014-06-10 | Package pin area wiring method capable of reducing impedance abrupt change |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103995942A (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105025668A (en) * | 2015-07-02 | 2015-11-04 | 浪潮电子信息产业股份有限公司 | Method for realizing impedance match of lines by adding through holes |
| CN105407627A (en) * | 2015-12-04 | 2016-03-16 | 广州兴森快捷电路科技有限公司 | High-speed printed circuit board and difference wiring method therefor |
| CN105760584A (en) * | 2016-02-01 | 2016-07-13 | 浪潮(北京)电子信息产业有限公司 | Internal wiring method and system for chip |
| CN111770637A (en) * | 2020-07-22 | 2020-10-13 | 浪潮电子信息产业股份有限公司 | Routing method, routing device and routing equipment for pins on PCB |
| CN113381244A (en) * | 2020-02-25 | 2021-09-10 | 杭州海康威视数字技术股份有限公司 | Net gape female terminal |
| CN113966080A (en) * | 2021-09-30 | 2022-01-21 | 苏州浪潮智能科技有限公司 | Crosstalk and routing impedance abrupt change identification method and related device |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2563885Y (en) * | 2002-05-21 | 2003-07-30 | 神达电脑股份有限公司 | Wiring improving structure for circuit board test wire |
| JP2006261492A (en) * | 2005-03-18 | 2006-09-28 | Toppan Printing Co Ltd | Circuit substrate |
| US20080230258A1 (en) * | 2007-03-23 | 2008-09-25 | Huawei Technologies Co., Ltd. | Printed circuit board, design method thereof and mainboard of terminal product |
-
2014
- 2014-06-10 CN CN201410251991.0A patent/CN103995942A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN2563885Y (en) * | 2002-05-21 | 2003-07-30 | 神达电脑股份有限公司 | Wiring improving structure for circuit board test wire |
| JP2006261492A (en) * | 2005-03-18 | 2006-09-28 | Toppan Printing Co Ltd | Circuit substrate |
| US20080230258A1 (en) * | 2007-03-23 | 2008-09-25 | Huawei Technologies Co., Ltd. | Printed circuit board, design method thereof and mainboard of terminal product |
Non-Patent Citations (1)
| Title |
|---|
| 电子发烧友网: "信号完整性：PCB走线宽度变化产生的反射", 《HTTP://WWW.ELECFANS.COM/ARTICLE/80/114/2012/20120515271669.HTML》 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105025668A (en) * | 2015-07-02 | 2015-11-04 | 浪潮电子信息产业股份有限公司 | Method for realizing impedance match of lines by adding through holes |
| CN105407627A (en) * | 2015-12-04 | 2016-03-16 | 广州兴森快捷电路科技有限公司 | High-speed printed circuit board and difference wiring method therefor |
| CN105407627B (en) * | 2015-12-04 | 2018-04-20 | 广州兴森快捷电路科技有限公司 | High-speed printed circuit board and its difference wiring method |
| US10433422B2 (en) | 2015-12-04 | 2019-10-01 | Guangzhou Fastprint Circuit Tech Co., Ltd. | High-speed printed circuit board and differential wiring method thereof |
| CN105760584A (en) * | 2016-02-01 | 2016-07-13 | 浪潮(北京)电子信息产业有限公司 | Internal wiring method and system for chip |
| CN113381244A (en) * | 2020-02-25 | 2021-09-10 | 杭州海康威视数字技术股份有限公司 | Net gape female terminal |
| CN111770637A (en) * | 2020-07-22 | 2020-10-13 | 浪潮电子信息产业股份有限公司 | Routing method, routing device and routing equipment for pins on PCB |
| CN113966080A (en) * | 2021-09-30 | 2022-01-21 | 苏州浪潮智能科技有限公司 | Crosstalk and routing impedance abrupt change identification method and related device |
| CN113966080B (en) * | 2021-09-30 | 2023-08-08 | 苏州浪潮智能科技有限公司 | Identification method for crosstalk and wiring impedance mutation and related device |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103995942A (en) | Package pin area wiring method capable of reducing impedance abrupt change | |
| WO2017092428A1 (en) | High-speed printed circuit board and difference wiring method therefor | |
| CN103970956A (en) | Design method for control transmission lines on same layer and with different impedance | |
| CN204335143U (en) | The pcb board structure of a kind of optimizing metal finger devices impedance | |
| US20140203417A1 (en) | Mitigation of far-end crosstalk induced by routing and out-of-plane interconnects | |
| US10897810B2 (en) | High speed signal fan-out method for BGA and printed circuit board using the same | |
| US20130114223A1 (en) | Semiconductor device | |
| US8898365B2 (en) | Micro-link high-bandwidth chip-to-chip bus | |
| US20160197051A1 (en) | Chip And Electronic Device | |
| CN104023474A (en) | Method for alleviating influence of impedance mutation on signal transmission line quality | |
| CN105323966A (en) | Design method for optimizing impedance continuity in interconnection of capacitors and differential through holes | |
| CN103987191A (en) | Method for reducing influence of AC coupling capacitor PAD on transmission of high-speed serial signals | |
| CN105447254B (en) | A kind of chip signal transmission control unit, system and method | |
| CN111741593A (en) | PCB and differential wiring impedance matching optimization structure thereof | |
| CN101048033A (en) | Printed circuit board | |
| CN211580287U (en) | Differential wiring structure of circuit board | |
| CN217116509U (en) | Via hole structure for optimizing multi-load DDRX daisy chain topology signal quality | |
| CN112770492A (en) | Design method and system of high-speed signal via hole and storage medium | |
| CN107690606A (en) | Head, capture apparatus and unmanned vehicle | |
| CN113435154B (en) | Chip and pin outgoing line design method thereof | |
| CN106446479A (en) | Wiring method giving consideration to production process capacity and signal quality | |
| CN205160910U (en) | High speed printing circuit board | |
| Chun et al. | Package and printed circuit board design of a 19.2 Gb/s data link for high-performance computing | |
| CN212163817U (en) | PCB structure for optimizing signal quality of T topology DDR module | |
| CN100518436C (en) | Cabling configuration for transmission line in high-speed printed circuit board |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20140820 |