JP2006261492A - Circuit substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a circuit substrate and a semiconductor device which enable an area array type package to be mounted at a low cost at high density while ensuring electrical characteristic and reliability, in a circuit substrate with a terminal formation surface 2 wherein a plurality of terminals are arranged and formed, and a circuit substrate and a semiconductor device whereon it is mounted. <P>SOLUTION: A region is provided, wherein a terminal is arranged and formed almost in an intersection of each line of a plane figure wherein a number of regular triangles are disposed and formed to bring each side into contact with each other. When an extended line of one side of a regular triangle is Y axis, a line vertical to it is X axis, and an intersection wherein a terminal in almost a center of a terminal formation surface is located is a center point of both axes, a terminal is disposed so that a distance is enlarged between adjacent terminals as it goes from the center point to an outer circumferential part of the terminal formation surface 2. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to mounting of a circuit board and a semiconductor device, for example, a package such as a BGA (Ball Grid Array) package, a CSP (Chip size Package), an LGA (Land Grid Array) package, or an area array terminal such as a flip chip. The present invention relates to a semiconductor chip having a plurality of contacts, a semiconductor chip having a plurality of non-contact terminals using an inductor or the like, and a circuit board on which these are mounted.

  In circuit boards and semiconductor devices mounted with area array type packages such as BGA, CSP, and LGA, terminals are generally arranged in a grid pattern at equal pitches on the circuit board or the like, or terminals are arranged every other terminal. Are arranged with repeated patterns.

Known documents are shown below.
JP, 2002-270723, A The patent application of a prior application is shown below. Japanese Patent Application No. 2005-045688

  Circuit boards and semiconductor devices are becoming increasingly narrow-pitch and multi-pin due to demands for miniaturization and high speed and high functionality. Therefore, the wiring is drawn from the central part of the mounting by increasing the wiring density of the circuit board and the semiconductor device and the board on which the circuit board is mounted, or by increasing the number of layers.

  As a result, the resistance value is increased by reducing the wiring width, and there are problems that a sufficient voltage cannot be supplied to the semiconductor device and disconnection due to thermal stress is likely to occur. In addition, problems such as an increase in manufacturing cost have occurred due to multilayering, an increase in the number of manufacturing steps of fine wiring, and a decrease in manufacturing yield.

  An object of the present invention is to provide a circuit board and a semiconductor device capable of mounting an area array type package at a low cost and a high density while ensuring electrical characteristics and reliability, and a circuit board and a semiconductor device on which the circuit board and the semiconductor device are mounted. .

  The present invention has been made in view of the above problems, and the invention according to claim 1 is a circuit board having a terminal forming surface on which a plurality of terminals are arranged and formed, and each side contacts a large number of equilateral triangles. Thus, the circuit board is characterized in that the terminals are substantially arranged and formed at the intersections of the lines of the plane figure arranged and formed as described above.

  In the invention of claim 2, the extension line of one side of the equilateral triangle is the Y axis, the line perpendicular to the X axis is the X axis, and the intersection where the terminal at the approximate center of the terminal forming surface is located is the center point of both axes. 2. The circuit board according to claim 1, wherein a region in which the terminals are arranged is provided so that a distance between adjacent terminals increases from the center point toward the outer peripheral portion of the terminal forming surface. Is.

According to a third aspect of the present invention, when the terminal forming surface has a quadrangular shape and each side thereof is substantially parallel to the X-axis and Y-axis, the region includes a side parallel to the Y-axis and the side of the side. An area formed by a line connecting both ends and the center point, and the distance between adjacent terminals in the direction parallel to the Y axis gradually increases from the end of the side parallel to the Y axis toward the center of the side. The circuit board according to claim 2, wherein:

  According to a fourth aspect of the present invention, the terminal forming surface has a polygonal shape, at least one side thereof is substantially parallel to a side of the equilateral triangle, and the region is a side substantially parallel to the side of the equilateral triangle, An area formed by a line connecting both ends of the side and the center point, and the distance between adjacent terminals in a direction parallel to the substantially parallel side is gradually increased from the end of the substantially parallel side toward the center of the side. The circuit board according to claim 2, wherein the circuit board is widened.

  Further, the invention of claim 5 is an area formed by a side parallel to the X-axis and a line connecting both ends of the side and the center point. Terminals are arranged so that the distance between them is wide, and the distance between adjacent terminals in the direction parallel to the X axis gradually increases from the end of the side parallel to the X axis toward the center of the side. A circuit board according to claim 3 is provided.

  According to a sixth aspect of the present invention, the terminal forming surface has a polygonal shape, and at least one side thereof is substantially perpendicular to the side of the equilateral triangle, the side substantially perpendicular to the side of the equilateral triangle, both ends and the center of the side. In the area formed by the line connecting the points, the terminals are arranged so that the distance between the adjacent terminals becomes wider from the center point toward the outer periphery of the terminal forming surface, and adjacent in the direction parallel to the substantially vertical side. 5. The circuit board according to claim 4, wherein the distance between the terminals gradually increases from an end portion of the substantially vertical side toward the center of the side.

  According to a seventh aspect of the present invention, the terminal forming surface is polygonal, and the region is a region formed by a polygonal side and a line connecting the both ends of the side and the center point. The circuit board according to claim 2, wherein the distance between adjacent terminals in a direction parallel to is gradually increased from the end of the side toward the center of the side.

  All circuit boards of the present invention include semiconductor devices and semiconductor packages.

  In the circuit board according to the present invention, a plurality of terminals of the circuit board are arranged substantially at the intersections of the lines of the plane figure formed so that each side is in contact with a number of equilateral triangles, and in the same direction with respect to the reference point The terminals located farther away from the reference point for the terminals located at a wider distance between the terminals adjacent to the terminals can be mounted at a high density without increasing the number of layers of the mounting board without reducing the wiring width. The circuit board can be made possible.

  Embodiments of the present invention will be specifically described below with reference to the drawings.

Fig.1 (a) is the partial explanatory view which looked at the terminal formation surface of an example of the circuit board of this invention in the plane. On the terminal formation surface, the terminals are substantially arranged at the intersections of the lines of the plane figure arranged so that each side is in contact with many regular triangles. However, the outermost triangle has a non-contact portion. The extension line of one side of the equilateral triangle is the Y axis, the line perpendicular to the X axis is the X axis, and the intersection of both axes is the position of one terminal. Such an arrangement of terminals has a structure in which a basic lattice and a cell are repeated as shown in FIG. In FIG. 5B, the horizontal axis represents the X-axis, the vertical axis represents the Y-axis, the intersection is the reference terminal position t0, the X-axis adjacent terminal position t1 of this terminal, the Y-axis adjacent terminal positions t2, t0. The position t3 of the nearest terminal is shown. t0-t1 and t0-t2 are repeated as vertical and horizontal basic lattices to form spatial lattices. If terminals are placed at the positions t0 and t3, respectively, and a cell is arranged in each spatial grid, all terminals can be arranged as shown in FIG. Note that t0, t1, t2, and t3 are vector quantities here. If the shortest distance between terminals is s = t3-t0 (vector length), the area of the basic lattice is (((√3) / 2) × s × 2) × s = (√3) s ^2. . Therefore, the number of terminals per unit area is 2 / ((√3) s ² ). On the other hand, when the terminals are placed evenly in the vertical and horizontal directions with the shortest distance s between the terminals as in the prior art (equal pitch lattice arrangement), the ratio is such that one terminal is placed in a square of length s as shown in FIG. Therefore, the number of terminals per unit area is 1 / s ² . Therefore, the density of the terminal of the present invention is ((2 / ((√3) s ² )) / (1 / s ² ) = 2 / (√3), which is about 1.15 times that of the prior art. This wiring board is mounted with high density.

  Next, wiring from the terminals will be described. Here, the wiring from the end of the X axis row is wide between the terminals, and it is usually possible to lead out from the terminal row of about 3 rows inside the end of the X axis to the outside of the terminal forming surface. Internal terminals are then connected to the inner layer of the wiring board via vias and wired to the outside. However, for wiring from the end of the Y-axis row, since the distance between adjacent terminals is short, it is usually possible to lead out to the outside of the terminal formation surface only from the Y-axis end to one inner row. For this reason, in the wiring board of the present application, the extended line of one side of the equilateral triangle is the Y axis, the line perpendicular to the X axis is the X axis, and the intersection point where the terminal is located at the approximate center of the terminal forming surface is the center point of both axes. In some cases, the region where the terminals are arranged is provided so that the distance between the adjacent terminals becomes wider from the center point toward the outer peripheral portion of the terminal formation surface. That is, the Y-axis end row in FIG. 1A is slightly shifted toward the X-axis toward the outside of the terminal formation surface, or the distance between the terminals of the Y-axis row is increased in the Y-axis direction. The wiring is drawn out from the terminals on the inner side of the shaft end to the outside.

  When the distance between terminals in the direction parallel to the Y axis is increased, the distance between adjacent terminals in the direction parallel to the Y axis is preferably gradually increased from the end of the side parallel to the Y axis toward the center of the side. . This is because in the side parallel to the Y axis, the number of wires to be drawn out is larger at the center of the side than at the end.

  In addition, the plane figure formed so that each edge | side may contact many regular triangles based on this application is hereafter called a hexagonal lattice arrangement | sequence.

  The above example of the present invention will be specifically described with reference to the drawings. FIG. 6 is a schematic explanatory view showing a mounting example of the wiring board of the present invention in cross section. The CSP 1 is mounted via the BGA balls 22 in the form of a ball grid array on the wiring board PCB3 on which the ball pads are formed. A semiconductor chip 21 is connected to the CSP 1 by balls. The arrangement of the ball pads of the CSP 1 on the PCB 3 is as shown in the arrangement plane 2 in which the terminals shown in FIG. As a typical value at present, the effective pad arrangement surface of CSP1 is 13 mm × 13 mm, and the mountable pad pitch of the eutectic solder ball having a diameter of 500 μm (distance from the pad center. (S) above) is 1 mm. To do.

  In the case of a regular ball grid array with an equal pitch grid, the maximum grid size is 169 pins of 13 × 13, but this CSP1, which is a hexagonal grid array, enables a high density arrangement of 187 pins. The line / space of the PCB 3 can be designed as a typical value of 100 μm / 100 μm. Also, if the pad diameter is 600 μm, the wiring that can pass 400 μm of the pad-to-pad space 16 is 1 in the conventional uniform pitch arrangement. It is a book.

  FIG. 2 is an explanatory view of a PCB wiring routing portion of a general ball grid array pad of an equal pitch grid arrangement. From the above, in the conventional general ball grid array shown in the drawing, the outermost pad row 40 and the ball pad row 50 inside one row can be wired in the first layer through the pads, but the inner pad row 80 is further arranged. In order to draw the wiring from the PCB, it is necessary to provide two or more wiring layers on the PCB 3.

FIG. 3 is a partial explanatory view showing the vicinity of the end of the arrangement in the X-axis direction shown in FIG. As shown in the figure, the CSP 3 includes a pad-to-pad space 17 (2 × ((()) from the outermost pad row 4, the ball pad row 5 inside one row, and the ball pad row 8 further inside one row in FIG. √3) / 2) × 1000−600 = about 1132 [μm]), and can be extracted by the extraction wiring 10.

  FIG. 4 is a partial explanatory view showing the vicinity of the end of the arrangement in the Y-axis direction shown in FIG. As shown in the figure, since the space 18 of the outermost pad row 6 in FIG. 1A is 400 μm, only the outermost pad row 6 and the pad row 7 inside the first row can be drawn out in one layer, and the inner side of the two rows The pad row 9 can only be pulled out by another layer.

  FIG. 5 is a partial explanatory view of a terminal forming surface of another example of the circuit board of the present invention as seen in a plane. In the figure, as the pad arrangement according to the present invention, the outermost pad row of CSP1 and PCB3 is modified from the position 6 of the hexagonal lattice row to form the outermost pad row 16 to be a substantially hexagonal lattice row. Drawer wiring. The center position of the pad arrangement surface is the reference point 11, and reference lines 12 to 15 are taken in the four diagonal directions starting from the reference point 11. The distance 19 from the reference point 11 to the inner pad row 7 is (√3 / 2) × 6 = 5.196 [mm], and the distance 20 from the pad row 7 to the outermost pad row 16 modified is represented by Take 1 mm. Furthermore, when the pad pitch belonging to the outermost pad row 16 between the reference line 12 and the reference line 15 is set to the value shown in FIG. 5, the pad row 7 and the pad row 9 can also be drawn out in the first layer. With this modification, the number of pads in the outermost pad row is reduced by one. Therefore, even if the same modification is performed on the outermost pad row surrounded by the reference line 13 and the reference line 14 on the opposite side, a full grid is obtained. It is possible to draw all 185 pins in two wiring layers.

This is described below.
As described above, the line / space of the PCB 3 can be designed as 100 μm / 100 μm as a typical value. Since the line width is 100 μm, the land diameter is estimated to be 200 μm. Compared to a pad diameter of 600 μm, the space between lands with a pitch of 1 mm is 800 μm.

  Hereinafter, it will be shown that all the wiring of the pad between the reference line 12 and the reference line 15 can be drawn from the two layers of the end PCB3. The length of the line in the fourth column from the reference point where the lead wiring remains is approximately 6.9 mm because the reference line passes through the corner of the arrangement surface. Among these, since there are seven lands located on this line, the length occupied by the lands is 200 × 7 = 1.4 mm, and 5.5 mm is a space that can be wired.

  On the other hand, the number of pins included in the region between the reference line 12 and the reference line 15 is 19 at most. In order to wire 19 lines with a line / space of 100 μm / 100 μm, a width of 2.0 mm is required, and even if the space between 7 lands and a line is taken into consideration, 3.0 mm is sufficient. 5.5 mm sufficiently fills the required space of 3.0 mm. Accordingly, the pad wiring included in the region between the reference line 12 and the reference line 15 can be wired in the second layer.

  In this example, because the lead-out wiring is in the Y-axis direction, only the pad arrangement in the end row of the Y row is adjusted, but this is not particular. That is, the pad arrangement may be adjusted for a plurality of Y rows from the end. In this case, the number of pads is further reduced, but the number of wirings that can be drawn on the PCB surface layer can be increased.

  In addition, although the case where the CSP is mounted on the PCB has been described, the pad arrangement when mounting the normal BGA package on the motherboard and the bump arrangement when flip-chip mounting the semiconductor chip on the interposer are only different in scale. The same effect can be obtained by the invention.

  Further, the present invention does not need to be a square or a square terminal arrangement area, and can be applied to any substantially circular shape including an asymmetric polygon, an arbitrary polygon, and the like.

  In this case, it is assumed that at least one of the terminal forming surfaces surrounded by the polygonal sides is substantially parallel to the side of the regular triangle. Then, as the distance from the adjacent terminal to the outer peripheral portion of the terminal forming surface from the center point is increased, the region where the terminals are arranged is a side substantially parallel to the equilateral triangle, both ends of the side, and the center point. An area formed by a line connecting the two. Further, the distance between adjacent terminals in the direction parallel to the substantially parallel side is gradually increased from the end of the substantially parallel side toward the center of the side. This is for the same reason as described above.

  A circuit board on which such a polygonal terminal forming surface is formed has a good effect in a high-frequency transmission circuit as described in Patent Document 2, for example. As an example of the circuit board of the present invention, a regular hexagonal terminal forming surface is used, and the circuit board has a regular hexagonal shape composed of sides parallel to the sides of the regular hexagon. This is mounted on another board. FIG. 7 is an explanatory view of the mounted board as viewed in plan. In this case, a plurality of circuit boards 30 of the present application are created, arranged on the board 31 so that each side is equidistant, and signal lines 32 are wired. By doing so, each signal line 32 can be wired with the same length, and there is little skew (temporal deviation between signals), and signals can be transmitted simultaneously. The circuit board 30 of this example is a circuit board particularly suitable for a high-frequency transmission circuit. In this example, the sides other than the signals to be equally wired do not need to be on a regular hexagonal line. Therefore, the circuit board of this example may be a polygon including a regular hexagon.

  In order to increase the number of lead wires from the terminal row to the outside of the terminal formation surface, in the above example, the distance between the terminals is increased in the portion where the terminal interval is narrow, and the lead wires are increased. However, this also has the effect of increasing the number of lead lines even if the distance between the terminals is increased in the same manner in the portion where the terminal interval is wide, for example, in the X-axis direction of FIG.

  That is, when the terminal formation surface is a quadrangle and each side is substantially parallel to the X axis and the Y axis, the terminal formation surface is formed by a line connecting the side parallel to the X axis and both ends of the side and the center point. The terminal may be arranged so that the distance between the adjacent terminals becomes wider from the center point toward the outer periphery of the terminal formation surface.

  Furthermore, the distance between adjacent terminals in the direction parallel to the X axis may be gradually increased from the end of the side parallel to the X axis toward the center of the side.

  In addition, when the terminal forming surface is polygonal and at least one side thereof is substantially perpendicular to the side of the regular triangle, a line connecting the side substantially perpendicular to the side of the regular triangle and both ends of the side and the center point The terminal may be arranged so that the distance between the adjacent terminals becomes wider from the center point toward the outer periphery of the terminal formation surface.

  Furthermore, the distance between adjacent terminals in the direction parallel to the substantially vertical side may be gradually increased from the end of the substantially vertical side toward the center of the side.

  From the above, in order to increase the number of lead wires from the terminal row to the outside of the terminal formation surface, since the terminal formation surface is polygonal, the lead wire is extended by widening the distance between the terminals in such a narrow terminal interval. Increasing the number can provide the same effect that the number of leader lines can be increased by the above-mentioned means regardless of whether the side is parallel to or perpendicular to the regular triangle or inclined at an arbitrary angle.

FIG. 1A is a partial explanatory view of a terminal forming surface of an example of a circuit board of the present invention as viewed in plan, FIG. 2B is an explanatory view of a basic lattice and a cell of this example, and FIG. It is explanatory drawing of a basic lattice and a cell at the time of arrange | positioning vertically and horizontally equally with the shortest distance s. It is a partial explanatory view of a PCB wiring routing portion of a general equi-pitch grid array ball grid array pad. It is a partial explanatory view showing the vicinity of the end of the arrangement in the X-axis direction shown in FIG. It is a partial explanatory view showing the vicinity of the end of the arrangement in the Y-axis direction shown in FIG. It is the partial explanatory view which looked at the terminal formation surface of the other example of the circuit board of the present invention in the plane. It is the model explanatory view which showed the example of the wiring board of this invention in the cross section. It is explanatory drawing which looked at the board | substrate which mounted the example of the wiring board of this invention in the plane.

Explanation of symbols

1 ... CSP
2 ... Terminal (ball pad) placement surface 3 ... PCB
4 ... outermost pad row 40 ... outermost pad row 5 ... one inner pad row 50 ... one inner pad row 6 ... outermost pad row 7 ... one Inner pad row 8 ... Two inner pad rows 80 ... Two inner pad rows 9 ... Two inner pad rows 10 ... Lead wiring 11 ... Reference point 12 ... Reference line 13... Reference line 14... Reference line 15... Reference line 16... Inter-pad space 17 at the time of general equi-pitch grid arrangement. Space 18 of outermost pad row 4 of array pad ... Space 19 of outermost pad row 6 of ball grid array pad of Y axis row of hexagonal lattice arrangement ... Ball grid array pad of substantially hexagonal lattice arrangement from reference point The distance 20 from the outermost one to the innermost row is approximately hexagonal lattice array Lumpur grid distance outermost row 16 of the array pad until one inner row 7 21 ... semiconductor chip 22 ... BGA balls 30 ... circuit board 31 ... substrate 32 ... signal line 32

Claims (7)

  In a circuit board having a terminal formation surface on which a plurality of terminals are arranged and formed, the terminals are substantially arranged and formed at the intersections of each line of a plane figure arranged and formed so that each side touches a number of equilateral triangles. Feature circuit board.   When the extension line of one side of the equilateral triangle is the Y axis, the line perpendicular to it is the X axis, and the intersection point where the terminal at the approximate center of the terminal formation surface is the center point of both axes, the terminal formation surface from the center point 2. The circuit board according to claim 1, wherein a region in which the terminals are arranged is provided so that a distance between adjacent terminals increases as going to the outer peripheral portion of the circuit board.   When the terminal formation surface is a quadrangular shape and each side thereof is substantially parallel to the X axis and the Y axis, the region is a line connecting the side parallel to the Y axis and both ends of the side and the center point. The distance between adjacent terminals in the direction formed in the direction parallel to the Y axis gradually increases from the end of the side parallel to the Y axis toward the center of the side. Circuit board.   The terminal forming surface has a polygonal shape, and at least one side thereof is substantially parallel to the side of the equilateral triangle, and the region connects the side that is substantially parallel to the side of the equilateral triangle, and both ends of the side and the center point. The distance between adjacent terminals in a direction parallel to a substantially parallel side, which is an area formed by lines, gradually increases from the end of the substantially parallel side toward the center of the side. 2. The circuit board according to 2.   A terminal formed so that the distance between adjacent terminals increases as it goes from the center point to the outer periphery of the terminal forming surface in a region formed by a line connecting the side parallel to the X axis and both ends of the side and the center point. 4. The circuit board according to claim 3, wherein a distance between adjacent terminals in a direction parallel to the X axis gradually increases from an end of a side parallel to the X axis toward the center of the side.   The terminal forming surface is polygonal, and at least one side thereof is substantially perpendicular to the side of the equilateral triangle, and is formed by a side that is substantially perpendicular to the side of the equilateral triangle, and a line connecting both ends of the side and the center point. In the region, the terminals are arranged so that the distance between the adjacent terminals becomes wider from the center point toward the outer periphery of the terminal forming surface, and the distance between the adjacent terminals in the direction parallel to the substantially vertical side is substantially vertical. The circuit board according to claim 4, wherein the circuit board gradually widens from the end of the side toward the center of the side.   The terminal forming surface is polygonal, and the region is a region formed by a line connecting a polygon side and both ends of the side and the center point, and the distance between adjacent terminals in the direction parallel to the side is The circuit board according to claim 2, wherein the circuit board gradually widens from the end of the side toward the center of the side.