CN103970956A - Design method for control transmission lines on same layer and with different impedance - Google Patents
Design method for control transmission lines on same layer and with different impedance Download PDFInfo
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- CN103970956A CN103970956A CN201410210573.7A CN201410210573A CN103970956A CN 103970956 A CN103970956 A CN 103970956A CN 201410210573 A CN201410210573 A CN 201410210573A CN 103970956 A CN103970956 A CN 103970956A
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Abstract
The invention discloses a design method for control transmission lines on the same layer and with different impedance. According to different Plane layers arranged on the control transmission lines with different impedance on a calculation mainboard of a server together, different design is performed on the line width and the line distance of the control transmission lines, and optimization design is performed on the high-impedance transmission lines on the premise that optimality of the low-impedance transmission lines is guaranteed; according to the optimization design, a reference plane below the high-impedance transmission lines is hollowed, so that the high-impedance transmission lines refer to a second plane below the high-impedance transmission lines, and the distance between the high-impedance transmission lines and the reference plane is increased. By means of the design method of the transmission lines, the requirement of impedance is met to guarantee impedance continuity of signals, loss of conductors is reduced, and signal integrity is optimized.
Description
Technical field
The present invention relates to electronic applications, specifically a kind of method for designing with the different impedance Control transmission line of layer.
Background technology
Along with the transmission speed of signal is more and more faster, PCIE3.0 is up to 8Gpbs, and FDR bus is especially up to 14Gbps, following can be to 25Gbps development, signal integrity signal effectively in transmission shared position more and more important.In passage Networking Design, the control of transmission line loss is the main points of design.And transmission line loss comprises two parts, conductor losses and dielectric loss.Dielectric loss is relevant with sheet material, and conductor losses is relevant with the width and thickness in transmission line cross section.Wide and thick conductive wire cross-section is better than thin and narrow cross-sectional area of conductor, is conducive to reduce the impact of skin effect on conductor losses.Various key elements on the interconnected transmission link of the many plates of high speed serialization Difference signal pair have proposed higher performance requirement.The influence factor of signal integrity, as change in the instantaneous impedance, is crosstalked, conductor losses, spillages of material etc. require more strict, need in each factor, accomplish optimum, for system reserves more surplus as far as possible.
The universal serial bus interconnecting between the chip chambers such as general PCIE, SATA, SAS, QDR, FDR and plate, is distributed in same plate, and impedance Control has 100 ohm, 85 ohm.When design high speed signal, for making high speed signal effectively transmission in PCB, pcb board must be designed to the controlled veneer of impedance.With in computer main board design very common 85 ohm, 100 ohm are present in the same aspect of same veneer is simultaneously example, and both impedance contrasts are apart from larger, the more difficult realization of impedance Control.Conventional impedance design, if ensure that 85 ohm transmission line impedance are controlled, live width devise optimum, can cause 100 ohm transmission line live widths narrower, and narrower live width, along with signal rate raises, electric current concentrates on conductive surface, causes conductor losses problem.Such distribution of impedance is in same aspect, and impedance design just becomes more difficult thing.If ensure the impedance design of 85 ohm, must affect the signal integrity of 100 ohm transmission line.How accomplish to have controlled impedance same in stacked, ensured that again the signal integrity of transmission line becomes good problem to study.
Summary of the invention
For above-mentioned technical matters, should meet impedance to ensure the impedance continuity of signal, reduce again conductor losses and optimize the problems such as signal integrity, the present invention proposes a kind of method for designing with the different impedance Control transmission line of layer.
Method for designing with the different impedance Control transmission line of layer of the present invention, the technical scheme that solves the problems of the technologies described above employing is as follows: the method for designing of this transmission line, based on meeting impedance to ensure the impedance continuity of signal, reduce again conductor losses and optimize the requirement of signal integrity, according to the difference of calculating the Plane layer that on mainboard, different impedance Control transmission lines arrange jointly at server, live width, the line-spacing of controlling transmission line are carried out to different designs, ensureing, under the prerequisite of Low ESR transmission line design optimum, to carry out the optimal design of high-impedance transmission line; The optimal design of described high-impedance transmission line comprises: artificially increase high-impedance transmission line and the distance of calculating reference planes in mainboard, reference planes by high-impedance transmission line below hollow out, make high-impedance transmission line with reference to its below second layer plane, widen the distance of high-impedance transmission line and reference planes.
The beneficial effect having with the method for designing of the different impedance Control transmission line of layer of the present invention: by the method for designing of the bright described transmission line of we, can realize the optimal design connecting up with the transmission line of the different impedance of layer in calculating mainboard, meet the impedance requirement of different transmission lines, ensure the impedance continuity of signal, reduce conductor losses simultaneously, optimized the integrality of signal.
Brief description of the drawings
Accompanying drawing 1 is stepped construction schematic diagram in embodiment 1;
Accompanying drawing 2 is that in the method, 85 ohmages are calculated schematic diagram;
Accompanying drawing 3 is that in the method, 100 ohmages are calculated schematic diagram.
Embodiment
With reference to Figure of description and specific embodiment, the method for designing with the different impedance Control transmission line of layer of the present invention is described in detail below.
Method for designing with the different impedance Control transmission line of layer of the present invention, based on meeting impedance to ensure the impedance continuity of signal, reduce again conductor losses and optimize the requirement of signal integrity, describe design content and the advantage of the method below by embodiment in detail.
Embodiment 1:
Accompanying drawing 1 is for calculating the stepped construction schematic diagram of mainboard in this embodiment, as shown in Figure 1, in the calculating mainboard of server, Plane4 (L4) is GND layer, Plane5 (L5) is SIGNAL layer, Plane6 (L6) is GND layer, and Plane7 (L7) is POWER, SIGNAL, GND layer; Wherein, 85 ohm, 100 ohmage lines are positioned at Signal5 layer, are respectively Plane4, Plane6 up and down with reference to aspect; As shown in Figure 2, in the present embodiment, 85 ohmage lines are designed to live width (trace width) 5.5Mil, line-spacing (Trace Separation) 8Mil, transmission line thickness (Trace Thickness) 1.3Mil, between Signal5 and Plane4, distance H 1 is 7 Mil, between Signal5 and Plane6, distance H 2 is 5.5 Mil, this design ensures that 85 ohm transmission line impedance are controlled, live width devise optimum;
But this design can cause 100 ohm transmission line live widths narrower, and narrower live width, along with signal rate raises, electric current concentrates on conductive surface, can cause conductor losses problem; Therefore, ensureing that for fear of 100 ohm transmission line under the prerequisite of impedance, live width is meticulous, in the present embodiment, increasing the distance of 100 ohm transmission line and reference planes.But simple strengthen distance between the distance H 1(Signal5 of reference planes and Plane4), distance between H2(Signal5 and Plane6), can affect 85 ohm transmission line impedance; Utilize the method for the invention, artificially increase the distance of 100 ohm transmission line and reference planes, hollow out the Copper Foil of 100 ohm transmission line below Plane6, make it with reference to Plane7 layer, Substrate 2 Height become 11 Mil from 5.5Mil; Adopt this design, use impedance computation software, 100 ohm transmission line designs meet impedance requirement, as shown in Figure 3.
Embodiment 2:
In a blade server, calculate that to have the PCIE3.0 bus of 85 ohm and transfer rate 14Gbps impedance Control in mainboard be the FDR bus of 100 ohm, this calculating mainboard stepped construction is 14 layers, the 3rd layer of wiring layer has 85 ohm, 100 ohm transmission line, wherein 85 ohm of buses are more, and 100 ohm of buses only have 16 pairs of differential lines.In the present embodiment, 85 ohm transmission line are designed to live width 6Mil, line-spacing 8Mil, 100 ohm transmission line are designed to live width 6.5Mil, line-spacing 9Mil; Simultaneously in order to ensure the impedance design of 100 ohm, the present embodiment reference planes below 100 ohm transmission line hollow out, make 100 ohm transmission line with reference to below second layer plane, widen H2(Plane3 and Plane4 spacing) length, increase impedance, make it meet the design of 100 ohm, be unlikely to again to reduce live width.
Above-mentioned embodiment is only concrete case of the present invention; scope of patent protection of the present invention includes but not limited to above-mentioned embodiment; suitable variation or replacement that person of an ordinary skill in the technical field any claims according to the invention and any does it, all should fall into scope of patent protection of the present invention.
Claims (4)
1. the method for designing with the different impedance Control transmission line of layer, based on meeting impedance to ensure the impedance continuity of signal, reduce again conductor losses and optimize the requirement of signal integrity, it is characterized in that, the method for designing of this transmission line, according to the difference of calculating the Plane layer that on mainboard, different impedance Control transmission lines arrange jointly at server, live width, the line-spacing of controlling transmission line are carried out to different designs, ensureing, under the prerequisite of Low ESR transmission line design optimum, to carry out the optimal design of high-impedance transmission line; The optimal design of described high-impedance transmission line comprises: artificially increase high-impedance transmission line and the distance of calculating reference planes in mainboard, reference planes by high-impedance transmission line below hollow out, make high-impedance transmission line with reference to its below second layer plane, widen the distance of high-impedance transmission line and reference planes.
2. the method for designing with the different impedance Control transmission line of layer according to claim 1, is characterized in that, described Low ESR transmission line is 85 ohm transmission line, and described high-impedance transmission line is 100 ohm transmission line.
3. the method for designing with the different impedance Control transmission line of layer according to claim 2, it is characterized in that, in the calculating mainboard of server, 85 ohm, 100 ohm transmission line are positioned at Signal5 layer, transmission line be respectively Plane4, Plane6 with reference to aspect up and down; It is that 7 Mil and Signal5 and Plane6 spacing are 5.5 Mil that 85 ohm, 100 ohm transmission line are all designed to live width 5.5Mil, line-spacing 8Mil, Signal5 and Plane4 spacing; Artificially increase the distance of 100 ohm transmission line and reference planes, hollow out the Copper Foil of 100 ohm transmission line below Plane6, make it with reference to Plane7 layer, Signal5 and Plane6 spacing become 11 Mil from 5.5Mil.
4. the method for designing with the different impedance Control transmission line of layer according to claim 1, it is characterized in that, in blade server, calculate in mainboard and have the PCIE3.0 bus of 85 ohm and the FDR bus of 100 ohm, this calculating mainboard stepped construction is 14 layers, and 85 ohm, 100 ohm transmission line are arranged on the 3rd layer of wiring layer, and 85 ohm transmission line are designed to live width 6Mil, line-spacing 8Mil, 100 ohm transmission line are designed to live width 6.5Mil, line-spacing 9Mil; 100 ohm transmission line below reference planes are hollowed out simultaneously, make 100 ohm transmission line with reference to its below second layer plane, increase the spacing of transmission line and below reference planes.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201410210573.7A CN103970956A (en) | 2014-05-19 | 2014-05-19 | Design method for control transmission lines on same layer and with different impedance |
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| CN201410210573.7A CN103970956A (en) | 2014-05-19 | 2014-05-19 | Design method for control transmission lines on same layer and with different impedance |
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106358364A (en) * | 2016-11-24 | 2017-01-25 | 湖南长城银河科技有限公司 | Printed circuit board and Fanout wiring method |
| CN106385765A (en) * | 2016-09-09 | 2017-02-08 | 郑州云海信息技术有限公司 | Method and system for determining signal line reference layer |
| CN106529077A (en) * | 2016-11-29 | 2017-03-22 | 郑州云海信息技术有限公司 | Simulation design method for AC coupling capacitor reference plane |
| CN107454736A (en) * | 2017-06-27 | 2017-12-08 | 上达电子（深圳）股份有限公司 | A kind of circuit board and its cabling impedance adjustment |
| CN108804809A (en) * | 2018-06-07 | 2018-11-13 | Oppo（重庆）智能科技有限公司 | Emulation mode, system and the Wiring structure of DDR circuits |
| CN112115673A (en) * | 2020-09-27 | 2020-12-22 | 浪潮电子信息产业股份有限公司 | PCIE signal PIN adjacent layer hollowing design method, system, device and storage medium |
| CN114786328A (en) * | 2022-05-23 | 2022-07-22 | 西安易朴通讯技术有限公司 | Multilayer printed circuit board |
| CN117098305A (en) * | 2023-10-18 | 2023-11-21 | 井芯微电子技术(天津)有限公司 | High-speed backboard capable of switching transmission line impedance |
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| CN102291951A (en) * | 2011-06-20 | 2011-12-21 | 华为终端有限公司 | Impedance control method and structure of FPC (Flexible Printed Circuit) |
| CN103108486A (en) * | 2013-01-18 | 2013-05-15 | 浪潮电子信息产业股份有限公司 | Design method of cross-layer reference loss reduction |
| CN103442513A (en) * | 2013-05-27 | 2013-12-11 | 浪潮集团有限公司 | Method for achieving continuous characteristic impedance of high-frequency lines |
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| CN102291951A (en) * | 2011-06-20 | 2011-12-21 | 华为终端有限公司 | Impedance control method and structure of FPC (Flexible Printed Circuit) |
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Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106385765A (en) * | 2016-09-09 | 2017-02-08 | 郑州云海信息技术有限公司 | Method and system for determining signal line reference layer |
| CN106385765B (en) * | 2016-09-09 | 2018-09-04 | 郑州云海信息技术有限公司 | A kind of determination method and system of signal wire reference layer |
| CN106358364A (en) * | 2016-11-24 | 2017-01-25 | 湖南长城银河科技有限公司 | Printed circuit board and Fanout wiring method |
| CN106529077A (en) * | 2016-11-29 | 2017-03-22 | 郑州云海信息技术有限公司 | Simulation design method for AC coupling capacitor reference plane |
| CN107454736A (en) * | 2017-06-27 | 2017-12-08 | 上达电子（深圳）股份有限公司 | A kind of circuit board and its cabling impedance adjustment |
| CN107454736B (en) * | 2017-06-27 | 2019-08-27 | 上达电子（深圳）股份有限公司 | A kind of circuit board and its cabling impedance adjustment |
| CN108804809A (en) * | 2018-06-07 | 2018-11-13 | Oppo（重庆）智能科技有限公司 | Emulation mode, system and the Wiring structure of DDR circuits |
| CN112115673A (en) * | 2020-09-27 | 2020-12-22 | 浪潮电子信息产业股份有限公司 | PCIE signal PIN adjacent layer hollowing design method, system, device and storage medium |
| CN114786328A (en) * | 2022-05-23 | 2022-07-22 | 西安易朴通讯技术有限公司 | Multilayer printed circuit board |
| CN114786328B (en) * | 2022-05-23 | 2024-04-30 | 西安易朴通讯技术有限公司 | Multilayer printed circuit board |
| CN117098305A (en) * | 2023-10-18 | 2023-11-21 | 井芯微电子技术(天津)有限公司 | High-speed backboard capable of switching transmission line impedance |
| CN117098305B (en) * | 2023-10-18 | 2024-02-20 | 井芯微电子技术(天津)有限公司 | High-speed backboard capable of switching transmission line impedance |
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Application publication date: 20140806 |