CN114786328B - Multilayer printed circuit board - Google Patents
Multilayer printed circuit board Download PDFInfo
- Publication number
- CN114786328B CN114786328B CN202210562806.4A CN202210562806A CN114786328B CN 114786328 B CN114786328 B CN 114786328B CN 202210562806 A CN202210562806 A CN 202210562806A CN 114786328 B CN114786328 B CN 114786328B
- Authority
- CN
- China
- Prior art keywords
- widened
- layer
- ended
- hole
- trace
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 6
- 229910052802 copper Inorganic materials 0.000 claims description 6
- 239000010949 copper Substances 0.000 claims description 6
- 239000007787 solid Substances 0.000 claims description 4
- 230000008054 signal transmission Effects 0.000 abstract description 12
- 238000000034 method Methods 0.000 description 7
- 238000012545 processing Methods 0.000 description 7
- 238000004088 simulation Methods 0.000 description 5
- 230000009286 beneficial effect Effects 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000006978 adaptation Effects 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000005253 cladding Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000012937 correction Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
- H05K1/0237—High frequency adaptations
- H05K1/025—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance
- H05K1/0251—Impedance arrangements, e.g. impedance matching, reduction of parasitic impedance related to vias or transitions between vias and transmission lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
The application provides a multilayer printed circuit board, which comprises a first single-ended wiring layer and n reference layers which are sequentially stacked along a first direction, wherein n is a positive integer greater than 1; the first single-ended wiring layer comprises a plurality of single-ended wirings, and at least one single-ended wiring is a widened wiring in the plurality of single-ended wirings; at least one through hole group is arranged on the first m-layer reference layer close to the first single-ended wiring layer, the through hole group comprises a plurality of through holes, each through hole penetrates through the first m-layer reference layer close to the first single-ended wiring layer, and m is a positive integer smaller than n; the through hole groups are in one-to-one correspondence with the widened wires, and the through hole groups are used for enabling the widened wires of the corresponding through hole groups to refer to the (m+1) th layer of reference layer through the through hole groups so as to raise the characteristic impedance of the widened wires. Under the condition that the characteristic impedance of the single-ended wiring is matched with the target impedance, the multilayer printed circuit board widens the single-ended wiring with smaller width so as to increase the quality of single-ended wiring signal transmission.
Description
Technical Field
The embodiment of the application relates to the technical field of circuit boards, in particular to a multilayer printed circuit board.
Background
A printed circuit board (Printed circuit board, abbreviated as PCB) is one of the important components of the electronics industry. Almost every electronic device, as small as an electronic watch, a calculator, as large as a computer, a communication electronic device, a military weapon system, has only electronic components such as an integrated circuit, and a printed circuit board is used for electrically interconnecting the respective components.
The printed circuit board includes a single-sided printed circuit board, a double-sided printed circuit board, and a multi-layered printed circuit board. In the related art, a multilayer printed circuit board with single-ended wiring includes a plurality of single-ended wiring layers and a plurality of reference layers, each single-ended wiring layer corresponds to one reference layer, the corresponding single-ended wiring layer is adjacent to the reference layer, and an insulating medium layer is arranged between the corresponding single-ended wiring layer and the reference layer. When the multilayer printed circuit board with the single-ended wiring is designed, in order to match the characteristic impedance of the single-ended wiring with the target impedance (the protocol impedance of a chip connected with the single-ended wiring), the line width of part of the single-ended wiring is smaller, but when the line width of the single-ended wiring is smaller, the current carrying capacity of the single-ended wiring is poorer, and the signal transmission quality of the single-ended wiring is affected.
Disclosure of Invention
The embodiment of the application provides a multilayer printed circuit board which is used for solving the technical problem that the quality of single-ended wiring signal transmission is affected due to smaller line width of part of single-ended wiring.
The embodiment of the application provides the following technical scheme for solving the technical problems:
the embodiment of the application provides a multilayer printed circuit board, which comprises a first single-ended wiring layer and n reference layers, wherein the first single-ended wiring layer and the n reference layers are sequentially stacked along a first direction, n is a positive integer greater than 1, and the reference layers are solid copper layers;
The first single-ended wiring layer comprises a plurality of single-ended wirings, and at least one single-ended wiring is a widened wiring in the plurality of single-ended wirings;
At least one through hole group is arranged on the front m-layer reference layer close to the first single-end wiring layer, the through hole group comprises a plurality of through holes, each through hole penetrates through the front m-layer reference layer close to the first single-end wiring layer, and m is a positive integer smaller than n;
The through hole groups are in one-to-one correspondence with the widened wires, and the through hole groups are used for enabling the widened wires corresponding to the through hole groups to refer to the (m+1) th layer of reference layer through the through hole groups so as to raise the characteristic impedance of the widened wires.
The embodiment of the application has the beneficial effects that: the multilayer printed circuit board provided by the embodiment of the application widens at least part of single-ended wires with smaller width in the single-ended wire layers, namely, widens at least one single-ended wire of the first single-ended wire layer to form widened wires, under the condition that the reference layer is unchanged, the characteristic impedance of the widened wires is reduced after the widened wires are widened, in order to enable the characteristic impedance of the widened wires to be matched with the target impedance after the widened wires are widened, through hole groups corresponding to the widened wires are arranged on the first m-layer reference layer close to the first single-ended wire layer, so that the widened wires penetrate through the m+1th layer reference layer, capacitance between the widened wires and the reference layer is reduced, the characteristic impedance of the widened wires is increased due to the fact that the characteristic impedance of the widened wires is matched with the target impedance, the width of the widened wires is required to be increased, and therefore the purpose of signal transmission of the single-ended wires with smaller width and the purpose of single-ended signal transmission of the widened wires is achieved under the condition that the characteristic impedance of the widened wires is ensured to be matched with the target impedance.
In a possible implementation manner, in the corresponding through hole group and the widening routing, the plurality of through holes of the through hole group are distributed in two rows, and the orthographic projection of the widening routing on a first plane is located between orthographic projections of the two rows of through holes on the first plane, and the first plane is perpendicular to the first direction.
In one possible implementation manner, in the corresponding through hole group and the widening trace, a plurality of through holes of the through hole group are distributed in a row along a length direction of the widening trace, an orthographic projection of the widening trace on a first plane is parallel to an orthographic projection of a plurality of through holes distributed in a row on the first plane, and the first plane is perpendicular to the first direction.
In a possible implementation manner, when the corresponding through hole group and the widening wire are orthographic projected on the first plane, a vertical distance between a side of each through hole of the through hole group, which is close to the widening wire, and the widening wire is not less than 5mil.
In one possible implementation, the through hole is a trapezoid hole, a lower bottom edge of the trapezoid hole is parallel to the widened wire, and the lower bottom edge of the trapezoid hole is located on a side close to the widened wire.
In a possible embodiment, the length of the lower base of the trapezoid hole is equal to the width of the widened trace.
In one possible embodiment, in the same row of the through holes, a distance between lower bottom edges of two adjacent trapezoidal holes is not greater than a length of the lower bottom edges of the trapezoidal holes.
In a possible implementation manner, in two rows of through holes of the through hole group, which are orthographic projected on the first plane, orthographic projection of one row of through holes on a first straight line forms a plurality of first line segments which are distributed at intervals, orthographic projection of the other row of through holes on the first straight line forms a plurality of second line segments which are distributed at intervals, the first straight line is positioned in the first plane, and the first straight line is parallel to the extending direction of each row of through holes;
The first line segments and the second line segments are alternately arranged on the first straight line, and any adjacent first line segments and second line segments are at least partially overlapped.
In one possible embodiment, the reference layer is a ground layer.
In one possible embodiment, the width of the widened trace is greater than 3 mils.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
FIG. 1 is a schematic diagram of a multi-layer printed circuit board according to an embodiment of the present application;
FIG. 2 is an orthographic view of a via group on a first plane according to an embodiment of the present application;
FIG. 3 is an orthographic view of a widened trace and two corresponding rows of vias on a first plane according to an embodiment of the present application;
FIG. 4 is an orthographic view of a widening trace and a corresponding row of through holes on a first plane according to an embodiment of the present application;
fig. 5 is a graph showing HFSS simulation results of a multilayer printed circuit board according to an embodiment of the present application and a related art multilayer printed circuit board.
Reference numerals illustrate:
100. A single-ended wiring layer;
110. Widening the wiring;
200. An insulating dielectric layer;
300. A reference layer;
310. a through hole;
400. a second wiring layer;
500. A first plane.
Specific embodiments of the present application have been shown by way of the above drawings and will be described in more detail below. The drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but rather to illustrate the inventive concepts to those skilled in the art by reference to the specific embodiments.
Detailed Description
In the related art, a multilayer printed circuit board with single-ended wiring includes a plurality of single-ended wiring layers and a plurality of reference layers, each single-ended wiring layer corresponds to one reference layer, the corresponding single-ended wiring layer is adjacent to the reference layer, and an insulating medium layer is arranged between the corresponding single-ended wiring layer and the reference layer. In order to ensure the quality of signal transmission and avoid reflection, the characteristic impedance of the single-ended wire needs to be matched with the target impedance (the protocol impedance of a chip connected with the single-ended wire), but the thickness of an insulating medium layer between the single-ended wire layer and a reference layer is generally thinner, so that the distance between the adjacent single-ended wire layer and the reference layer is too close, and therefore, when the single-ended wire is designed, the line width of part of the single-ended wire is smaller, the current carrying capacity of the single-ended wire with smaller line width is poorer, and the quality of the single-ended wire signal transmission is affected. On the other hand, when the line width of the single-ended wiring is smaller than 3mil, the processing of the single-ended wiring is difficult, so that in the actual processing process of the single-ended wiring, the processing error of the single-ended wiring with the line width smaller than 3mil is larger, the characteristic impedance of the single-ended wiring is not matched with the target impedance, and the quality of signal transmission is further affected.
Therefore, in the embodiment of the application, the through hole group is arranged on the m-th reference layer close to the single-end wiring, so that the single-end wiring can refer to the m+1th reference layer through the through hole group, the capacitance between the single-end wiring and the reference layer is reduced, the capacitance between the widened wiring and the reference layer is reduced, the characteristic impedance of the single-end wiring is increased, the width of the single-end wiring is increased to reduce the characteristic impedance of the widened wiring in order to match the characteristic impedance of the widened wiring with the target impedance, and the purpose of widening the single-end wiring with smaller width under the condition that the characteristic impedance of the single-end wiring is ensured to match the target impedance is realized, so that the signal transmission quality of the single-end wiring is improved.
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
FIG. 1 is a schematic diagram of a multi-layer circuit board according to an embodiment of the present application; FIG. 2 is an orthographic view of a via group on a first plane according to an embodiment of the present application; FIG. 3 is an orthographic view of a widened trace and two corresponding rows of vias on a first plane according to an embodiment of the present application; FIG. 4 is an orthographic view of a widening trace and a corresponding row of through holes on a first plane according to an embodiment of the present application; fig. 5 is a graph showing HFSS simulation results of a multilayer printed circuit board according to an embodiment of the present application and a related art multilayer printed circuit board.
The multilayer printed circuit board provided by the embodiment of the application can be in a four-layer structure, a six-layer structure, an eight-layer structure or a more-layer structure. When the multi-layer printed circuit board is of a six-layer structure, the six-layer printed circuit board comprises a first single-end wiring layer and three reference layers which are sequentially stacked along a first direction, wherein the reference layer close to the first single-end wiring layer is a first reference layer, the reference layer positioned in the middle is a second reference layer, the reference layer far away from the first single-end wiring layer is a third reference layer, the six-layer printed circuit board further comprises a second wiring layer corresponding to the second reference layer and a third wiring layer corresponding to the third reference layer, that is, the six-layer printed circuit board comprises a first single-end wiring layer, a first reference layer, a second wiring layer, a second reference layer, a third reference layer and a third wiring layer which are sequentially stacked along the first direction, and an insulating medium layer is arranged between the adjacent two layers. For another example, as shown in fig. 1, when the multi-layer printed circuit board has a four-layer structure, the four-layer printed circuit board includes a first single-ended trace layer 100 and two reference layers 300 sequentially stacked along a first direction, the four-layer printed circuit board further includes a second trace layer 400 corresponding to the reference layer 300 far from the first single-ended trace layer 100, that is, the four-layer printed circuit board includes the first single-ended trace layer 100, the reference layer 300, and the second trace layer 400 sequentially stacked along the first direction, and an insulating medium layer 200 is disposed between two adjacent layers, that is, the four-layer printed circuit board includes the first single-ended trace layer 100, the insulating medium layer 200, the reference layer 300, the insulating medium layer 200, and the second single-ended trace layer 100 sequentially stacked along the first direction. That is, the multilayer printed circuit board provided in the embodiment of the present application includes a first single-ended trace layer 100 and n reference layers 300 stacked in sequence along a first direction, where n is a positive integer greater than 1, and the reference layers 300 are solid copper layers.
It is understood that the first direction is a thickness direction of the multilayer printed circuit board.
In an embodiment of the present application, as shown in fig. 2, 3 and 4, the first single-ended trace layer 100 includes a plurality of single-ended traces, and at least one single-ended trace is a widened trace 110. That is, at least one single-ended trace among the plurality of single-ended traces is widened to form the widened trace 110, and after the single-ended trace is widened, the current carrying capability of the single-ended trace can be improved, and the processing is facilitated. In order to match the characteristic impedance of the single-ended trace after the widening process with the target impedance, at least one via group is disposed on the first m reference layers 300 adjacent to the first single-ended trace layer 100, where the via group corresponds to the widening trace 110 one by one, that is, one widening trace 110 is disposed, and one via group is disposed; two widening wires 110 are arranged, and two through hole groups are arranged; five widening traces 110 are provided and five via groups are provided.
The via group includes a plurality of vias 310, each via 310 penetrating through the first m reference layers 300 adjacent to the first single-ended trace layer 100, where m is a positive integer less than n. The via group is used for enabling the widened wire 110 of the corresponding via group to refer to the m+1th layer reference layer 300 through the via group, when the widened wire 110 is used for referring to the m+1th layer reference layer 300 through the via group, the capacitance of the widened wire 110 with respect to the m+1th layer reference layer 300 through the via group is reduced, that is, the capacitance between the widened wire 110 and the associated reference layer 300 is reduced, so that the characteristic impedance of the widened wire 110 is increased, and in order to match the characteristic impedance of the widened wire 110 with the target impedance, the width of the widened wire 110 needs to be increased to reduce the characteristic impedance of the widened wire 110, so that the purpose of widening the single-ended wire with smaller width under the condition that the characteristic impedance of the single-ended wire is ensured to match the target impedance is achieved, and the purpose of increasing the quality of single-ended wire signal transmission is achieved.
For the analysis, it is exemplified that when no via group is provided on the front m-layer reference layer 300 near the first single-end wiring layer 100, i.e. the reference layer 300 is a solid copper layer without a via group, at this time, the first single-end wiring layer 100 has a single-end wiring with a smaller width, for example, one of the single-end wirings with a smaller width is the first single-end wiring, the width of the first single-end wiring is 2.5mil in design, the characteristic impedance (equal to the target impedance) is 50ohm, the width of the first single-end wiring is smaller, so that the processing difficulty is larger and the current carrying capability is worse, and the processing is convenient, in this case, a via group corresponding to the first single-end wiring is provided on the front m-layer reference layer 300 near the first single-end wiring layer 100, at this time, the first single-end wiring penetrates through the via group to the m+1-th layer reference layer 300, so that the characteristic impedance of the first single-end wiring is raised, for example, the characteristic impedance of the first single-end wiring is raised to the first single-end wiring (equal to the target impedance) is 50ohm, the characteristic impedance of the first single-end wiring is raised, and the characteristic impedance of the first single-end wiring is lowered by implementing the first single-end wiring, and the application is lowered, and the characteristic impedance of the first single-end wiring is lowered by setting the first single-end wiring to be 50ohm, and the characteristic impedance is lowered, and the first single-end wiring is lowered to the first line is required to be lowered, and the characteristic impedance is lowered by the first line and the line is lowered. It is understood that the first single-ended trace is the widened trace 110 of the first single-ended trace layer 100.
It should be noted that, m may be 1,2 or 3, and the value of m is designed according to the widening requirement of the single-ended trace, for example, a set of through holes is formed on a layer of reference layer 300 close to the first single-ended trace layer 100, so that the widening requirement of the widening trace 110 can be met when the widening trace 110 refers to the second layer of reference layer 300, and then the multilayer printed circuit board may only be formed on a layer of reference layer 300 close to the first single-ended trace layer 100. If the set of vias is not satisfactory only on one reference layer 300 close to the first single-ended trace layer 100, the widened trace 110 is still narrower after being widened, then the set of vias may be opened on two reference layers 300 close to the first single-ended trace layer 100, so that the widened trace 110 references the third reference layer 300, to further reduce the capacitance between the widened trace 110 and the associated reference layer 300, thereby further increasing the width of the widened trace 110.
Furthermore, it should be noted that, when the widened wire 110 references the third reference layer 300 or the reference layer 300 of the next layer, each wire of the wire layer located between the reference layer 300 of the widened wire 110 and the reference layer 300 of the widened wire 110 that is referenced through the via group avoids each via 310 of the via group.
The principle that disposing the group of vias corresponding to the widened trace 110 on the first m-layer reference layer 300 near the first single-ended trace layer 100 can increase the width of the widened trace 110 is as follows:
I＝KT0.44A0.75 (3)
In formula (1), C is capacitance, epsilon is dielectric constant, each material has its own dielectric constant, S is the facing area of the two plates of the capacitor, and k d is the distance between the two plates of the capacitor.
In formula (2), C is a capacitance, Z 0 is a trace characteristic impedance, and L is an inherent inductance of a transmission line per unit length.
In the formula (3), K is a correction coefficient, generally, the copper-clad wire takes 0.024 in the inner layer, 0.048 in the outer layer, T is the maximum temperature rise in degrees centigrade (the melting point of copper is 1060 ℃), A is the copper-clad sectional area in square mil, I is the allowable maximum current, and in amperes (amps).
Taking the first single-ended trace as an example, the target impedance of the first single-ended trace is 50ohm, and since the distance between the first single-ended trace and the reference layer 300 adjacent to the first single-ended trace is smaller, the line width of the first single-ended trace is narrower and is 2.5mil when the first single-ended trace is designed, in order to increase the line width of the first single-ended trace, a group of through holes is formed on the reference layer 300 adjacent to the first single-ended trace, the reference layer 300 adjacent to the first single-ended trace is the first reference layer 300, and the reason for the implementation is analyzed from the formula: when the through hole group is formed on the first reference layer 300, when the return current flows through the through hole group of the first reference layer 300, the current will refer to the next reference layer 300 (the second reference layer 300), that is, k d in formula (1) increases, the capacitance C will be reduced, the capacitance C is brought into formula (2), the capacitance C is reduced to increase the characteristic impedance of the first single-ended trace, and at this time, in order to maintain the characteristic impedance of the first single-ended trace at 50ohm, the first single-ended trace needs to be widened (the first single-ended trace is widened, the characteristic impedance is reduced), so that the requirement that the design line width is higher than 3mil is satisfied.
In addition, as can be seen from the formula 3, the smaller the copper-clad cross-sectional area a is, the worse the wiring current-carrying capacity I is, so as to avoid the damage to the first single-ended wiring caused by the large current generated during the switching power supply. Wherein, the copper-clad cross-sectional area A is the thickness of the copper cladding multiplied by the width of the copper-clad wire diameter.
In some embodiments of the present application, as shown in fig. 4, in the corresponding via group and the widened wire 110, a line width is first preset for a single-ended wire with a smaller width (the widened wire 110 is after the widening process), a characteristic impedance of the single-ended wire with the preset line width is calculated, when a difference between the characteristic impedance of the single-ended wire with the preset line width and a target impedance is less than 10ohm, the plurality of vias 310 of the via group are distributed in a row along a length direction of the widened wire 110, an orthographic projection of the widened wire 110 on the first plane 500 is parallel to an orthographic projection of the plurality of vias 310 distributed in a row on the first plane 500, the first plane 500 is perpendicular to the first direction, that is, the plurality of vias 310 are disposed in a row, and the row of vias 310 is located at one side of the widened wire 110. Since the difference between the characteristic impedance and the target impedance of the single-ended trace with the preset line width is smaller than 10ohm, that is, when the single-ended trace with the preset line width needs to be widened by a smaller amount, only one row of through holes 310 need to be formed in the reference layer 300 corresponding to the single-ended trace, at this time, the number of the through holes 310 is smaller, the through holes 310 are not easy to be divided into two rows, and the characteristic impedance distribution of the single-ended trace is uneven due to the fact that the two rows of through holes 310 are scattered relatively, so that signal transmission is affected.
In other embodiments of the present application, as shown in fig. 2 and fig. 3, in the corresponding via groups and the widened trace 110, when the reference layer 300 does not have the via groups corresponding to the widened trace 110, a line width is first preset for a single-ended trace with a smaller width (i.e. the widened trace 110 after the widening process), the characteristic impedance of the single-ended trace with the preset line width is calculated, and when the difference between the characteristic impedance of the widened trace 110 and the target impedance is greater than 10ohm, the plurality of vias 310 of the via groups are distributed in two rows, and the orthographic projection of the widened trace 110 on the first plane 500 is located between the orthographic projections of the two rows of vias 310 on the first plane 500, and the first plane 500 is perpendicular to the first direction. That is, the plurality of through holes 310 are divided into two rows, each row of through holes 310 extends in the length direction of the widened wire 110, and the two rows of through holes 310 are located at two sides of the widened wire 110, since the difference between the characteristic impedance and the target impedance of the single-ended wire with the preset line width is greater than 10ohm, that is, when the single-ended wire with the preset line width needs to be widened, the number of through holes 310 is greater, and the through holes 310 are divided into two rows, so that the number of through holes 310 can be conveniently set, and the number of through holes 310 can be increased, and the two rows of through holes 310 are located at two sides of the widened wire 110, so that the influence on the return current is smaller. Of course, when two rows of through holes 310 are formed in the reference layer 300 near the widening trace 110, the through hole groups may be formed in the second reference layer 300 at the same time, or the through holes 310 may be formed in the second reference layer 300 and the third reference layer 300.
In the arrangement of the single row of through holes 310 and the arrangement of the two rows of through holes 310, when the corresponding through hole group and the widening trace 110 are orthographically projected on the first plane 500, a vertical distance between a side of each through hole 310 of the through hole group, which is close to the widening trace 110, and the widening trace 110 is not less than 5mil. This arrangement can avoid the influence of the set of through holes on the reference layer 300 on the return current.
In some embodiments of the present application, the through hole 310 is a trapezoid hole, and the lower bottom edge of the trapezoid hole is parallel to the widened trace 110, and the lower bottom edge of the trapezoid hole is located at a side close to the widened trace 110. The arrangement enables the area with larger area of the lower part of the trapezoid to be close to the widened wire 110, the arrangement enables the capacitance between the widened wire 110 and the relevant reference layer 300 to be reduced more, the characteristic impedance of the widened wire 110 is improved, the area with smaller area of the upper part of the trapezoid is far away from the widened wire 110, and the arrangement can ensure that the through hole group acts on the widened wire 110 and simultaneously reduce the influence of the through hole group on other single-ended wires as much as possible. In addition, the trapezoid hole has a larger area than the triangle hole, and the trapezoid hole can reduce the capacitance between the widened wire 110 and the related reference layer 300 more than the triangle hole, which is beneficial to improving the characteristic impedance of the widened wire 110, and in the case that the first single-ended wire layer 100 has multiple single-ended wires, the trapezoid hole has interpenetration with the rectangular hole and the circular Kong Dengxiang, which can save space. Alternatively, in order to avoid the situation that the characteristic impedance of the widened wire 110 is discontinuous due to the arrangement of the via group, the length of the lower bottom edge of the trapezoid hole is equal to the width of the widened wire 110. Alternatively, in the same row of through holes 310, the interval between the lower bottom edges of adjacent two trapezoidal holes is not greater than the length of the lower bottom edges of the trapezoidal holes.
When the plurality of through holes 310 of the through hole group are arranged in two rows, as shown in fig. 2, in the two rows of through holes 310 of the through hole group that are orthographic projected on the first plane 500, orthographic projection of one row of through holes 310 on a first line forms a plurality of first line segments that are distributed at intervals, orthographic projection of the other row of through holes 310 on the first line forms a plurality of second line segments that are distributed at intervals, the first line is located in the first plane 500, and the first line is parallel to the extending direction of each row of through holes 310, that is, the first line is a line parallel to the length direction of the widening trace 110, which may be a line connecting the centers of each through hole 310 of one row. The first line segments and the second line segments are alternately arranged on the first straight line, and any adjacent first line segments and second line segments are at least partially overlapped. That is, any adjacent first line segment and second line segment may be overlapped at end points or partially overlapped, which can make the continuity of the characteristic impedance of the widened wire 110 better, and avoid the uneven distribution of the characteristic impedance of the widened wire 110, and influence the signal transmission.
In the embodiment of the present application, each reference layer 300 is a Ground layer (GND), and the width of the widened wire 110 is greater than 3mil, that is, the width of the widened wire 110 is greater than 3mil after the widening process, which is convenient for processing the widened wire 110.
In the simulation process of the multilayer printed circuit board provided by the embodiment of the application and the multilayer printed circuit board of the related art, as shown in fig. 5, the simulation result of the HFSS (High Frequency Simulator Structure, abbreviated as HFSS, HFSS is a 3D modeling tool) of the multilayer printed circuit board is compared with that of the multilayer printed circuit board of the related art, except that in the simulation process of the multilayer printed circuit board provided by the embodiment of the application and the multilayer printed circuit board of the related art, the through hole group is arranged on the reference layer corresponding to the single-ended wiring with smaller width, other parameters are unchanged, in the figure, 1 is the impedance curve of the single-ended wiring with smaller width of the multilayer printed circuit board of the related art, and 2 is the impedance curve of the corresponding single-ended wiring in the multilayer printed circuit board provided by the embodiment of the application, compared with the two curves, the through hole group is arranged on the reference layer corresponding to the single-ended wiring with smaller width, so that the characteristic impedance of the single-ended wiring is required to be widened, and the single-ended wiring is well suppressed after being widened.
This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.
Claims (9)
1. The multilayer printed circuit board is characterized by comprising a first single-ended wiring layer and n reference layers which are sequentially stacked along a first direction, wherein n is a positive integer greater than 1, and the reference layers are solid copper layers;
The first single-ended wiring layer comprises a plurality of single-ended wirings, and at least one single-ended wiring is a widened wiring in the plurality of single-ended wirings;
At least one through hole group is arranged on the front m-layer reference layer close to the first single-end wiring layer, the through hole group comprises a plurality of through holes, each through hole penetrates through the front m-layer reference layer close to the first single-end wiring layer, and m is a positive integer smaller than n;
The through hole groups are in one-to-one correspondence with the widened wires, and the through hole groups are used for enabling the widened wires corresponding to the through hole groups to refer to the m+1th layer of reference layer through the through hole groups so as to raise the characteristic impedance of the widened wires;
The through hole is a trapezoid hole, the lower bottom edge of the trapezoid hole is parallel to the widened wiring, and the lower bottom edge of the trapezoid hole is located on one side close to the widened wiring.
2. The multilayer printed circuit board of claim 1, wherein in the corresponding set of vias and the widened trace, a plurality of the vias of the set of vias are distributed in two rows, an orthographic projection of the widened trace on a first plane is located between orthographic projections of the two rows of the vias on the first plane, the first plane being perpendicular to the first direction.
3. The multilayer printed circuit board of claim 1, wherein in the corresponding set of vias and the widened trace, a plurality of the vias of the set of vias are distributed in a row along a length direction of the widened trace, an orthographic projection of the widened trace on a first plane is parallel to an orthographic projection of the plurality of vias distributed in a row on the first plane, and the first plane is perpendicular to the first direction.
4. A multilayer printed circuit board according to claim 2 or 3, wherein the vertical distance between the side of each through hole of the group of through holes close to the widened trace and the widened trace is not less than 5mil when the corresponding group of through holes and the widened trace are orthographically projected on the first plane.
5. The multilayer printed circuit board of claim 4, wherein a length of a lower base of the trapezoid hole is equal to a width of the widened trace.
6. The multilayer printed circuit board of claim 4, wherein in the same row of said through holes, a spacing between lower bases of adjacent two of said trapezoidal holes is not greater than a length of a lower base of said trapezoidal hole.
7. The multilayer printed circuit board of claim 2, wherein, in two rows of vias of the group of vias orthographically projected on the first plane, orthographically projected one row of vias on a first line forms a plurality of first line segments distributed at intervals, orthographically projected another row of vias on the first line forms a plurality of second line segments distributed at intervals, the first line is located in the first plane, and the first line is parallel to a direction in which each row of vias extends;
The first line segments and the second line segments are alternately arranged on the first straight line, and any adjacent first line segments and second line segments are at least partially overlapped.
8. The multilayer printed circuit board of claim 1, wherein the reference layer is a ground layer.
9. The multilayer printed circuit board of claim 8, wherein the line width of the widened trace is greater than 3 mils.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210562806.4A CN114786328B (en) | 2022-05-23 | 2022-05-23 | Multilayer printed circuit board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210562806.4A CN114786328B (en) | 2022-05-23 | 2022-05-23 | Multilayer printed circuit board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN114786328A CN114786328A (en) | 2022-07-22 |
| CN114786328B true CN114786328B (en) | 2024-04-30 |
Family
ID=82409258
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210562806.4A Active CN114786328B (en) | 2022-05-23 | 2022-05-23 | Multilayer printed circuit board |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN114786328B (en) |
Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5568107A (en) * | 1995-05-01 | 1996-10-22 | Apple Computer, Inc. | Transmission line having impedance set by reference plane fenestration |
| CN1780536A (en) * | 2004-11-25 | 2006-05-31 | 华为技术有限公司 | Impedance adjustment of multi-layer printing circuit board |
| CN1856214A (en) * | 2005-04-28 | 2006-11-01 | 日东电工株式会社 | Interconnect circuit substrate |
| JP2007141990A (en) * | 2005-11-16 | 2007-06-07 | Sumitomo Bakelite Co Ltd | Circuit board |
| CN101309547A (en) * | 2007-05-18 | 2008-11-19 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN102724809A (en) * | 2012-06-30 | 2012-10-10 | 索尔思光电（成都）有限公司 | Multi-layer PCB (printed circuit board) and manufacturing method thereof |
| CN103442513A (en) * | 2013-05-27 | 2013-12-11 | 浪潮集团有限公司 | Method for achieving continuous characteristic impedance of high-frequency lines |
| CN103970956A (en) * | 2014-05-19 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Design method for control transmission lines on same layer and with different impedance |
| CN104185362A (en) * | 2014-08-19 | 2014-12-03 | 深圳市兴森快捷电路科技股份有限公司 | Flexible printed circuit board trace impedance and delay control method |
| CN104797079A (en) * | 2015-04-10 | 2015-07-22 | 福州瑞芯微电子有限公司 | Method for reducing impedance mismatching on package and PCB (printed circuit board) |
| CN106257967A (en) * | 2015-06-19 | 2016-12-28 | 星电株式会社 | Multilayer printed-wiring board and multilayer printed-wiring board and the attachment structure of adapter |
| JP2019192844A (en) * | 2018-04-27 | 2019-10-31 | 京セラ株式会社 | Printed-circuit board |
-
2022
- 2022-05-23 CN CN202210562806.4A patent/CN114786328B/en active Active
Patent Citations (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5568107A (en) * | 1995-05-01 | 1996-10-22 | Apple Computer, Inc. | Transmission line having impedance set by reference plane fenestration |
| CN1780536A (en) * | 2004-11-25 | 2006-05-31 | 华为技术有限公司 | Impedance adjustment of multi-layer printing circuit board |
| CN1856214A (en) * | 2005-04-28 | 2006-11-01 | 日东电工株式会社 | Interconnect circuit substrate |
| JP2007141990A (en) * | 2005-11-16 | 2007-06-07 | Sumitomo Bakelite Co Ltd | Circuit board |
| CN101309547A (en) * | 2007-05-18 | 2008-11-19 | 鸿富锦精密工业（深圳）有限公司 | Printed circuit board |
| CN102724809A (en) * | 2012-06-30 | 2012-10-10 | 索尔思光电（成都）有限公司 | Multi-layer PCB (printed circuit board) and manufacturing method thereof |
| CN103442513A (en) * | 2013-05-27 | 2013-12-11 | 浪潮集团有限公司 | Method for achieving continuous characteristic impedance of high-frequency lines |
| CN103970956A (en) * | 2014-05-19 | 2014-08-06 | 浪潮电子信息产业股份有限公司 | Design method for control transmission lines on same layer and with different impedance |
| CN104185362A (en) * | 2014-08-19 | 2014-12-03 | 深圳市兴森快捷电路科技股份有限公司 | Flexible printed circuit board trace impedance and delay control method |
| CN104797079A (en) * | 2015-04-10 | 2015-07-22 | 福州瑞芯微电子有限公司 | Method for reducing impedance mismatching on package and PCB (printed circuit board) |
| CN106257967A (en) * | 2015-06-19 | 2016-12-28 | 星电株式会社 | Multilayer printed-wiring board and multilayer printed-wiring board and the attachment structure of adapter |
| JP2019192844A (en) * | 2018-04-27 | 2019-10-31 | 京セラ株式会社 | Printed-circuit board |
Also Published As
| Publication number | Publication date |
|---|---|
| CN114786328A (en) | 2022-07-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10194524B1 (en) | Anti-pad for signal and power vias in printed circuit board | |
| US7601919B2 (en) | Printed circuit boards for high-speed communication | |
| US7435912B1 (en) | Tailoring via impedance on a circuit board | |
| US4560962A (en) | Multilayered printed circuit board with controlled 100 ohm impedance | |
| US9202783B1 (en) | Selective antipad backdrilling for printed circuit boards | |
| US6236572B1 (en) | Controlled impedance bus and method for a computer system | |
| US4553111A (en) | Printed circuit board maximizing areas for component utilization | |
| US8071890B2 (en) | Electrically conductive structure of circuit board and circuit board using the same | |
| US20100259338A1 (en) | High frequency and wide band impedance matching via | |
| US10292257B2 (en) | Cross-talk reduction for high speed signaling at ball grid array region and connector region | |
| US20120247825A1 (en) | Printed circuit board | |
| TWI429343B (en) | Printed circuit board | |
| KR100666224B1 (en) | Rigid flexible printed circuit board having openings | |
| US20060044083A1 (en) | Circuit board and method for producing a circuit board | |
| CN108575044B (en) | Printed circuit board and assembly thereof | |
| JP2009021511A (en) | Printed wiring board, and electronic device | |
| JP4933318B2 (en) | Printed circuit board assembly and inverter using the printed circuit board assembly | |
| US4004196A (en) | Multi-layer panel board with single-in-line package for high speed switching logic | |
| CN114786328B (en) | Multilayer printed circuit board | |
| US20020139568A1 (en) | Buried intersignal capacitance | |
| US20100175911A1 (en) | High-Speed Two-Layer and Multilayer Circuit Boards | |
| US7271472B2 (en) | Circuit board and method for producing a circuit board | |
| CN113891576A (en) | Layer-changing through hole circuit comprising multilayer PCB, manufacturing method and equipment | |
| US20040189418A1 (en) | Method and structure for implementing enhanced differential signal trace routing | |
| EP0137694B1 (en) | Printed circuit board maximizing areas for component utilization |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |