CN107240417B

CN107240417B - High-voltage anti-coupling high-voltage bleeder circuit of memory

Info

Publication number: CN107240417B
Application number: CN201710632485.XA
Authority: CN
Inventors: 刘吉平; 朱金桥; 唐伟
Original assignee: Shenzhen Hangshun Chip Technology R&D Co Ltd
Current assignee: Shenzhen Hangshun Chip Technology R&D Co Ltd
Priority date: 2017-07-28
Filing date: 2017-07-28
Publication date: 2023-06-02
Anticipated expiration: 2037-07-28
Also published as: CN107240417A

Abstract

The invention discloses a high-voltage anti-coupling high-voltage bleeder circuit of a memory, which comprises a first memory cell, a second memory cell, a node A and a node B, wherein parasitic capacitance Cg is arranged between the node A and the node B, an auxiliary circuit is connected in series between the node A and the node B, the auxiliary circuit comprises a resistor string, a voltage comparator and an NMOS switch tube, the resistor string arranged in the auxiliary circuit is divided into the voltage comparator, the voltage comparator controls the on-off of the NMOS switch tube, the node B is instantly pulled down to a low level, the high voltage coupled by the Cg can be weakened, and the right memory cell is protected from being wrongly written; the patent aims at the phenomenon of misoperation of adjacent memory cells possibly caused by high-voltage coupling in the read-write process of the memory cells, adopts necessary high-voltage anti-coupling high-voltage release measures, designs corresponding circuits, and achieves the aim of preventing the adjacent memory cells from being wrongly written.

Description

High-voltage anti-coupling high-voltage bleeder circuit of memory

Technical Field

The patent relates to the field of storage hardware, in particular to a high-voltage anti-coupling high-voltage bleeder circuit of a memory.

Background

In the nonvolatile memory circuit, the memory cells in the memory are subjected to read-write operation through high-voltage signals. When the read-write circuit reads and writes a certain memory cell, the read-write state of the adjacent circuit is not affected, and misoperation is caused to affect the accuracy and reliability of data. The traditional nonvolatile memory has large unit area, large adjacent distance, less serious voltage signal coupling and no coupling prevention measure. However, as the area size of the memory cells is smaller and smaller, the arrangement between the cells is more compact, the signal coupling of the high voltage control signal to the adjacent cells is more serious, and the misreading and writing operation of the cells are frequent, which has to draw attention. In order to prevent this phenomenon, effective measures must be taken to add a high-voltage coupling prevention circuit to the memory cell and its accessory circuit, so as to ensure that high-voltage signals are not coupled or cross-linked to adjacent memory cells.

Disclosure of Invention

The present invention is directed to overcome the above-mentioned problems in the prior art, and provides a high-voltage anti-coupling high-voltage bleeder circuit for a memory, which prevents erroneous writing of data due to high-voltage coupling between adjacent memory cells in a high-density nonvolatile memory.

In order to achieve the technical purpose and achieve the technical effect, the patent is realized by the following technical scheme:

the utility model provides a high-voltage anti-coupling high-voltage bleeder circuit of memory, includes adjacent non-volatile memory unit first memory cell, second memory cell, node A and node B, be equipped with parasitic capacitance Cg between node A and the node B, it has the auxiliary circuit to establish ties between node A and the node B, the auxiliary circuit includes resistor string, voltage comparator and NMOS switch tube, and the resistor string partial pressure that the auxiliary circuit was equipped gives voltage comparator, voltage comparator control NMOS switch tube break-make, node B pulls down to low level in the twinkling of an eye, can weaken the high voltage of Cg coupling, has protected the right memory cell can not by the write in by mistake.

Further, the input end of the voltage comparator is respectively connected with the resistor string node and the reference voltage end to form a voltage comparison circuit, the output end of the voltage comparator is connected with the grid electrode of the NMOS switching tube to control the on-off of the source electrode and the drain electrode of the NMOS switching tube, and the source electrode and the drain electrode of the NMOS switching tube are respectively connected with the ground wire and the node B.

Further, the resistor string is provided with a first resistor, a second resistor and a third resistor which are connected in series, the third resistor is an adjustable resistor and is grounded, the connection end of the third resistor and the second resistor is connected with the negative end of the voltage comparator, and the positive end of the voltage comparator is connected with the reference source to form an open-loop voltage comparator circuit.

Further, the first resistor, the second resistor and the third resistor are well resistors.

Further, the aspect ratio of the NMOS transistor is greater than ten to one.

The benefit effect of this patent is:

the patent aims at the phenomenon of misoperation of adjacent memory cells possibly caused by high-voltage coupling in the read-write process of the memory cells, adopts necessary high-voltage anti-coupling high-voltage release measures, designs corresponding circuits, and achieves the aim of preventing the adjacent memory cells from being wrongly written.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present patent, the drawings that are needed for the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present patent, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a first memory cell and a second memory cell according to the present invention;

FIG. 2 is a schematic diagram of an accessory circuit according to the present invention;

FIG. 3 is a waveform diagram of an uncoupled bleeder circuit;

fig. 4 is a waveform diagram of a coupled bleeder circuit.

Detailed Description

The following description of the embodiments of the present patent will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the present patent. All other embodiments, based on the embodiments in this patent, which would be within the purview of one of ordinary skill in the art without the particular effort to make the invention are intended to be within the scope of the patent protection.

As shown in fig. 1-4, this patent is a high-voltage anti-coupling high-voltage bleeder circuit of memory, including adjacent non-volatile memory unit first memory cell, second memory cell, node a and node B, be equipped with parasitic capacitance Cg between node a and the node B, be connected in series between node a and the node B and have the auxiliary circuit, the auxiliary circuit includes resistor string, voltage comparator and NMOS switch tube, the resistor string partial pressure that the auxiliary circuit was equipped with gives voltage comparator, voltage comparator control NMOS switch tube break-make, node B pulls down to low level in the twinkling of an eye, can weaken the high voltage of Cg coupling, protected the right memory cell can not by the write in by mistake.

The input end of the voltage comparator is respectively connected with the resistor string node and the reference voltage end to form a voltage comparison circuit, the output end of the voltage comparator is connected with the grid electrode of the NMOS switching tube to control the on-off of the source electrode and the drain electrode of the NMOS switching tube, and the source electrode and the drain electrode of the NMOS switching tube are respectively connected with the ground wire and the node B.

The resistor string is provided with a first resistor (R1), a second resistor (R2) and a third resistor (R3) which are connected in series, the third resistor is an adjustable resistor and is grounded, the connection end of the third resistor and the second resistor is connected with the negative end of the voltage comparator, and the positive end of the voltage comparator is connected with the reference source to form an open-loop voltage comparator circuit.

The first resistor, the second resistor and the third resistor are well resistors.

Wherein, the width-to-length ratio of the NMOS tube is more than ten to one.

One specific application of this embodiment is:

in the circuit shown in fig. 2, the first resistor, the second resistor and the third resistor are all well resistors, the square resistors are 5K siemens/sq, the first resistor and the second resistor are 100K, the third resistor is 20K, the reference voltage vref=1.1v, and the aspect ratio of the NMOS switch tube N1 can be selected to be 6um/0.6um. When the first memory cell does not read and write, the voltage of the node A is lower, the voltage of the node VIN is lower, VREF > VIN, and the NMOS switching tube is cut off; when the first memory cell is read and written, the HV voltage can be up to more than 15V, the voltage VIN between the second resistor and the third resistor can reach 1.5V, VIN > VREF through the voltage division of the first resistor, the second resistor and the third resistor, the voltage comparator CMP outputs a high level, the NMOS switch tube is conducted, and the node B signal is pulled down. The voltage at node B is then low even though node a is pulled high multiple times.

When neither memory cell is writing, both GA and GB are low, and the memory cell is not operating. When the left memory cell needs to be written with data (the right memory cell does not operate), the grid level of the NMOS tube GA is changed to be high, the MOS tube is conducted, HV high voltage is transmitted to the node A through the MOS tube, and the voltage of the node A is rapidly increased from low to high, so that abrupt change of the voltage at the point A is formed. Because the two memory units are very similar, the parasitic capacitance Cg of the two memory units cannot be ignored, and the voltage difference at two ends of the capacitor cannot be suddenly changed in a short period according to the electromagnetic principle, the voltage suddenly changed of the node A inevitably leads to the voltage following change of the node B, and the voltage of the node B also instantaneously rises to the voltage similar to HV, so that the misoperation operation of the right memory unit is caused, and the stability and the reliability of data are caused. The detailed waveforms are shown in fig. 3.

In order to prevent the occurrence of the above phenomenon, a high-voltage anti-coupling high-voltage bleeder circuit is designed as shown in fig. 2. The circuit has the functions of: when no writing operation is performed on the two memory cells, the voltage of the node A is low, after the voltage is divided by the resistor network, the voltage of the connection point IN (namely the positive end P of the comparator) of the second resistor and the third resistor is low, the voltage is lower than the reference voltage VREF, the output of the comparator is low, and the switch NMOS tube N1 is IN a cut-off state.

When the left memory cell has a write operation, as shown IN fig. 3, the voltage at the node a is instantaneously raised, the voltage at the connection point IN of the second resistor and the third resistor (i.e., the positive end P of the comparator) is increased by the voltage division of the resistor network, and is higher than the reference voltage VREF, the output voltage of the comparator CMP turns high, the gate of the switch NMOS N1 becomes high level to cause the conduction of the source drain, and the node B is instantaneously pulled low to low level, thus canceling the high voltage coupled by Cg, so that the voltage at the node B is not pulled high, and the right memory cell is protected from being wrongly written.

In the description of the present specification, reference to the terms "one embodiment," "example," "specific example," and the like, means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present patent. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiments or examples. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.

The above-disclosed preferred embodiments of the present patent are provided only to help illustrate the present patent. The preferred embodiments are not exhaustive or to limit the patent to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the patent and the practical application, thereby enabling others skilled in the art to best understand and utilize the patent. This patent is limited only by the claims and the full scope and equivalents thereof.

Claims

1. The utility model provides a high-voltage anti-coupling high-voltage bleeder circuit of memory, includes adjacent non-volatile memory unit first memory cell, second memory cell, node A and node B, be equipped with parasitic capacitance Cg between node A and the node B, its characterized in that: an auxiliary circuit is connected in series between the node A and the node B, the auxiliary circuit comprises a resistor string, a voltage comparator and an NMOS switch tube, the resistor string arranged in the auxiliary circuit is divided into the voltage comparator, the voltage comparator controls the on-off of the NMOS switch tube, the node B is instantly pulled down to a low level, the high voltage coupled with Cg can be weakened, and the right memory cell is protected from being wrongly written;

the input end of the voltage comparator is respectively connected with a resistor string node and a reference voltage end to form a voltage comparison circuit, the output end of the voltage comparator is connected with the grid electrode of the NMOS switching tube to control the on-off of the source electrode and the drain electrode of the NMOS switching tube, and the source electrode and the drain electrode of the NMOS switching tube are respectively connected with the ground wire and the node B;

the width-to-length ratio of the NMOS switch tube is 6um/0.6um.

2. A memory high voltage anti-coupling high voltage bleeder circuit according to claim 1, wherein: the resistor string is provided with a first resistor, a second resistor and a third resistor which are connected in series, the third resistor is an adjustable resistor and is grounded, the connecting end of the third resistor and the second resistor is connected with the positive end of the voltage comparator, and the negative end of the voltage comparator is connected with a reference source to form an open-loop voltage comparator circuit.

3. A memory high voltage anti-coupling high voltage bleeder circuit as defined in claim 2, wherein: the first resistor, the second resistor and the third resistor are well resistors.