CN107204369A - 半导体装置和半导体装置的制造方法 - Google Patents

半导体装置和半导体装置的制造方法 Download PDF

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CN107204369A
CN107204369A CN201710052983.7A CN201710052983A CN107204369A CN 107204369 A CN107204369 A CN 107204369A CN 201710052983 A CN201710052983 A CN 201710052983A CN 107204369 A CN107204369 A CN 107204369A
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interlayer dielectric
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岩谷将伸
内海诚
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Fuji Electric Co Ltd
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Abstract

本发明提供一种半导体装置以及半导体装置的制造方法。该半导体装置不增大接触电阻，不会成为单元间距缩小的障碍，并在形成镍硅化物时，能够防止镍渗入层间绝缘膜。该半导体装置的制造方法在栅极绝缘膜(6)和栅电极(7)上形成层间绝缘膜(8)，将层间绝缘膜(8)开口，形成接触孔。接下来，用氮化钛膜(10)覆盖层间绝缘膜(8)以及通过接触孔而露出的区域(4、5)，通过回蚀刻使氮化钛膜(10)仅残留在栅极绝缘膜(6)和层间绝缘膜(8)的在接触孔露出的端部。接下来，用镍膜覆盖层间绝缘膜(8)以及通过接触孔而露出的区域(4、5)，在去除与层间绝缘膜(8)直接接触的镍膜之后，对镍膜进行加热，形成镍硅化物层(9)。

Description

半导体装置和半导体装置的制造方法
技术领域
本发明涉及一种半导体装置和半导体装置的制造方法。
背景技术
以往，作为功率器件而使用的半导体器件是以使用硅(Si)作为半导体材料的器件为主流。然而，作为带隙比硅宽的宽带隙半导体的碳化硅(SiC)具有导热系数是硅的3倍、最大场强是硅的10倍、电子漂移速度是硅的2倍的物理性质。因此，近年来，SiC作为击穿电压高，低损失，能够在高温下工作的功率器件，对其应用进行了研究。
在SiC器件之中，在功率MOSFET(Metal Oxide Semiconductor Field EffectTransistor：绝缘栅型场效应晶体管)和/或IGBT(Insulated Gate Bipolar Transistor：绝缘栅型双极晶体管)中，为了获得与表面侧的基板的欧姆接触，通常使用镍(Ni)硅化物。其制造方法如下。
首先，在SiC基板形成了所期望的杂质层之后，形成栅极绝缘膜，并在栅极绝缘膜上形成多晶硅的图案。然后，在多晶硅上形成了层间绝缘膜之后，对需要接触的部位通过蚀刻进行开口。接下来，在接触孔底面形成Ni膜，并通过快速热处理形成镍硅化物。
在形成镍硅化物时，如果Ni膜与层间绝缘膜接触，则在快速热处理时，Ni渗入层间绝缘膜而导致绝缘性降低，因此存在通过使用剥离(lift-off)法来避免Ni膜与层间绝缘膜接触的技术(例如，参考专利文献1)。
现有技术文献
专利文献
专利文献1：日本专利第4671314号公报
发明内容
技术问题
然而，专利文献1的方法由于使用湿蚀刻来形成接触孔所以不适于细微化，另外还存在在剥离时附着异物的问题。所以，想到在层间绝缘膜上形成氮化钛(TiN)膜，从而防止Ni渗入层间绝缘膜的方法。具体来说，在接触开口之后，通过反应溅射法(以下简称为溅射)等在SiC基板的整面形成TiN膜，对于接触孔底面的想要硅化的部分通过干蚀刻来将TiN膜开口。接下来，通过溅射或蒸镀，在TiN膜的开口部形成Ni膜，并通过进行快速热处理，来形成镍硅化物。
图9是示出在接触开口之后形成了TiN膜的纵向型MOSFET的结构的剖视图。如图9所示，在接触孔底面将TiN膜开口时，需要预测对准偏差和/或尺寸精度，使TiN膜开口宽度小于接触开口宽度。因此，存在能够形成镍硅化物层9的面积变窄，接触电阻增大这样的问题。另外，由于在接触开口部形成TiN膜开口部，所以存在无法缩小接触开口部，接触开口部成为缩小器件的单元间距(cell pitch)时的障碍这样的问题。
本发明的目的在于，提供一种半导体装置和半导体装置的制造方法，该半导体装置不使接触电阻增大，不会成为单元间距缩小的障碍，并且在形成镍硅化物时，能够防止镍渗入层间绝缘膜。
技术方案
为了解决上述问题，达到本发明的目的，本发明的半导体装置具有以下特征。半导体装置具备：第一导电型的宽带隙半导体基板，包括带隙比硅宽的半导体；和第一导电型的宽带隙半导体堆积层，堆积于上述宽带隙半导体基板的正面，且杂质浓度比上述宽带隙半导体基板的杂质浓度低。另外，半导体装置具备：第二导电型区，选择性地设置于上述宽带隙半导体堆积层的相对于上述宽带隙半导体基板侧为相反侧的表面层；和第一导电型区，选择性地设置于上述第二导电型区内。另外，半导体装置具备：栅极绝缘膜，设置于上述宽带隙半导体堆积层的被上述第二导电型区夹住的部分的表面、以及上述第二导电型区的表面；栅电极，设置于上述栅极绝缘膜上；以及层间绝缘膜，覆盖上述栅电极。另外，半导体装置具备：接触孔，开口于上述层间绝缘膜，且到达上述第二导电型区和上述第一导电型区；镍硅化物层，在上述接触孔的底面与上述第二导电型区和上述第一导电型区接触；表面电极，设置于上述镍硅化物层上；以及背面电极，设置于上述宽带隙半导体基板的背面。另外，上述栅极绝缘膜与上述层间绝缘膜的在上述接触孔露出的端部被氮化钛膜覆盖。
为了解决上述问题，达到本发明的目的，本发明的半导体装置的制造方法具有以下特征。半导体装置的制造方法，首先，在包括带隙比硅宽的半导体的第一导电型的宽带隙半导体基板的正面形成杂质浓度比上述宽带隙半导体基板的杂质浓度低的第一导电型的宽带隙半导体堆积层。接下来，在上述宽带隙半导体堆积层的表面层选择性地形成第二导电型区。接下来，在上述第二导电型区内选择性地形成第一导电型区。接下来，在上述宽带隙半导体堆积层的被上述第二导电型区夹住的部分的表面以及上述第二导电型区的表面形成栅极绝缘膜。接下来，在上述栅极绝缘膜上形成栅电极。接下来，在上述栅极绝缘膜以及上述栅电极上形成层间绝缘膜。接下来，将上述层间绝缘膜开口，形成到达上述第二导电型区和上述第一导电型区的接触孔。接下来，用氮化钛膜覆盖上述层间绝缘膜、以及通过上述接触孔而露出的上述第二导电型区和上述第一导电型区。接下来，通过回蚀刻使上述氮化钛膜仅残留在上述栅极绝缘膜和上述层间绝缘膜的在接触孔露出的端部。接下来，用镍膜覆盖上述层间绝缘膜、以及通过上述接触孔而露出的上述第二导电型区和上述第一导电型区。接下来，去除与上述层间绝缘膜直接接触的上述镍膜。接下来，对上述镍膜进行加热，形成镍硅化物层。接下来，在上述镍硅化物层上形成表面电极。接下来，在上述宽带隙半导体基板的背面形成背面电极。
另外，本发明的半导体装置的制造方法的特征在于，在上述发明中，上述镍膜的去除是通过在上述栅电极旁的平坦部形成抗蚀图案，来去除与上述层间绝缘膜直接接触的上述镍膜。
另外，本发明的半导体装置的制造方法的特征在于，在上述发明中，上述镍膜的去除是将上述抗蚀图案形成为在从上述层间绝缘膜的端部和上述栅极绝缘膜的端部朝向上述栅电极的方向上比用于形成上述接触孔的抗蚀图案大0.2～0.8μm。
根据上述发明，在层间绝缘膜的端部和栅极绝缘膜的端部形成TiN膜，通过TiN膜，能够防止Ni渗入层间绝缘膜。另外，镍硅化物层能够形成于接触孔的整个底面，因此不会使接触电阻增大。具体来说，能够将接触电阻比在接触开口之后形成了TiN膜的图9的纵向型MOSFET，减少大约30％。
另外，由于不需要在接触开口部再次形成TiN膜用的开口部，因此能够缩小接触开口部，并且接触开口部不会成为缩小器件的单元间距时的障碍。
发明效果
根据本发明的半导体装置和半导体装置的制造方法，能够起到不使接触电阻增大，不会成为单元间距缩小的障碍，并且在形成镍硅化物时，能够防止镍渗入层间绝缘膜的效果。
附图说明
图1为示出实施方式的纵向型MOSFET的结构的剖视图。
图2为示出实施方式的纵向型MOSFET的制造过程中的状态的剖视图(之一)。
图3为示出实施方式的纵向型MOSFET的制造过程中的状态的剖视图(之二)。
图4为示出实施方式的纵向型MOSFET的制造过程中的状态的剖视图(之三)。
图5为示出实施方式的纵向型MOSFET的制造过程中的状态的剖视图(之四)。
图6为示出实施方式的纵向型MOSFET的制造过程中的状态的剖视图(之五)。
图7为示出实施方式的纵向型MOSFET的制造过程中的状态的剖视图(之六)。
图8为示出在Ni膜的光刻工序中的抗蚀图案的剖视图。
图9为示出在接触开口之后形成了TiN膜的纵向型MOSFET的结构的剖视图。
符号说明
1：n+型碳化硅基板
2：n-型碳化硅外延层
3：p型沟道层
4：n+型源区
5：p+型接触区
6：栅极绝缘膜
7：栅电极
8：层间绝缘膜
9：镍硅化物层
10：TiN膜
11：源电极
12：背面电极
13：Ni膜
14：抗蚀图案
具体实施方式
以下，参考附图对本发明的半导体装置以及半导体装置的制造方法的优选的实施方式详细地进行说明。在本说明书以及附图中，在前缀有n或p的层和区域中，分别表示电子或空穴为多数载流子。并且，标记于n或p的+和-分别表示杂质浓度比未标记+和-的层或区域的杂质浓度高和低。在包括+和-的n或p的表示相同的情况下表示浓度相近而并不限于浓度相同。应予说明，在以下的实施方式的说明以及附图中，对同样的结构标记相同的符号，并省略重复的说明。
(实施方式)
本发明的半导体装置使用宽带隙半导体而构成。在实施方式中，以纵向型MOSFET为例对使用例如碳化硅作为宽带隙半导体而制作(制造)的碳化硅半导体装置进行说明。图1为示出实施方式的纵向型MOSFET的结构的剖视图。
如图1所示，实施方式的碳化硅半导体装置在n+型碳化硅基板(第一导电型的宽带隙半导体基板)1的第一主表面(正面)堆积有n-型碳化硅外延层(第一导电型的宽带隙半导体堆积层)2。
n+型碳化硅基板1为掺杂了例如氮(N)的碳化硅单晶基板。n-型碳化硅外延层2为杂质浓度比n+型碳化硅基板1的杂质浓度低，且掺杂有例如氮的低浓度n型漂移层。以下，将n+型碳化硅基板1和n-型碳化硅外延层2一起作为碳化硅半导体基体。
在碳化硅半导体基体的正面侧形成有MOS栅(由金属-氧化膜-半导体构成的绝缘栅)结构(元件结构)。具体来说，在n-型碳化硅外延层2的相对于n+型碳化硅基板1为相反侧(碳化硅半导体基体的正面侧)的表面选择性地设置有p型沟道层(第二导电型区)3。
在p型沟道层3的内部，与n-型碳化硅外延层2分离地、选择性地设置有n+型源区4(第一导电型区)。另外，在p型沟道层3内的n+型源区4之间，选择性地设置有与n+型源区4接触的杂质浓度比p型沟道层3高的p+型接触区5。
在n-型碳化硅外延层2的被p型沟道层3夹住的部分的表面以及p型沟道层3的表面隔着栅极绝缘膜6而设置有栅电极7。栅电极7也可以隔着栅极绝缘膜6而设置于n+型源区4的表面。
在碳化硅半导体基体的正面侧，设置有以覆盖栅电极7的方式设置的层间绝缘膜8。在开口于层间绝缘膜8的接触孔设置有与n+型源区4和p+型接触区5接触的镍硅化物层9。另外，镍硅化物层9设置在接触孔的整个底面。隔着镍硅化物层9设置有与n+型源区4和p+型接触区5电连接的源电极11(表面电极)。
层间绝缘膜8和栅极绝缘膜6的在接触孔露出的端部被TiN膜10覆盖。通过TiN膜10能够阻碍形成镍硅化物层9前的Ni膜与层间绝缘膜8接触，并防止镍渗入层间绝缘膜8。
在n+型碳化硅基板1的第二主表面(背面，即碳化硅半导体基体的背面)，隔着镍硅化物层9设置有背面电极12。背面电极12构成漏电极。
(实施方式的纵向型MOSFET的制造方法)
接下来，对实施方式的纵向型MOSFET的制造方法进行说明。图2～图7为示出实施方式的纵向型MOSFET的制造过程中的状态的剖视图。
首先，准备掺杂了氮的n+型碳化硅基板1。接下来，在n+型碳化硅基板1的第一主表面上使掺杂了氮的厚度为15μm的n-型碳化硅外延层2外延生长。至此为止的状态记载于图2。
接下来，在n-型碳化硅外延层2的表面上利用例如抗蚀剂通过光刻技术来形成具有期望的开口部的掩模。并且，将该抗蚀剂作为掩模，通过离子注入法将p型的杂质进行离子注入。由此，在n-型碳化硅外延层2的表面区的一部分形成p型沟道层3。接下来，去除用于形成p型沟道层3的离子注入时所使用的掩模。
接下来，在p型沟道层3的表面上利用例如抗蚀剂通过光刻技术来形成具有期望的开口部的掩模。并且，将该抗蚀剂作为掩模，通过离子注入法将n型的杂质进行离子注入。由此，在p型沟道层3的表面区的一部分形成n+型源区4。接下来，去除用于形成n+型源区4的离子注入时所使用的掩模。
接下来，在p型沟道层3的表面上利用例如抗蚀剂通过光刻技术来形成具有期望的开口部的掩模。并且，将该抗蚀剂作为掩模，通过离子注入法将p型的杂质进行离子注入。由此，在p型沟道层3的表面区的一部分形成p+型接触区5。接下来，去除用于形成p+型接触区5的离子注入时所使用的掩模。
接下来，进行用于使p型沟道层3、n+型源区4和p+型接触区5活性化的热处理(退火)。在此，形成n+型源区4、p+型接触区5的顺序能够进行各种改变。至此为止的状态记载于图3。
接下来，将碳化硅半导体基体的正面侧热氧化，形成栅极绝缘膜6。由此，n-型碳化硅外延层2和在n-型碳化硅外延层2的表面形成的各区域被栅极绝缘膜6覆盖。
接下来，在栅极绝缘膜6上形成例如掺杂多晶硅来作为栅电极7。接下来，对掺杂多晶硅进行图案化并选择性地去除，将掺杂多晶硅残留在n-型碳化硅外延层2的被p型沟道层3夹住的部分的表面以及p型沟道层3的表面上。这时，也可以将掺杂多晶硅残留在n+型源区4上。
接下来，以覆盖栅电极7的方式使层间绝缘膜8成膜。接下来，通过对层间绝缘膜8进行图案化并选择性地去除，形成接触孔，使n+型源区4和p+型接触区5露出。在此，由于栅电极7的宽度比栅极绝缘膜6的宽度窄，所以在层间绝缘膜8产生阶梯部15。至此为止的状态记载于图4。
接下来，在碳化硅半导体基体的正面侧使TiN膜10在整面成膜。由此，通过TiN膜10覆盖通过接触孔而露出的n+型源区4的表面(与n+型碳化硅基板1相反一侧的面)和p+型接触区5的表面、通过接触孔而露出的层间绝缘膜8的端部和栅极绝缘膜6的端部、以及层间绝缘膜8的表面(与n+型碳化硅基板1相反一侧的面)。至此为止的状态记载于图5。
接下来，对碳化硅半导体基体的正面侧的整面进行回蚀刻。由此，从通过接触孔而露出的n+型源区4的表面和p+型接触区5的表面、以及层间绝缘膜8的表面去除TiN膜10。也就是说，在通过接触孔而露出的层间绝缘膜8的端部以及栅极绝缘膜6的端部残留TiN膜10作为隔离物(spacer)。这时，也可以在层间绝缘膜8的阶梯部15残留TiN膜10。至此为止的状态记载于图6。
接下来，在碳化硅半导体基体的正面侧使Ni膜13在整面成膜。由此，通过Ni膜13覆盖通过接触孔而露出的n+型源区4的表面和p+型接触区5的表面、被TiN膜10覆盖的层间绝缘膜8的端部和栅极绝缘膜6的端部、以及层间绝缘膜8的表面。
接下来，利用光刻工序去除与层间绝缘膜8直接接触的Ni膜13。这是因为如果形成Ni膜13与层间绝缘膜8接触的状态的图案，则在之后的加热处理中会发生镍向层间绝缘膜8的渗入，层间绝缘膜8的绝缘性降低，而成为短路故障的原因。通过该去除，Ni膜13被残留在通过接触孔而露出的n+型源区4的表面和p+型接触区5的表面、以及被TiN膜10覆盖的层间绝缘膜8的端部和栅极绝缘膜6的端部。至此为止的状态记载于图7。
然而，该光刻工序是通过湿蚀刻而进行图案形成，因此根据加入侧蚀刻(sideetching)以及从抗蚀剂与Ni膜13的界面进行蚀刻等理由，尺寸的控制难以进行。
因此，在实施方式中，在栅电极7旁的平坦部16形成抗蚀图案。在此，平坦部16是指比接触孔高一级的TiN膜10的上表面以及层间绝缘膜8的端部上表面。由此，能够控制性良好地在通过接触孔而露出的n+型源区4的表面和p+型接触区5的表面、以及层间绝缘膜8的端部和栅极绝缘膜6的端部形成Ni膜13的图案。也就是说，形成Ni膜13不与层间绝缘膜8接触的状态的图案。
在此，图8为示出在Ni膜的光刻工序中的抗蚀图案14的剖视图。该光刻工序中的抗蚀图案14形成为在栅电极7的方向上比用于形成接触孔的抗蚀图案大0.2～0.8μm。具体来说，如图8所示，形成从层间绝缘膜8的端部和栅极绝缘膜6的端部起向栅电极7的方向大0.2～0.8μm的5.4～7.0μm的抗蚀图案14。即使比较大地形成抗蚀图案14，由于进行湿蚀刻，所以蚀刻后图案变窄。通过实验确认了如果在平坦部16预先形成抗蚀图案14的端部，则Ni膜13在层间绝缘膜8上被蚀刻，仅在接触孔残留Ni膜13。
接下来，使Ni膜13也在碳化硅半导体基体的背面侧整面成膜，并通过烧结(sintering)(热处理)使碳化硅半导体部(n+型碳化硅基板1、n+型源区4和p+型接触区5)与Ni膜13反应形成镍硅化物层9，由此与碳化硅半导体部形成欧姆接触。应予说明，也可以在镍硅化物层9形成之后增加通过湿蚀刻来去除未反応的Ni的工序。最后，通过使在表面和背面成为电极的金属膜成膜，来完成图1所示的MOSFET。
如以上说明，根据实施方式的半导体装置，在层间绝缘膜的端部和栅极绝缘膜的端部形成TiN膜，通过TiN膜，能够防止Ni渗入层间绝缘膜。另外，由于镍硅化物层能够形成于接触孔的整个底面，因此不会使接触电阻增大。具体来说，能够将接触电阻比在接触开口之后形成了TiN膜的图9的纵向型MOSFET，减少大约30％。
另外，由于不需要在接触开口部再次形成TiN膜用的开口部，因此能够缩小接触开口部，并且接触开口部不会成为缩小器件的单元间距时的障碍。
另外，根据实施方式的半导体装置的制造方法，通过5.4～7.0μm的抗蚀图案14形成了大致相同的Ni图案。在具有层间绝缘膜阶梯和/或接触孔阶梯的状态下，侧蚀刻的加入方法与平坦面的光刻不同，平坦面的光刻能够控制性良好地形成图案，在缩小单元间距时有利。
以上，在本发明中，以在利用碳化硅形成的碳化硅基板的第一主表面上构成了MOS栅结构的情况为例进行了说明，但并不限于此，能够对宽带隙半导体的种类(例如氮化镓(GaN)等)、基板主表面的面方位等进行各种改变。另外，在本发明中，在各实施方式中将第一导电型设为了n型，将第二导电型设为了p型，但即使将第一导电型设为p型，将第二导电型设为n型本发明也同样成立。
产业上的可利用性
如上所述，本发明的半导体装置以及半导体装置的制造方法对使用于电力转换装置和/或各种工业用机器等的电源装置等的高耐圧半导体装置有用。

Claims (4)

1.一种半导体装置，其特征在于，具备：
第一导电型的宽带隙半导体基板，包括带隙比硅宽的半导体；
第一导电型的宽带隙半导体堆积层，堆积于所述宽带隙半导体基板的正面，且杂质浓度比所述宽带隙半导体基板的杂质浓度低；
第二导电型区，选择性地设置于所述宽带隙半导体堆积层的相对于所述宽带隙半导体基板侧为相反侧的表面层；
第一导电型区，选择性地设置于所述第二导电型区内；
栅极绝缘膜，设置于所述宽带隙半导体堆积层的被所述第二导电型区夹住的部分的表面、以及所述第二导电型区的表面；
栅电极，设置于所述栅极绝缘膜上；
层间绝缘膜，覆盖所述栅电极；
接触孔，开口于所述层间绝缘膜，且到达所述第二导电型区和所述第一导电型区；
镍硅化物层，在所述接触孔的底面与所述第二导电型区和所述第一导电型区接触；
表面电极，设置于所述镍硅化物层上；以及
背面电极，设置于所述宽带隙半导体基板的背面，
其中，所述栅极绝缘膜与所述层间绝缘膜的在所述接触孔露出的端部被氮化钛膜覆盖。
2.一种半导体装置的制造方法，其特征在于，包括：
在包括带隙比硅宽的半导体的第一导电型的宽带隙半导体基板的正面形成杂质浓度比所述宽带隙半导体基板的杂质浓度低的第一导电型的宽带隙半导体堆积层的工序；
在所述宽带隙半导体堆积层的表面层选择性地形成第二导电型区的工序；
在所述第二导电型区内选择性地形成第一导电型区的工序；
在所述宽带隙半导体堆积层的被所述第二导电型区夹住的部分的表面以及所述第二导电型区的表面形成栅极绝缘膜的工序；
在所述栅极绝缘膜上形成栅电极的工序；
在所述栅极绝缘膜以及所述栅电极上形成层间绝缘膜的工序；
将所述层间绝缘膜开口，形成到达所述第二导电型区和所述第一导电型区的接触孔的工序；
用氮化钛膜覆盖所述层间绝缘膜、以及通过所述接触孔而露出的所述第二导电型区和所述第一导电型区的工序；
通过回蚀刻使所述氮化钛膜仅残留在所述栅极绝缘膜和所述层间绝缘膜的在接触孔露出的端部的工序；
用镍膜覆盖所述层间绝缘膜、以及通过所述接触孔而露出的所述第二导电型区和所述第一导电型区的工序；
去除与所述层间绝缘膜直接接触的所述镍膜的工序；
对所述镍膜进行加热，形成镍硅化物层的工序；
在所述镍硅化物层上形成表面电极的工序；以及
在所述宽带隙半导体基板的背面形成背面电极的工序。
3.根据权利要求2所述的半导体装置的制造方法，其特征在于，去除所述镍膜的工序中，通过在所述栅电极旁的平坦部形成抗蚀图案，来去除与所述层间绝缘膜直接接触的所述镍膜。
4.根据权利要求3所述的半导体装置的制造方法，其特征在于，去除所述镍膜的工序中，将所述抗蚀图案形成为在从所述层间绝缘膜的端部和所述栅极绝缘膜的端部朝向所述栅电极的方向上比用于形成所述接触孔的抗蚀图案大0.2～0.8μm。
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