CN107202977B - Comprehensive processing system based on VPX platform and software design method - Google Patents

Abstract

The invention discloses a comprehensive processing system based on a VPX platform and a software design method, comprising a plurality of slotsThe system is a master-slave board framework based on a standard VPX bus, and comprises a mother board and a daughter board, wherein the mother board is a switching interface board, the daughter board is an expansion interface board, the mother board and the daughter board are connected through an XMC connector, and the mother board and the daughter board are communicated through an X4SRIO bus; the plurality of slots can be used for inserting a plurality of other board cards, and the backboard realizes communication between the motherboard and the daughter board in the integrated processing system and other board cards; the motherboard and the daughter board are provided with dual cores of ARM Cortex^TMThe processor PS of A9 runs the VxWorks real-time operating system. The comprehensive processing system has rich expansion capability, can meet the application requirements of different scenes by replacing daughter boards with different functions, has strong flexibility and wide application range, namely the module realizes shelf-based, and can quickly build the comprehensive processing system aiming at the specific guidance application background according to the application requirements.

Description

Comprehensive processing system based on VPX platform and software design method

Technical Field

The invention belongs to the technical field of digital signal processing, and particularly relates to a comprehensive processing system based on a VPX platform and a software design method.

Background

With the continuous change of the requirements of the work task and the work environment of the precise guidance aircraft system, the requirements on the generalization, the miniaturization and the expandability of the comprehensive processing systems of different guidance systems are more and more urgent.

The traditional comprehensive processing system is realized by adopting a DSP + FPGA architecture, the FPGA mainly completes interface and time sequence control, and the DSP mainly completes flow control and complex algorithm realization. The layout and wiring of the main processing chip of the card and the data interaction process are relatively complex. When the DSP performs multi-task management, a large number of interrupt registers need to be arranged, and the task scheduling is inflexible and poor in real-time performance. The comprehensive processing system is usually designed according to the application requirements of a certain specific guidance system, the hardware cost of the system architecture is relatively high, and the adaptability and the expandability of the application environment are poor.

VPX is a next generation advanced computing platform standard which is established by VITA organization and used for meeting the requirements of high reliability and high bandwidth in severe environment, high-speed serial buses such as SRIO, PCI Express, Fobre Channel, InfiniBand, Hyper-transport, 10Gb Ethernet and the like are defined among modules, and the transmission rate is as high as 30Gb dual-core ARM Cortex^TMThe processor PS of A9 and the super-strong data processing ability, therefore, the general ruggedized computer based on the VPX framework is very suitable for the data processing system of the accurate guidance aircraft of the new generation.

Disclosure of Invention

Aiming at the defects and shortcomings in the technology, the invention aims to provide a comprehensive processing system based on a VPX platform, which comprises a back plate provided with a plurality of slots and is characterized in that the system is a master-slave plate framework based on a standard VPX bus and comprises a mother plate and a daughter plate, wherein the mother plate is a switching interface plate, the daughter plate is an expansion interface plate, the mother plate and the daughter plate are connected through an XMC connector, and the mother plate and the daughter plate communicate through an X4SRIO bus; the plurality of slots can be used for inserting a plurality of other board cards, and the backboard realizes communication between the motherboard and the daughter board in the integrated processing system and other board cards;

the exchange interface board is based on a motherboard ZYNQ-7000 processor, a motherboard SOC chip, an SRIO exchange chip and an Ethernet exchange chip and is mainly used for realizing data exchange and comprehensive control of the whole system, the motherboard ZYNQ-7000 processor is of an FPGA + ARM architecture, and the motherboard dual-core ARM Cortex^TM-A9 processor PS and motherboard programmable logic PL integrated on a single chip, motherboard dual ARM Cortex implemented via internal AXI bus^TMHigh speed data communication of the a9 processor PS and the motherboard programmable logic PL; the motherboard SOC chip is of an FPGA + ARM architecture, and the main interfaces comprise a motherboard SRIO, an MLVDS, an SGMII, a JTAG, an I2C, a QSPI, a PMBUS, a CAN and a motherboard RS 422;

the expansion interface board is an expansion interface daughter board of the switching module, is based on a daughter board ZYNQ-7000 processor and a daughter board SOC chip, and is mainly used for realizing interface expansion of the switching moduleThe daughter board ZYNQ-7000 processor is of an FPGA + ARM architecture and a daughter board dual-core ARM Cortex^TM-A9 processor PS and daughter board programmable logic PL integrated on a single chip, daughter board dual core ARM Cortex is realized through internal AXI bus^TMHigh speed data communication of the a9 processor PS and daughter board programmable logic PL; the daughter board SOC chip is of an FPGA + ARM architecture, and the main interface comprises a daughter board SRIO, a CameraLink, a 1553B and a daughter board RS 422;

the motherboard ZYNQ-7000 processor and the motherboard and the daughter board dual-core ARMCortex in the daughter board ZYNQ-7000 processor^TMThe software operated by the processor PS and the programmable logic PL of the mother board and the daughter board of A9 carries out task division according to the interface type and the processing capacity, and can carry out multi-task scheduling and dynamic distribution of the computing nodes;

the motherboard and the daughter board are provided with dual cores of ARM Cortex^TMThe processor PS of A9 runs the VxWorks real-time operating system.

Preferably, the motherboard and the daughter board are provided with dual-core ARM Cortex^TMThe A9 processor PS and the software run by the motherboard and daughter board programmable logic PL program different contents to be written into the system according to the interface type and the processing capability of the system to realize the system reconfiguration as required.

Optionally, the comprehensive processing system is further connected with a general signal processing board through the multi-slot back board, and is externally connected with an optical detector through the CameraLink interface to construct an optical guidance system for comprehensive processing of optical guidance, so as to realize flow control and signal processing of the complete optical guidance system;

the general signal processing board adopts a processing architecture of a plurality of DSP6678 multi-core processors.

Optionally, the comprehensive processing system is further connected with the multi-channel AD/DA board and the general signal processing board through the multi-slot backplane, and constructs a radar guidance system through an external antenna front end, so as to implement a complete flow control and signal processing of the radar guidance system;

the multichannel AD/DA board integrates a multichannel AD/DA and an FPGA processor.

The software design method of the comprehensive processing system based on the VPX platform,the method is characterized in that the integrated processing system software divides tasks according to the interface type and the processing capacity of the integrated processing system, performs multi-task scheduling and dynamic distribution of computing nodes, performs complex flow control, and combines the resource use condition of the programmable logic PL of the mother board and the daughter board and the dual-core ARM Cortex of the mother board and the daughter board^TMThe processing capability of the processor PS A9 divides the algorithm into different sub-modules, and the sub-modules are operated cooperatively by the processor PS and the processor PS through a motherboard and a daughter board dual-core ARM Cortex^TMThe interaction of the intermediate results of the high-speed interfaces between the A9 processor PS and the programmable logic PLs of the mother board and the daughter board meets the requirements of the real-time performance of the comprehensive processing system, reduces the difficulty of algorithm implementation and improves the processing performance.

Specifically, the integrated processing system software includes a communication module for realizing and controlling the system, an antenna front end communication module, a telemetry system communication module, a data recording device communication module, and other board cards communication modules, and also includes tasks for realizing command analysis and response, and overall flow control:

the control system communication module is used for communicating the comprehensive processing system software with the control system through a universal serial bus; the daughter board programmable logic PL mainly realizes the bus interface control task and the dual core ARM Cortex of the daughter board and the chip^TM-data interaction between a9 processors PS; daughter board dual core ARM Cortex^TMThe A9 processor PS mainly realizes data format conversion and data interaction with the on-chip daughter board programmable logic PL data, encapsulates received effective data into SRIO messages with the length specified by a protocol and sends the SRIO messages to the motherboard ZYNQ-7000 processor, extracts data packets in the SRIO messages sent by the motherboard ZYNQ-7000 processor and sends the data packets to a control system through the on-chip daughter board programmable logic PL control interface chip; the motherboard programmable logic PL mainly realizes the control task of the SRIO bus interface, the motherboard programmable logic PL and the motherboard dual-core ARM Cortex^TM-data interaction between a9 processors PS; motherboard dual-core ARM Cortex^TMThe A9 processor PS mainly implements instructionsAnalyzing and executing template data loading, real-time parameter resolving and distributing, communication flow control and finishing information synthesis and instruction response workflow according to an instruction analysis result; mother board double-core ARMCortex^TMThe processor PS of A9 finishes the data interaction with on-chip mother board programmable logic PL at the same time, pack the order response message into SRIO message of the agreement regulation length, send to daughter board ZYNQ-7000 processor through on-chip mother board programmable logic PL;

the antenna front end communication module, the comprehensive processing system software and the antenna front end adopt universal serial bus communication and an HDLC communication protocol; motherboard dual-core ARM Cortex^TMThe A9 processor PS communicates with the antenna front end according to the overall flow control and the command analysis result, sends the command frame to the antenna front end through the on-chip motherboard programmable logic PL, extracts effective information from the received command response frame returned by the antenna front end, completes the overall flow control according to the working time sequence of the antenna front end, and after the flow execution is completed, synthesizes the information and packs the information into a bus message to return to the control system; the programmable logic PL of the motherboard realizes the HDLC protocol of communication with the front end of the antenna, and the dual cores ARM Cortex of the motherboard^TMThe command frame sent by the PS of the A9 processor is sent to the antenna front end according to the HDLC protocol, and the command response frame returned by the antenna front end according to the HDLC protocol is sent to the dual-core ARM Cortex of the motherboard through the internal interface^TM-a9 processor PS making data frame validity decisions and information extraction;

the remote measuring system communication module is used for communicating the comprehensive processing system software with the remote measuring system through a universal serial bus and adopting an HDLC communication protocol; the daughter board programmable logic PL realizes an HDLC protocol for communicating with the telemetering system, and receives and analyzes a request frame sent by the telemetering system at regular time according to the HDLC protocol; the programmable logic PL of the daughter board passes through the daughter board dual core ARM Cortex^TMThe PS processing of the A9 processor obtains data needing to be transmitted by telemetering and down, time marking information is printed on the data, and then the data is transmitted to a telemetering system according to an HDLC protocol, if the daughter board and the daughter board are dual-core ARM Cortex^TMThe A9 processor PS processes the data which does not need to be downloaded, and then the telemetry data frame is downloaded to be an all-zero frame only containing the time mark information;

a module for communicating with a data recording device,the integrated processing system software and the data recording device communicate through the Ethernet and adopt a UDP communication protocol; the RGMII interface of the motherboard ZYNQ-7000 processor realizes the conversion of the SGMII interface and the RGMII interface through the PHY chip and then is connected with the Ethernet switching chip; motherboard dual-core ARM Cortex^TMThe A9 processor PS realizes the communication with the data recording device after the route of the Ethernet switching chip; after the comprehensive processing system is in power distribution work, when Doorbell sent by other board cards is received to inform that one frame of recording data is sent, the motherboard dual-core ARM Cortex^TMThe A9 processor PS controls the DDR3 cached recording data and corresponding auxiliary information, and commands sent by the control system are sent to the data recording device according to a UDP protocol;

the integrated processing system running by the integrated processing system software is connected with other board cards through a back plate of the VPX platform, and the integrated processing system is communicated with the other board cards and the other board cards through SRIO high-speed buses; motherboard dual-core ARM Cortex^TMThe A9 processor PS mainly completes SRIO bus data storage space allocation, and reads data from the DDR3 according to the SRIO address and the Doorbell type of the received data to complete data forwarding and data processing; the programmable logic PL of the motherboard mainly completes the control of the SRIO interface and the dual core ARM Cortex of the motherboard^TMData interaction of processor PS according to motherboard dual core ARM Cortex, A9^TMThe address space allocated by the a9 processor PS controls the store of received data in the external DDR3 memory; motherboard dual-core ARM Cortex^TMThe A9 processor PS sends data to be sent to other corresponding boards to the SRIO switch chip via the motherboard programmable logic PL according to the overall process control, and the SRIO switch chip routes the data according to the source ID and the target ID and then sends the data to other corresponding boards via the VPX platform backplane.

Optionally, the integrated processing system software further comprises an image compression module, the motherboard ZYNQ-7000 processor judges to transmit the received image data sent by other board cards to the daughter board ZYNQ-7000 processor through the SRIO bus according to the SRIO address and the DoorBell type of the received data; daughter board dual core ARM Cortex^TMThe a9 processor PS performs a blocking process on the received image data, and after the completion of the image blocking processSending the image data block to the daughter board programmable logic PL according to an interrupt request sent by the on-chip daughter board programmable logic PL to perform second-order Daubechies5/3 lifting wavelet transformation; LH1 and HL1 sub-bands formed by first-order wavelet transform and HH2, LH2, HL2 and LL2 sub-bands formed by second-order wavelet transform are subjected to quantization processing by using different quantization step sizes and then are sent to the on-chip and the daughter-board dual-core ARM Cortex^TM-a9 processor PS; daughter board dual core ARM Cortex^TMThe a9 processor PS encodes each sub-band wavelet coefficient using the SPIHT algorithm.

Optionally, the integrated processing system software further includes a data framing module and a daughter board dual core ARM Cortex^TMThe A9 processor PS packs the image compression code stream data into a compression code stream data frame by adding a compression code stream frame header, an image block number, SPIHT algorithm parameters, a code stream length and code stream data; adding frame header and frame number information to inertial navigation data received in an imaging period and packaging the inertial navigation data into inertial navigation data frames; and adding frame header and data length information into received algorithm operation intermediate results, system key state information, other auxiliary information and the like sent by other board cards, and packaging the obtained result into a state detection data frame.

Optionally, the integrated processing system software further comprises a BIT detection module.

The invention relates to a comprehensive processing system based on a VPX platform, which is a mother board and daughter board framework based on a standard VPX bus, wherein a mother board is an exchange interface board, a daughter board is an expansion interface board, the mother board is based on a mother board ZYNQ-7000 processor, a mother board SOC chip, an SRIO exchange chip and an Ethernet exchange chip, and the daughter board is based on a daughter board ZYNQ-7000 processor and a daughter board SOC chip; the motherboard and daughter board ZYNQ-7000 processor is a Xilinx new generation SOC chip, dual-core ARM Cortex^TM-A9 processor PS and Xilinx programmable logic PL integrated on a single chip, implementing dual core ARM CORTEX via an internal AXI bus^TMHigh-speed data communication of the processor PS and the programmable logic PL (analog-to-digital) A9 is realized, namely, the daughter board is an interface extension of the system, the system has rich extension capability, can meet the application requirements of different scenes by replacing daughter boards with different functions, can realize system reconstruction by programming different software, has strong flexibility and wide application rangeNamely, the module realizes goods shelves, and a comprehensive processing system aiming at a specific guidance application background can be quickly built according to application requirements. For example, the comprehensive processing system and the general signal processing board form a comprehensive signal processing system of the optical guidance system, and the CameraLink interface is externally connected with the optical detector to form an optical guidance system, so that the application requirements of the current optical guidance system precision guidance aircraft platform can be met.

The system and the software design method of the invention have good universality. The method is based on a general VPX platform, adopts a modular design, and specifically comprises an antenna front-end communication module, a control system communication module, a telemetering system communication module, a data recording device communication module, other board card communication modules, an image compression module, a data framing module and the like.

The system and the software design method have high operation efficiency. The comprehensive processing system software runs on the ZYNQ-7000 processor of the mother board and the daughter board, and the ZYNQ-7000 processor adopts a dual-core ARM + FPGA architecture, so that the advantages of the two processors are integrated. The dual-core ARM scheduling and computing capability based on the VxWorks real-time operating system is strong, and the dual-core ARM scheduling and computing system mainly achieves the functions of command analysis, overall flow control, image blocking, SPIHT coding operation, data framing and the like. The FPGA interface control and real-time operation capability is strong, the functions of interface control, data format conversion, HDLC protocol, second-order Daubechies5/3 lifting wavelet transformation and the like are mainly completed, the advantages of a processor core framework are fully exerted, software can be developed for collaborative design, data are interacted in a mother-daughter board or ZYNQ-7000 processor (chip), and the software operation efficiency is high.

The system and the software design method have high reliability. The software runs on the ZYNQ-7000 processor of the exchange interface board and the expansion interface board, the software acquires data through the external interface and then completes data analysis, data transmission, intermediate result interaction and the like in the chip, the mother board and the daughter board are positioned in the same metal structure assembly, and the data interaction among the board cards, among different board cards, and between the mother board assembly and the daughter board assembly and other board cards is relatively reduced, so that the probability of being interfered by electromagnetic environment is reduced, and the reliability and the anti-interference capability of software execution are effectively improved.

The system and the software design method of the invention have small volume. The expansion interface board and the exchange interface board are in a mother board and daughter board structure, the mother board and the daughter board are connected through an XMC component and are mixed and assembled into the same component. The mother board and the daughter board mainly carry out information interaction through an SRIO bus, all functional modules of the integrated information processing software run in ZYNQ-70000 processors (chips) of the daughter board and the mother board respectively, and the assembly has the advantages of small hardware volume, simple structure, high integration level and convenience in maintenance.

The system and the software design method of the invention provide an image compression algorithm implementation method based on a ZYNQ-7000 processor, the image compression algorithm is divided in a modularization way, and the sub-modules after the division are respectively arranged in a programmable logic PL and a dual-core ARM CORTEX^TM-a9 processor PS. The programmable logic PL realizes two-level Daubechies5/3 lifting wavelet transformation, and completes multi-level wavelet transformation through multiplexing of the prediction and update modules and time-sharing multiplexing of the row/column transformation modules, thereby realizing software modular design and saving hardware resources. Dual-core ARM CORTEX^TMThe A9 processor PS performs image blocking and SPIHT coding operation, and the compressed code stream data and the algorithm parameters are downloaded through a telemetering system after being coded. Dual-core ARM CORTEX^TMThe a9 processor PS and the programmable logic PL cooperate to reduce the complexity of the algorithm implementation while meeting the image compression real-time requirements.

The system and the software design method provided by the invention have various types of interfaces and perform data interaction with a plurality of systems, the efficient real-time multi-task kernel of the VxWorks real-time operating system is utilized to complete multi-task real-time scheduling so as to realize complex overall flow control, and the high efficiency and response timeliness of multi-task scheduling such as template data loading, real-time parameter resolving and distribution, high-capacity high-speed data transmission, command analysis, control and antenna front end and other board cards of a processor, information synthesis and command response are ensured by reasonably setting the priority of tasks.

Drawings

FIG. 1 is a diagram of a hardware platform and interfaces of an integrated processing system according to an embodiment of the present invention;

FIG. 2 is a block diagram of a motherboard/daughter board ZYNQ-7000 processor system architecture according to an embodiment of the present invention;

fig. 3 is a 1553B data packing format according to an embodiment of the present invention;

FIG. 4 is a 1553B command parsing flowchart provided by the embodiment of the invention;

FIG. 5 is a block diagram of an implementation of an HDLC protocol according to an embodiment of the present invention;

fig. 6 is a simplified diagram of a communication process with an antenna front end according to an embodiment of the present invention;

FIG. 7 is a diagram illustrating a second-order wavelet transform according to an embodiment of the present invention;

FIG. 8 is a simplified second-order Daubechies5/3 wavelet transform flow diagram according to an embodiment of the present invention;

Detailed Description

The following further describes embodiments of the present invention with reference to the drawings. It should be noted that the description of the embodiments is provided to help understanding of the present invention, but the present invention is not limited thereto.

Example one

FIG. 1 is a diagram of the hardware platform and interface of the integrated processing system of the present invention. A mother board exchange interface board and a daughter board expansion interface board are used as carriers by depending on a general VPX platform (namely a VPX processor), two board cards are respectively provided with a ZYNQ-7000 series processor, and the system architecture of the mother board and the daughter board ZYNQ-7000 processors is shown in figure 2. The most important characteristic of the ZYNQ-7000 processor is that a dual-core ARM Cortex is adopted^TMThe-a 9 processor PS and the Xilinx7 programmable logic PL are integrated on a single chip. Thus, the ARM processing system is perfectly integrated with the Xilinx7 series of programmable logic, allowing the user to create unique and powerful designs.

Dual-core ARM CORTEX of ZYNQ-7000 processor system^TMThe A9 processor PS part includes on-chip memory, external memory interfaces, and a rich set of I/O peripherals in addition to the dual-core A9 core. The peripheral devices mainly comprise a DDR3 particle memory, a JTAG interface, a UART interface, a USB interface and a CAN busInterfaces, I2C bus interface, SPI bus interface, XADC interface, TF card slot, ethernet interface, and the like. The PL part provides better flexibility and scalability, and can perform real-time signal processing and high-speed signal transmission according to the logic customized by the user.

The comprehensive processing system based on the VPX platform comprises a back panel provided with a plurality of slots, is a mother board and a daughter board framework based on a standard VPX bus, and comprises a mother board and a daughter board, wherein the mother board is a switching interface board, the daughter board is an expansion interface board, the mother board is connected with the daughter board through an XMC connector, and the mother board is communicated with the daughter board through an X4SRIO bus; the plurality of slots can be used for inserting a plurality of other board cards, and the backboard realizes communication between the motherboard and the daughter board in the integrated processing system and other board cards;

the switching interface board is based on a motherboard ZYNQ-7000 processor, a motherboard SOC chip, an SRIO switching chip and an Ethernet switching chip and is mainly used for realizing data exchange and comprehensive control of the whole system, the motherboard ZYNQ-7000 processor is of an FPGA + ARM architecture, and the motherboard dual-core ARM Cortex^TM-A9 processor PS and motherboard programmable logic PL integrated on a single chip, motherboard dual ARM Cortex implemented via internal AXI bus^TMHigh speed data communication of the a9 processor PS and the motherboard programmable logic PL; the motherboard SOC chip is an FPGA + ARM architecture integrated inside, and the main interfaces comprise a motherboard SRIO, an MLVDS, an SGMII, a JTAG, an I2C, a QSPI, a PMBUS, a CAN and a motherboard RS 422;

the expansion interface board is an expansion interface daughter board of the switching module, the board card is based on a daughter board ZYNQ-7000 processor and a daughter board SOC chip and is mainly used for realizing interface expansion of the switching module, the daughter board ZYNQ-7000 processor is of an FPGA + ARM architecture, and the daughter board dual-core ARM Cortex^TMDaughter board programmable logic PL of A9 processor PS and Xilinx integrated on a single chip, daughter board dual core ARM Cortex realized by internal AXI bus^TMHigh speed data communication of the a9 processor PS and daughter board programmable logic PL; the daughter board SOC chip is an internally integrated FPGA + ARM architecture, and the main interface comprises a daughter board SRIO, a CameraLink, a 1553B and a daughter board RS 422;

motherboard and daughter board dual-core ARM Cortex in motherboard ZYNQ-7000 processor and daughter board ZYNQ-7000 processor^TMSoftware operated by a processor PS and a motherboard and a daughter board programmable logic PL of the Xilinx A9 performs task division according to interface types and processing capacity, and can perform multi-task scheduling and dynamic distribution of computing nodes;

dual-core ARM Cortex for motherboard and daughter board^TMThe processor PS of A9 runs the VxWorks real-time operating system.

Dual-core ARM Cortex for motherboard and daughter board^TMThe A9 processor PS and the software run by the motherboard and daughter board programmable logic PL program different contents to be written into the system according to the interface type and the processing capability of the system to realize the system reconfiguration as required.

The comprehensive processing system is also connected with a general signal processing board through the multi-slot back board, and is externally connected with an optical detector through the CameraLink interface to construct an optical guidance system for comprehensive processing of optical guidance, so that the flow control and signal processing of the complete optical guidance system are realized. Can meet the application requirement of the prior optical guidance system precision guidance aircraft platform)

The universal signal processing board adopts a processing architecture of a plurality of DSP6678 multi-core processors, and meets the capability requirement of high-speed signal processing at present.

The comprehensive processing system is also connected with the multi-channel AD/DA board and the general signal processing board through the multi-slot back board, and a radar guidance system is constructed through the front end of an external antenna, so that the complete flow control and signal processing of the radar guidance system are realized, and the application requirement of the current radar guidance system accurate guidance aircraft platform can be met. The multi-channel AD/DA board integrates a multi-channel AD/DA and FPGA processor, and meets the capacity requirement of high-speed signal processing at present.

Example two

In the software design method of the integrated processing system based on the VPX platform according to the first embodiment, the integrated processing system software designed by the method performs task division and task management according to the interface type and the processing capability of the integrated processing system, and performs multi-task scheduling and dynamic allocation of computing nodesThe method can perform complicated flow control, and the parallelizable operation part of the complicated algorithm can combine the resource use condition of the programmable logic PL of the mother board and the daughter board and the dual-core ARMCortex of the mother board and the daughter board^TMThe processing capability of the processor PS A9 divides the algorithm into different sub-modules, and the sub-modules are operated cooperatively by the processor PS and the processor PS through a motherboard and a daughter board dual-core ARM Cortex^TMThe interaction of the intermediate results of the high-speed interfaces between the A9 processor PS and the programmable logic PLs of the mother board and the daughter board meets the requirements of the real-time performance of the comprehensive processing system, reduces the difficulty of algorithm implementation and improves the processing performance.

The software of the comprehensive processing system comprises a realization and control system, an antenna front end (a phased array front end in the embodiment), a telemetering system, a data recording device and other board cards of a VPX processor, and also comprises tasks of realizing command analysis and response and overall flow control, and correspondingly, the software of the comprehensive processing system comprises a communication module with the control system, a communication module with the antenna front end, a communication module with the telemetering system, a communication module with the data recording device and a communication module with other board cards:

the control system communication module is used for communicating the comprehensive processing system software with the control system through a universal serial bus; the daughter board programmable logic PL mainly realizes the bus interface control task and the dual core ARM Cortex of the daughter board and the chip^TM-data interaction between a9 processors PS; daughter board dual core ARM Cortex^TMThe A9 processor PS mainly realizes data format conversion and PL data interaction with the on-chip daughter board programmable logic, encapsulates received effective data into SRIO messages with a protocol specified length (80 bytes long in the embodiment) and sends the SRIO messages to the motherboard ZYNQ-7000 processor, extracts data packets in the SRIO messages sent by the motherboard ZYNQ-7000 processor and sends the data packets to a control system through the on-chip daughter board programmable logic PL control interface chip; the motherboard programmable logic PL mainly realizes the control task of the SRIO bus interface, the motherboard programmable logic PL and the motherboard dual-core ARM Cortex^TM-data interaction between a9 processors PS; motherboard dual-core ARM Cortex^TMThe A9 processor PS mainly realizes instruction analysis and executes template data loading, real-time parameter resolving and distributing according to the instruction analysis result, and communication flow program controlCompleting information synthesis and instruction response work flow; motherboard dual-core ARM Cortex^TMThe processor PS of A9 finishes the data interaction with on-chip mother board programmable logic PL at the same time, pack the order response message into SRIO message of the agreement regulation length, send to daughter board ZYNQ-7000 processor through on-chip mother board programmable logic PL;

the antenna front end communication module, the comprehensive processing system software and the antenna front end adopt universal serial bus communication and an HDLC communication protocol; motherboard dual-core ARM Cortex^TMThe A9 processor PS communicates with the antenna front end according to the overall flow control and the command analysis result, sends the command frame to the antenna front end through the on-chip motherboard programmable logic PL, extracts effective information from the received command response frame returned by the antenna front end, completes the overall flow control according to the working time sequence of the antenna front end, and after the flow execution is completed, synthesizes the information and packs the information into a bus message to return to the control system; the programmable logic PL of the motherboard realizes the HDLC protocol of communication with the front end of the antenna, and the dual cores ARM Cortex of the motherboard^TMThe command frame sent by the PS of the A9 processor is sent to the antenna front end according to the HDLC protocol, and the command response frame returned by the antenna front end according to the HDLC protocol is sent to the dual-core ARM Cortex of the motherboard through the internal interface^TM-a9 processor PS making data frame validity decisions and information extraction;

the remote measuring system communication module is used for communicating the comprehensive processing system software with the remote measuring system through a universal serial bus and adopting an HDLC communication protocol; the daughter board programmable logic PL realizes an HDLC protocol for communicating with the telemetering system, and receives and analyzes a request frame sent by the telemetering system at regular time according to the HDLC protocol; the programmable logic PL of the daughter board passes through the daughter board dual core ARM Cortex^TMThe PS processing of the A9 processor obtains data needing to be transmitted by telemetering and down, time marking information is printed on the data, and then the data is transmitted to a telemetering system according to an HDLC protocol, if the daughter board and the daughter board are dual-core ARM Cortex^TMThe A9 processor PS processes the data which does not need to be downloaded, and then the telemetry data frame is downloaded to be an all-zero frame only containing the time mark information;

the integrated processing system software and the data recording device communicate through the Ethernet and adopt a UDP communication protocol; mother board ZYThe NQ-7000 processor RGMII interface (the interface is an intermediate interface, not an external interface) realizes the conversion of the SGMII and RGMII interfaces through the PHY chip and then is connected with the Ethernet switching chip; mother board double-core ARMCortex^TMThe A9 processor PS realizes the communication with the data recording device after the route of the Ethernet switching chip; after the comprehensive processing system is in power distribution work, when Doorbell sent by other board cards is received to inform that one frame of recording data is sent, the motherboard dual-core ARM Cortex^TMThe A9 processor PS controls the DDR3 cached recording data and corresponding auxiliary information, and commands sent by the control system are sent to the data recording device according to a UDP protocol;

the integrated processing system running by the integrated processing system software is connected with other board cards through a back plate of the VPX platform, and the integrated processing system is communicated with the other board cards and the other board cards through SRIO high-speed buses; motherboard dual-core ARM Cortex^TMThe A9 processor PS mainly completes SRIO bus data storage space allocation, and reads data from the DDR3 according to the SRIO address and the Doorbell type of the received data to complete data forwarding and data processing; the programmable logic PL of the motherboard mainly completes the control of the SRIO interface and the dual core ARM Cortex of the motherboard^TMData interaction of processor PS according to motherboard dual core ARM Cortex, A9^TMThe address space allocated by the a9 processor PS controls the store of received data in the external DDR3 memory; motherboard dual-core ARM Cortex^TMThe A9 processor PS sends data to be sent to other corresponding boards to the SRIO switch chip via the motherboard programmable logic PL according to the overall process control, and the SRIO switch chip routes the data according to the source ID and the target ID and then sends the data to other corresponding boards via the VPX platform backplane.

The comprehensive processing system software also comprises an image compression module, and the motherboard ZYNQ-7000 processor judges to transmit the received image data sent by other board cards to the daughter board ZYNQ-7000 processor through the SRIO bus according to the SRIO address and Doorbell type of the received data; daughter board dual core ARM Cortex^TMThe A9 processor PS divides the received image data into blocks, and after the image blocks are finished, the image data are sequentially processed according to the interrupt request sent by the on-chip and sub-chip programmable logic PLThe block is sent to daughter board programmable logic PL to carry out second-order Daubechies5/3 lifting wavelet transform; LH1 and HL1 sub-bands formed by first-order wavelet transform and HH2, LH2, HL2 and LL2 sub-bands formed by second-order wavelet transform are subjected to quantization processing by using different quantization step sizes and then are sent to the on-chip and the daughter-board dual-core ARM Cortex^TM-a9 processor PS; daughter board dual core ARM Cortex^TMThe a9 processor PS encodes each sub-band wavelet coefficient using the SPIHT algorithm.

The integrated processing system software also comprises a data framing module and a daughter board dual-core ARM Cortex^TMThe A9 processor PS packs the image compression code stream data into a compression code stream data frame by adding a compression code stream frame header, an image block number, SPIHT algorithm parameters, a code stream length and code stream data; adding frame header and frame number information to inertial navigation data received in an imaging period and packaging the inertial navigation data into inertial navigation data frames; and adding frame header and data length information into received algorithm operation intermediate results, system key state information, other auxiliary information and the like sent by other board cards, and packaging the obtained result into a state detection data frame.

The integrated processing system software also includes a BIT detection module.

Specifically, when the comprehensive processing system is used, the system is initialized after being electrified, and each functional module controls work according to the working flow of the aircraft system. In this embodiment, the integrated processing system is configured, and the BIT detection implementation process and the content (process) of the work executed by the integrated processing system software to implement the functions of the integrated processing system software, the control system communication module, the antenna front-end communication module, the telemetry system communication module, the other board card communication module, the data recording device communication module, the image compression module, and the data framing module are described as follows.

1. Integrated processing system configuration

The comprehensive processing system comprises a switching interface board and an expansion interface board, wherein the expansion interface board and the switching interface board are in a mother board and daughter board structure and are connected through an XMC connector, the mother board, the daughter board and each (functional) board card of the processor are mainly communicated through an X4SRIO bus, and the communication rate is 12.5Gb dual-core ARM Cortex^TMA9 processor PS.

FPGA chip selection of exchange interface boardThe ZYNQ-7000 series chip XC7Z015, the external DDR3 memory and FLASH memory of treater realize 4 ways MLVDS and 1 way LVDS interface through interface chip, and 1 way X4SRIO external interface adopts FPGA's GTP interface to realize. The SRIO switch chip selects 80HC dual-core ARM CORTEX of IDT company^TMThe processor PS1848CRMI of A9, SRIO switch chip can provide 7X 4SRIO, wherein 4 is led out from the P1 port of the VPX connector, 1 is led out from the P2 port of the VPX connector, 1 is led out from the XMC connector, and the rest 1 is communicated with the FPGA. SOC chip processor pass I²The C bus dynamically manages the SRIO node of the switching chip, updates the routing table, and the switching chip completes the switching function of the external 7-path X4 SRIO. The Ethernet exchange chip selects VSC7428XJG of Vitesse company, and can provide 6 groups of SGMII interfaces and 4 groups of MDI interfaces. 5 of the 6 groups of SGMII interfaces are connected through a VPX connector P2 port, and the other group of SGMII interfaces can realize SGMII and RGMII interface conversion through a PHY chip 88E1111 and are connected to the FPGA chip. 3 groups of the 4 groups of MDI interfaces are isolated and connected to the high-speed hybrid connector through a transformer, and the rest groups are isolated and connected to the port P2 of the VPX connector through the transformer. The SOC chip processor can configure the switching chip VSC7428XJG related parameters through the SPI bus.

The FPGA chip of the expansion interface board selects ZYNQ-7000 series chips XC7Z015, a DDR3 memory and a FLASH memory are externally hung on the processor, 1 path of 1553B, 1 path of Camera Link interface and 1 path of RS422 interface are realized through the interface chip, and 1 path of X4SRIO external interface is realized by adopting a GTP interface of the FPGA. The 1553B bus controller selects HT-61843GB of 8357, and a chip contains an independent two-channel 4M 1553B communication control logic; internal 8K word memory; simultaneous MT/RT mode is supported. The CameraLink interface chip selects DS90CR286AMTD and adopts the Base mode. And the RS422 serial port conversion chip selects LTM2881MPY to realize the conversion between LVCMOS level and RS422 level. The board card is provided with 1 RS232 serial port and 1 Ethernet port for debugging.

The SOC chip processors of the exchange interface board and the expansion interface board both adopt an A2F500M3G chip of Microsmi, and the A2F500M3G-1FGG484 chip is internally integrated

Cortex^TM-M3、

3 FPGA, a memory, a comparator, an AD/DA and other related functional circuits, and the chip is divided into 4 parts of a microcontroller subsystem, an FPGA module, an analog interface system, an I/O and a power supply. The SOC chip provides a control platform for the whole board card to complete power supply management and control and system management functions.

BIT detection implementation Process

Dual-core ARM CORTEX of exchange interface board ZYNQ-7000 of comprehensive processing system^TMThe processor PS of A9 receives and analyzes the command sent by the control system through the SRIO bus, and after the current command is judged to be the BIT detection command, the ZYNQ-7000 dual-core ARM CORTEX^TMThe a9 processor PS sends BIT detection commands to the SOC chip on the board through SPI, and the SOC chip sends to the other boards through PMBUS. After receiving BIT detection commands, SOC chips on board cards and other board cards of the integrated processing system start BIT detection on the respective board cards, and software versions, data link states, communication states of various interfaces, FPGA, DSP, AD, DA, DDR3, FLASH and E of the board cards can be obtained in the BIT detection process²The working states of main chips such as PROM, Ethernet exchange chip, SRIO exchange chip, etc. After the BIT detection is finished, the comprehensive processing system collects BIT detection information of the system and BIT detection information of other board cards and sends the collected information to the control system. The state information of each single machine downloaded by the control system can be used for carrying out state management and fault diagnosis and analysis of the system.

3. Working process of communication module with control system

1553B command receiving and processing flow:

step 1: the programmable logic PL of the daughter board ZYNQ-7000 processor receives 1553B messages sent by the control system, and the 1553B messages pass through the programmable logic PL and the dual-core ARM CORTEX^TMInternal port transfer between-A9 processors PS to dual core ARM CORTEX^TMA9 processor PS.

Step 2: dual-core ARM CORTEX^TMThe A9 processor PS pads the 1553B message into an 80-byte SRIO message, which prepends the packet (frame) header "7B8c ', a subaddr which is a sub address to which the 1553B data packet is sent, a data length (namely an effective byte length) ' Len ', a 1553B data packet and the like are packaged, the residual bit of the data frame is filled with zero, the data packaging format is shown in figure 3, the data frame is an outer layer frame header of the package, the 1553B data packet is also provided with a frame header, and the two frame headers are judged to be effective frames. And SRIO Message format information such as a receiving end SRIO port number uDestId, a receiving end MailBox number MailBox, a receiving end Message number letter, and the like is added and then sent to the programmable logic PL, and the programmable logic PL is sent to the mother board ZYNQ-7000 processor through an SRIO switching chip route.

Step 3: the programmable logic PL of the motherboard ZYNQ-7000 processor sends the received SRIO message to the on-chip dual-core ARM CORTEX through the internal port^TMA9 processor PS.

And 4, step 4: dual-core ARM CORTEX^TMThe A9 processor PS runs the VxWorks real-time operating system, registers the SRIO Message callback function Message. When the SRIO Message is received, a software interrupt is generated to execute the Message. And responding to the interrupt by the Message, reading the SRIO interface data, and analyzing the instruction sent by the control system, wherein an instruction analysis flow chart is shown in FIG. 4. The instruction analysis module firstly acquires the semaphore and judges whether a frame header of a command frame in a receiving cache is a protocol frame header, if so, a 1553B command word is acquired from the command frame and CRC (cyclic redundancy check) is carried out, and if correct, corresponding operation is executed according to the content of the command word and a response is returned; if the bus check command is not the bus check command, the corresponding error information is assigned by the gSysErrorStatus.

1553B command response processing flow:

step 1: dual-core ARM CORTEX of motherboard ZYNQ-7000 processor^TMAfter the a9 processor PS completes the instruction parsing and performs the corresponding operation, the command response is executed. It packs the data packet header "7B 8 c", subaddr), data length (Len), 1553B data packet, etc., and the remaining bits of the data frame are padded with zero, and the data packing format is shown in fig. 3. Then adding receiving terminal SRIO port number uDestId and receiving terminal mailbox number Mand sending the SRIO Message format information such as the ailBox and the receiving terminal signal Letter to the programmable logic PL through the internal port.

Step 2: the programmable logic PL routes the SRIO message through the SRIO switch chip to the daughter board ZYNQ-7000 processor.

Step 3: the programmable logic PL of the daughter board ZYNQ-7000 processor receives the SRIO message through the programmable logic PL and the dual-core ARM CORTEX^TMInternal port transfer between-A9 processors PS to dual core ARM CORTEX^TM-a9 processor PS;

and 4, step 4: dual-core ARM CORTEX^TMThe A9 processor PS runs the VxWorks real-time operating system, registers the SRIO Message callback function Message. When the SRIO Message is received, a software interrupt is generated to execute the Message. And the Message responds to the interrupt, reads the SRIO interface data, extracts 1553B Message and the corresponding length and sub-address thereof from the SRIO Message, and sends a command to the sub-address corresponding to the 1553B Message, wherein if the command is in a vector word form, the command corresponds to the position 1 of the vector word.

4. Working process of communication module with antenna front end

The communication with the antenna front end is driven by a command of a control system, when a 1553B command is received and the 1553B command analysis is completed, the communication with the antenna front end is controlled according to the overall flow, the 1553B command receiving and responding processing flow of the module is the same as the processing flow of the communication module of the control system, and the module is not repeated.

The HDLC protocol data frame format is a mark word '7E' + effective data + two bytes CRC check code + mark word '7E', the global clock is the input working clock of the module, the HDLC protocol implementation block diagram is shown in figure 5, and the HDLC protocol receiving processing module implementation flow is as follows:

step 1: software receives an external input clock RxCLk and serial data RxD, and the shift register sends sampled serial data to the shift register according to the serial clock to continuously shift.

Step 2: the shift register sends the output parallel data to the flag word detection and zero deletion operation module. The module first performs flag bit detection, and when the flag word "7E" is detected and the two consecutive bytes are not both "7E", the data frame is valid. Data in the middle of the two flag words 7E is detected, and 1 '0' inserted after 5 '1's are continuously deleted to restore the original data content.

And step 3: the HDLC protocol receiving and processing module completes the synchronous processing of the signals of the serial clock domain and the parallel clock domain, and the CRC check module performs CRC check on the data after the zero deletion operation and outputs a corresponding check result.

And 4, step 4: and after passing through the CRC module, the data is subjected to serial/parallel conversion and is sent to a receiving buffer for data buffering, a receiving state signal is output, a read enabling signal is waited, and finally HDLC protocol data is output through DAT _ O.

HDLC protocol sending process:

step 1: and the software writes parallel data into the HDLC protocol module through the DAT _ I, and the parallel data are sent to the sending cache module for data caching. And after the data caching is finished, controlling the data to be read according to bytes according to the states of other modules in the sending process and finishing the parallel/serial conversion.

Step 2: and the HDLC protocol sending processing and zero insertion operation module completes the synchronous processing of the signals of the serial clock domain and the parallel clock domain. Meanwhile, 1 '0' is inserted after 5 '1's in the serial data to complete the data zero insertion operation.

And step 3: and the CRC generation module performs CRC on the data and generates a CRC code of two bytes to be attached to the data and then transmits the CRC code.

And 4, step 4: the flag word generator inserts 1 flag word '7E' into the head and tail of data frame according to the transmission flow control.

And 5: the transmission selector selects to transmit valid data, CRC check codes or flag words according to the control signals of the protocol module.

Step 6: the shift register is responsible for continuously shifting the input serial data through the shift register to output data TxD and simultaneously outputting a serial clock TxCLK.

The schematic diagram of the communication process with the antenna front end is shown in fig. 6, and the specific process is as follows:

step 1: dual-core ARM CORTEX of motherboard ZYNQ-7000 processor^TMThe processor PS of A9 receives 1553B command and finishesAnd after command analysis, when the communication with the front end of the antenna is needed. Dual-core ARM CORTEX^TMThe PS function of the a9 processor first acquires the semaphore. Setting an antenna front end instruction according to a communication protocol and a dual-core ARM CORTEX according to a received instruction sent by a control system and by combining a working time sequence of the antenna front end^TMThe a9 processor PS sends instruction frames to the programmable logic PL through the internal port and informs the programmable logic PL through the register to read the data in the buffer.

Step 2: the programmable logic PL reads the data in the buffer and sends instructions to the antenna front end according to the HDLC protocol.

And step 3: when the programmable logic PL of the motherboard ZYNQ-7000 processor receives a command response returned by the front end of the antenna, the receiving ready signal of the HDLC protocol module is valid, and the programmable logic PL controls to store the read data in the cache RAM of the protocol module into the programmable logic PL and the dual-core ARM CORTEX^TM-A9 processor PS internal interface cache RAM and send interrupt notification dual core ARM CORTEX^TMThe a9 processor PS reads the data.

And 4, step 4: the response frame returned by the front end of the antenna is sent to the dual-core ARM CORTEX through the programmable logic PL^TMA9 processor PS, determining whether the CRC check of the response frame is correct if the antenna front end returns a response, determining that the response of the antenna front end is valid if the response is correct, filling the command response of the antenna front end into the corresponding position of the buffer, determining whether the command response of the antenna front end has been sent three times if the CRC check is wrong or no response is returned within a specified time, and filling the corresponding position of the buffer into a corresponding error state if no response is found for three consecutive times or the check is wrong.

And 5: dual-core ARM CORTEX^TMThe A9 processor PS judges the state of the front end of the antenna according to the response, executes the instruction communication according to the overall flow control, and packs the response information to return to the control system after all the instructions are executed.

5. Working process of module for communicating with telemetering system

Telemetry request receiving process flow:

and after receiving a request frame sent by the telemetry system, the programmable logic PL of the daughter board ZYNQ-7000 processor reads the request frame data from the HDLC protocol module buffer and judges the validity of the request frame, and after judging that the frame is valid, the programmable logic PL triggers a telemetry data sending flow to start working.

Telemetry data sending and processing flow:

after the telemetry sending process is started, whether a telemetry data sending cache is empty is judged, when the cache is not empty, data in the cache is read, a communication protocol frame header is added, time mark information is printed, then the data are sent to an HDLC protocol module according to bytes, and the data are sent to a telemetry system through an RS422 interface. Meanwhile, the number of the remaining bytes in the sending cache is continuously detected, and when the number of the remaining bytes in the cache is smaller than a set threshold value, the dual-core ARM CORTEX is notified through interruption^TMThe a9 processor PS sends a frame of data again; when the sending buffer is empty, the downloaded data is an all-zero frame containing the frame header and the time mark information of the communication protocol.

6. Working process of communication module with other board cards

Data receiving and processing flow:

step 1: dual-core ARM CORTEX of ZYNQ-7000 processor^TMBoth the-a 9 processor PS and the programmable logic PL have access to the off-chip DDR 3. Dual-core ARM CORTEX of motherboard ZYNQ-7000 processor^TMThe A9 processor PS allocates the corresponding DDR3 memory address space for the different types of data sent by the other boards. The programmable logic PL control of the motherboard ZYNQ-7000 caches the received data of corresponding types into the address space corresponding to the DDR3, and the corresponding board card informs the dual-core ARM CORTEX through Doorbell^TMThe A9 processor PS data transmission is complete.

Step 2: dual-core ARM CORTEX of motherboard ZYNQ-7000 processor^TMThe A9 processor PS registers the SRIO DoorBell callback function, and generates a software interrupt when receiving the DoorBell of the SRIO; and the Doorbell interrupt service program processes Doorbell interrupt of the SRIO and performs corresponding data processing according to the SRIO address uSrcID and the Doorbell type of the interrupt source. When the image data is judged to be the image data, the image data is controlled to be sent to the processor of the sub-board ZYNQ-7000 through the SRIO bus between the mother board and the sub-board.

Data transmission processing flow:

step 1: motherboard ZYNQ-7000 processingDual-core ARM CORTEX of device^TMThe a9 processor PS sends the data to be sent to the corresponding board to the programmable logic PL through the internal port and informs the programmable logic PL of the completion of data sending through the status register according to the overall flow control.

Step 2: the programmable logic PL of the motherboard ZYNQ-7000 processor completes data caching and sends data to the SRIO switching chip according to the SRIO bus protocol, and the switching chip routes according to the ID and then sends the data to a corresponding (functional) board card through the VPX processor backboard.

7. Working process of communication module with data recording device

Dual-core ARM CORTEX of motherboard ZYNQ-7000 processor^TMThe A9 processor PS registers the SRIO DoorBell callback function, and generates a software interrupt when receiving the DoorBell of the SRIO; and the Doorbell interrupt service program processes Doorbell interrupt of the SRIO and performs corresponding data processing according to the SRIO address uSrcID and the Doorbell type of the interrupt source. And when the data is judged to be recorded, reading the recorded data from the DDR3 according to the allocated address space, sending the recorded data and the cached corresponding auxiliary information to the data recording device through a gigabit Ethernet, and sending a 1553B command sent by the cached control system to the data recording device through the Ethernet.

8. Image compression module working process

Step 1: after receiving image data sent by other board cards through the SRIO bus by the programmable logic PL of the daughter board ZYNQ-7000, the programmable logic PL of the daughter board ZYNQ-7000 transmits the image data to the SRIO bus according to the dual-core ARM CORTEX^TMWriting the PS allocated base address space of the A9 processor into the external DDR3 cache, and informing the sending completion of the (function) board card through Doorbell.

Step 2: dual-core ARM CORTEX of daughter board ZYNQ-7000^TMA9 processor PS registers SRIO DoorBell callback function, generates software interrupt when receiving the Doorbell of SRIO, the Doorbell interrupt service program processes the Doorbell interrupt of SRIO, processes corresponding data according to the SRIO address uSrcID and the Doorbell type of the interrupt source, when judging that the image data transmission is finished, executes image blocking operation, decomposes the image data into image blocks with 128 × 128 pixel size, transmits the 1 st image block to programmable logic PL, and registers by writing after the data transmission is finishedThe state of the device informs the programmable logic PL.

And step 3: programmable logic PL detection dual-core ARM CORTEX^TMThe method comprises the steps of reading image data and inputting the data into a wavelet transform module according to bytes to complete second-order Daubechies/3 lifting wavelet transform after a PS writing state register is effective, reading the image data and inputting the data into the wavelet transform module according to bytes to complete second-order Daubechies/3 lifting wavelet transform, a schematic diagram of the second-order Daubechies/3 wavelet transform is shown in FIG. 7, performing first-order wavelet transform on an image block with the size of 128 pixels to generate HH, HL, LH and LL 64-pixel size sub-bands, performing second-order wavelet transform on the LL sub-band to decompose the LL sub-band into HH, HL, LH and LL 32-pixel size sub-bands, and an updating sub-module, calculating the high-frequency component H of an output image by the predicting sub-module, performing prediction sub-module function, updating the low-frequency component L of the output image by the updating sub-module, performing wavelet transform to realize sub-band updating sub-module function by the sub-band, performing first-order data buffer and RAM address calculation, performing line/column transform to achieve second-order Daubechies/3 wavelet transform, reading sub-band data according to a sequence of HL, performing line/3 line/column wavelet transform, reading sub-line, line-3, line-line read, LH, line-lineAnd then the coefficients are respectively cached in an RAM _ h and an RAM _ v, and the second-order subband coefficients are stored in an RAM _ a after quantization, wherein a small quantization step size is adopted for a low-frequency subband with concentrated energy, and a large quantization step size is adopted for a high-frequency subband with less energy. Notifying dual-core ARM CORTEX through interruption after cache is finished^TMThe a9 processor PS reads the wavelet coefficients and sends the next image block data for wavelet transform.

And 4, step 4: dual-core ARM CORTEX^TMThe processor PS of A9 responds to the interrupt after receiving the interrupt, reads the wavelet transform coefficient and sends it to the SPIHT coding module to finish coding according to the preset refining times, and codes the wavelet coefficient of each sub-band in turn according to the important order of the code stream, and sends the compressed code stream data to the data coding module to judge whether all the image blocks are coded, if not, reads the wavelet coefficient of the next image data to execute coding operation.

9. Data framing module working process

Since the code stream length of image compression is related to the image content, the image compression ratio is not a fixed value. In order to adapt to the transmission bandwidth of a remote measuring system, the minimum compression ratio of an image is set to be 4, and when the length of a compressed code stream is detected to be larger than a set threshold value, an important code stream is intercepted preferentially for transmission. The image compression code stream adds frame head, image block number, SPIHT algorithm parameter, code stream length and code stream data and packs them into compression code stream data frame, the sub-board ZYNQ-7000 processor's dual-core ARM CORTEX^TMThe a9 processor PS sends the codestream data to the programmable logic PL in response to a data download interrupt request sent by the programmable logic PL.

Dual-core ARM CORTEX of daughter board ZYNQ-7000 processor^TMThe A9 processor PS extracts inertial navigation information in 1553B information sent by the control system at fixed time during imaging, adds frame header and frame number information, packs the information into an inertial navigation data frame, sends data to the programmable logic PL according to a data downloading interruption request sent by the programmable logic PL, and downloads the data through the telemetering system.

Dual-core ARM CORTEX of daughter board ZYNQ-7000 processor^TMThe algorithm run intermediate results sent by the processor PS a9 from the other boards, system critical status information, other assistanceAnd after adding frame header and data length information, the information and the like are packaged into a state detection data frame, the data is sent to the programmable logic PL according to a data downloading interruption request sent by the programmable logic PL, and the data is downloaded through a remote measuring system.

The present invention is not limited to the above embodiments, and those skilled in the art can implement the present invention in other various embodiments according to the disclosure of the present invention, so that all designs and concepts of the present invention can be changed or modified without departing from the scope of the present invention.

Claims (5)

1. A comprehensive processing system based on a VPX platform comprises a back plate provided with a plurality of slots and is characterized in that the system is a master-slave plate framework based on a standard VPX bus and comprises a mother plate and a daughter plate, wherein the mother plate is a switching interface plate, the daughter plate is an expansion interface plate, the mother plate and the daughter plate are connected through an XMC connector, and the mother plate and the daughter plate are communicated through an X4SRIO bus; the plurality of slots can be used for inserting a plurality of other board cards, and the backboard realizes communication between the motherboard and the daughter board in the integrated processing system and other board cards;

the exchange interface board is based on a motherboard ZYNQ-7000 processor, a motherboard SOC chip, an SRIO exchange chip and an Ethernet exchange chip and is mainly used for realizing data exchange and comprehensive control of the whole system, the motherboard ZYNQ-7000 processor is of an FPGA + ARM architecture, and the motherboard dual-core ARM Cortex^TM-A9 processor PS and motherboard programmable logic PL integrated on a single chip, motherboard dual ARM Cortex implemented via internal AXI bus^TMHigh speed data communication of the a9 processor PS and the motherboard programmable logic PL; the motherboard SOC chip is of an FPGA + ARM architecture, and the main interfaces comprise a motherboard SRIO, an MLVDS, an SGMII, a JTAG, an I2C, a QSPI, a PMBUS, a CAN and a motherboard RS 422;

the expansion interface board is an expansion interface daughter board of the switching module, is based on a daughter board ZYNQ-7000 processor and a daughter board SOC chip, and is mainly used for realizing interface expansion of the switching module, wherein the daughter board ZYNQ-7000 processor is of an FPGA + ARM architecture, and the daughter board dual-core ARM Cortex^TM-A9 processor PS and daughter board programmable logic PL integrated on a single chip, daughter board dual core ARM Cortex is realized through internal AXI bus^TMHigh speed data communication of the a9 processor PS and daughter board programmable logic PL; the daughter board SOC chip is of an FPGA + ARM architecture, and the main interface comprises a daughter board SRIO, a CameraLink, a 1553B and a daughter board RS 422;

the motherboard ZYNQ-7000 processor and the motherboard and the daughter board dual-core ARM Cortex in the daughter board ZYNQ-7000 processor^TMThe software operated by the processor PS and the programmable logic PL of the mother board and the daughter board of A9 carries out task division according to the interface type and the processing capacity, and can carry out multi-task scheduling and dynamic distribution of the computing nodes;

the motherboard and the daughter board are provided with dual cores of ARM Cortex^TMThe processor PS of A9 runs a VxWorks real-time operating system;

the motherboard and the daughter board are provided with dual cores of ARM Cortex^TMA9 processor PS and software run by the motherboard and daughterboard programmable logic PL writes different contents to the system according to the interface type and processing capability of the system to realize the system reconfiguration as required;

the comprehensive processing system is also connected with a general signal processing board through the back boards of the slots, and is externally connected with an optical detector through the CameraLink interface to construct an optical guidance system for comprehensive processing of optical guidance and realize the flow control and signal processing of the complete optical guidance system;

the general signal processing board adopts a processing architecture of a plurality of DSP6678 multi-core processors;

the comprehensive processing system is also connected with the multi-channel AD/DA board and the general signal processing board through the back boards of the slots, and a radar guidance system is constructed through the front end of an external antenna, so that the flow control and the signal processing of the complete radar guidance system are realized;

the multi-channel AD/DA board integrates a multi-channel AD/DA and FPGA processors;

the comprehensive processing software divides tasks according to the interface type and the processing capacity of the comprehensive processing system, performs multi-task scheduling and dynamic distribution of computing nodes, performs complex flow control, and can combine algorithmsThe part of the row operation can combine the resource use condition of the programmable logic PL of the motherboard and the daughter board and the ARM Cortex of the dual cores of the motherboard and the daughter board^TMThe processing capability of the processor PS A9 divides the algorithm into different sub-modules, and the sub-modules are operated cooperatively by the processor PS and the processor PS through a motherboard and a daughter board dual-core ARM Cortex^TMThe interaction of the intermediate results of the high-speed interfaces between the A9 processor PS and the programmable logic PLs of the mother board and the daughter board meets the requirements of the real-time performance of the comprehensive processing system, reduces the difficulty of algorithm implementation and improves the processing performance;

the comprehensive processing software comprises a communication module with the control system, a communication module with the antenna front end, a communication module with the remote measuring system, a communication module with the data recording device and a communication module with other board cards, and correspondingly comprises tasks of realizing command analysis and response and overall flow control:

the comprehensive processing software is communicated with the control system through a universal serial bus; the daughter board programmable logic PL mainly realizes the bus interface control task and the dual core ARM Cortex of the daughter board and the chip^TM-data interaction between a9 processors PS; daughter board dual core ARM Cortex^TMThe A9 processor PS mainly realizes data format conversion and data interaction with the on-chip daughter board programmable logic PL data, encapsulates received effective data into SRIO messages with the length specified by a protocol and sends the SRIO messages to the motherboard ZYNQ-7000 processor, extracts data packets in the SRIO messages sent by the motherboard ZYNQ-7000 processor and sends the data packets to a control system through the on-chip daughter board programmable logic PL control interface chip; the motherboard programmable logic PL mainly realizes the control task of the SRIO bus interface, the motherboard programmable logic PL and the motherboard dual-core ARM Cortex^TM-data interaction between a9 processors PS; motherboard dual-core ARM Cortex^TMThe A9 processor PS mainly realizes instruction analysis, executes template data loading, real-time parameter calculation and distribution, communication flow control and completes information synthesis and instruction response workflow according to the instruction analysis result; motherboard dual-core ARM Cortex^TMThe A9 processor PS simultaneously completes the data interaction with the on-chip motherboard programmable logic PL, responding to the commandThe answer information is packaged into SRIO messages with the length specified by the protocol and sent to the sub-board ZYNQ-7000 processor through the on-board mother board programmable logic PL;

the comprehensive processing software and the front end of the antenna adopt universal serial bus communication and an HDLC communication protocol; mother board double-core ARMCortex^TMThe A9 processor PS communicates with the antenna front end according to the overall flow control and the command analysis result, sends the command frame to the antenna front end through the on-chip motherboard programmable logic PL, extracts effective information from the received command response frame returned by the antenna front end, completes the overall flow control according to the working time sequence of the antenna front end, and after the flow execution is completed, synthesizes the information and packs the information into a bus message to return to the control system; the programmable logic PL of the motherboard realizes the HDLC protocol of communication with the front end of the antenna, and the dual cores ARM Cortex of the motherboard^TMThe command frame sent by the PS of the A9 processor is sent to the antenna front end according to the HDLC protocol, and the command response frame returned by the antenna front end according to the HDLC protocol is sent to the dual-core ARM Cortex of the motherboard through the internal interface^TM-a9 processor PS making data frame validity decisions and information extraction;

the comprehensive processing software is communicated with the remote measuring system through a universal serial bus, and an HDLC communication protocol is adopted; the daughter board programmable logic PL realizes an HDLC protocol for communicating with the telemetering system, and receives and analyzes a request frame sent by the telemetering system at regular time according to the HDLC protocol; the programmable logic PL of the daughter board passes through the daughter board dual core ARM Cortex^TMThe PS processing of the A9 processor obtains data needing to be transmitted by telemetering and down, time marking information is printed on the data, and then the data is transmitted to a telemetering system according to an HDLC protocol, if the daughter board and the daughter board are dual-core ARM Cortex^TMThe A9 processor PS processes the data which does not need to be downloaded, and then the telemetry data frame is downloaded to be an all-zero frame only containing the time mark information;

the comprehensive processing software and the data recording device communicate through the Ethernet and adopt a UDP communication protocol; the RGMII interface of the motherboard ZYNQ-7000 processor realizes the conversion of the SGMII interface and the RGMII interface through the PHY chip and then is connected with the Ethernet switching chip; motherboard dual-core ARM Cortex^TMThe A9 processor PS realizes the communication with the data recording device after the route of the Ethernet switching chip; after the comprehensive processing system is in power distribution work, when Do sent by other board cards is receivedAfter the OrBell informs that one frame of recorded data is sent, the dual-core ARM Cortex of the motherboard^TMThe A9 processor PS controls the DDR3 cached recording data and corresponding auxiliary information, and commands sent by the control system are sent to the data recording device according to a UDP protocol;

the comprehensive processing system for comprehensively processing software operation is connected with other board cards through a back plate of the VPX platform, and the communication between the comprehensive processing system and the other board cards and between the other board cards is completed through the SRIO high-speed bus; mother board double-core ARMCortex^TMThe A9 processor PS mainly completes SRIO bus data storage space allocation, and reads data from the DDR3 according to the SRIO address and the Doorbell type of the received data to complete data forwarding and data processing; the programmable logic PL of the motherboard mainly completes the control of the SRIO interface and the dual core ARM Cortex of the motherboard^TMData interaction of processor PS from A9, according to motherboard dual core ARMCortex^TMThe PS-allocated address space of the A9 processor controls the storage of received data in the externally-hung DDR3 memory; motherboard dual-core ARM Cortex^TMThe A9 processor PS sends data to be sent to other corresponding boards to the SRIO switch chip via the motherboard programmable logic PL according to the overall process control, and the SRIO switch chip routes the data according to the source ID and the target ID and then sends the data to other corresponding boards via the VPX platform backplane.

2. The system of claim 1, wherein the integrated processing software further comprises an image compression module, the motherboard ZYNQ-7000 processor transmits the received image data sent by other boards to the daughter board ZYNQ-7000 processor through the SRIO bus according to the SRIO address and the DoorBell type judgment of the received data; daughter board dual core ARM Cortex^TMThe A9 processor PS carries out blocking processing on the received image data, and after image blocking is finished, the image data blocks are sent to the daughter board programmable logic PL according to an interrupt request sent by the on-chip daughter board programmable logic PL to carry out second-order Daubechies5/3 lifting wavelet transformation; LH1 and HL1 sub-bands formed by first-order wavelet transform and HH2, LH2, HL2 and LL2 sub-bands formed by second-order wavelet transform are subjected to quantization processing by using different quantization step sizes and then are sent to the on-chip and the daughter-board dual-core ARM Cortex^TM-A9 treatmentA PS; daughter board dual-core ARMCortex^TMThe a9 processor PS encodes each sub-band wavelet coefficient using the SPIHT algorithm.

3. The system of claim 1 or 2, wherein the integrated processing software further comprises a data framing module, a daughter board dual core ARM Cortex^TMThe A9 processor PS packs the image compression code stream data into a compression code stream data frame by adding a compression code stream frame header, an image block number, SPIHT algorithm parameters, a code stream length and code stream data; adding frame header and frame number information to inertial navigation data received in an imaging period and packaging the inertial navigation data into inertial navigation data frames; and adding frame headers and data length information to the received algorithm operation intermediate results, system key state information and other auxiliary information sent by other board cards, and packaging the result into a state detection data frame.

4. The system of claim 1 or 2, wherein the integrated processing software further comprises a BIT detection module.

5. The system of claim 3, wherein the integrated processing software further comprises a BIT detection module.

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