WO2022227092A1

WO2022227092A1 - Movable platform, and verification apparatus and verification method for chip design

Info

Publication number: WO2022227092A1
Application number: PCT/CN2021/091772
Authority: WO
Inventors: 张鼎; 林顺豪; 周贤超; 许美蓉
Original assignee: 深圳市大疆创新科技有限公司
Priority date: 2021-04-30
Filing date: 2021-04-30
Publication date: 2022-11-03

Abstract

A movable platform (100), comprising: a machine body (110); a first FPGA module (10), which is capable of writing a function program file so as to configure same as a functional subsystem, wherein the functional subsystem is used to execute a functional task corresponding to the function program file, and the functional task comprises controlling the machine body (110) to adjust a pose; a hard-core processor (20), which is connected to the first FPGA module (10), and which is used to execute a computer program and schedule the first FPGA module (10) when the computer program is executed, the first FPGA module (10) and the hard-core processor (20) both being provided on the machine body (110). The amount of FPGA resources occupied during chip verification can be reduced. Also provided are a verification apparatus and verification method for chip design.

Description

Movable platform, verification device and verification method for chip design

technical field

The present application relates to the technical field of chip design, and in particular, to a movable platform, a verification device for chip design, and a verification method.

Background technique

FPGA (Field Programmable Gate Array, Field Programmable Gate Array) is a hardware device that can realize any circuit. It can be used to configure the chip design into the FPGA for real functional operation, so as to truly verify the correctness of the chip design. . In the process of chip development, FPGA verification is an essential verification method to actually put the chip code into the hardware to run.

The inside of the chip can be composed of multiple subsystems, and these subsystems work together to complete the task of the entire chip. Before Tape Out (fabrication), each chip needs to perform its own functional verification of each subsystem, called ST (System Test), and/or need to integrate all subsystems for verification, called IT ( Integration Test).

For example, inside the SoC (System on Chip) chip for mobile platforms, there are multiple subsystems such as processor subsystem, flight control subsystem, Image Signal Process (ISP) subsystem, high-speed external When testing, the processor subsystem is required to control the verified subsystem and complete the function together. However, the processor subsystems (such as CPU, ARM subsystems, etc.) of chips that generally exist for a long time in the industry are very large and occupy a lot of FPGA resources.

SUMMARY OF THE INVENTION

The present application provides a mobile platform, a verification device for chip design, and a verification method, which aim to solve the technical problems that existing chip verification takes up a lot of FPGA resources.

In a first aspect, an embodiment of the present application provides a movable platform, including:

body;

a first FPGA module, capable of writing a functional program file to be configured as a functional subsystem, where the functional subsystem is configured to execute a functional task corresponding to the functional program file, and the functional task includes controlling the body to adjust the pose;

a hard-core processor, connected to the first FPGA module, for executing a computer program and scheduling the first FPGA module when executing the computer program;

Both the first FPGA module and the hard core processor are arranged on the body.

In a second aspect, an embodiment of the present application provides a verification device for a chip design, including:

a first FPGA module, capable of writing a functional program file to be configured as a functional subsystem, where the functional subsystem is used to execute a functional task corresponding to the functional program file;

A hard-core processor, connected to the first FPGA module, is configured to execute a computer program and schedule the first FPGA module when executing the computer program.

In a third aspect, an embodiment of the present application provides a method for verifying a chip design, including:

Get functional program files;

Write the acquired functional program file into the first FPGA module of the verification device to obtain a functional subsystem;

obtain computer programs;

The hard-core processor configuring the verification apparatus executes the computer program and schedules the first FPGA module when executing the computer program.

The embodiments of the present application provide a mobile platform, a verification device and a verification method for chip design. By importing the chip design into the mobile platform, the verification environment of the chip design can be more suitable for the actual application scenario of the mobile platform. The verification of the chip design is more accurate; the first FPGA module can write a functional program file to configure it as a functional subsystem to execute the functional task corresponding to the functional program file, and schedule the first FPGA module through the hard-core processor, which can solve the problem of During the verification process of the chip design, the processor subsystem has a long-term monopoly on a large-capacity and expensive FPGA, and the operating frequency and performance of the hard-core processor are stronger, which facilitates timing closure and avoids limitations such as the logic capacity of the FPGA.

It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and do not limit the disclosure of the embodiments of the present application.

Description of drawings

In order to explain the technical solutions of the embodiments of the present application more clearly, the following briefly introduces the accompanying drawings used in the description of the embodiments. Obviously, the drawings in the following description are some embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained from these drawings without any creative effort.

1 is a schematic structural diagram of a movable platform provided by an embodiment of the present application;

2 is a schematic diagram of data transmission performed by a movable platform and a terminal device in an embodiment;

3 is a schematic diagram of the connection between a first FPGA module and a hard-core processor in an embodiment;

4 is a schematic diagram of the connection between the first FPGA module and the hard-core processor in another embodiment;

5 is a schematic diagram of the connection between the first FPGA module and the hard-core processor in another embodiment;

6 is a schematic diagram of the connection between the first FPGA module and the hard-core processor in yet another embodiment;

7 is a schematic structural diagram of a verification device for a chip design provided by an embodiment of the present application;

FIG. 8 is a schematic flowchart of a verification method for a chip design provided by an embodiment of the present application.

Description of reference numerals: 100, movable platform; 110, body; 111, power assembly; 120, remote control; 130, mobile phone; 140, wearable device; 10, first FPGA module; 20, hard core processor; 30 41, a first interface; 42, a second interface; 43, a third interface; 200, a SoC chip; 300, an external device; 600, a verification device.

Detailed ways

The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

The flowcharts shown in the figures are for illustration only, and do not necessarily include all contents and operations/steps, nor do they have to be performed in the order described. For example, some operations/steps can also be decomposed, combined or partially combined, so the actual execution order may be changed according to the actual situation.

Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and features in the embodiments may be combined with each other without conflict.

Please refer to FIG. 1 . FIG. 1 is a schematic structural diagram of a movable platform 100 provided by an embodiment of the present application. Exemplarily, the movable platform 100 may include at least one of an unmanned aerial vehicle, a gimbal, an unmanned vehicle, and the like. Further, the unmanned aerial vehicle can be a rotary-wing drone, such as a quad-rotor drone, a hexa-rotor drone, an octa-rotor drone, or a fixed-wing drone.

Exemplarily, as shown in FIG. 1 , the movable platform 100 includes a body 110, and the body 110 includes a power assembly 111. For example, the power assembly 111 includes a motor and a blade, and the motor drives the blade to rotate, which can provide the movable platform. 100 Power to adjust position and/or attitude. In other embodiments, the power assembly 111 may include a wheel, such as a Mecanum wheel.

In some embodiments, the mobile platform 100 can be used to verify the chip design of the mobile platform 100 to determine the performance, reliability and other indicators or defects of the chip design; in other embodiments, users can design their own The custom chip design or the open source chip design is imported into the mobile platform 100 to realize the mobile platform 100 of the custom chip design.

In some embodiments, the movable platform 100 is capable of being communicatively connected with a terminal device. As shown in FIG. 2 , the terminal device includes at least one of the following: a remote control 120 , a mobile phone 130 , and a wearable device 140 , for example, a wearable device 140 may include first-person view (First Person View) glasses, but is not limited to this, for example, the terminal device may also include a tablet computer, a laptop computer, a desktop computer, and the like.

Exemplarily, a wireless channel from the mobile platform 100 to the terminal device, referred to as a downlink channel, is used to transmit data collected by the mobile platform 100, such as video, images, sensor data, and the mobile platform 100, such as unmanned telemetry data such as the status information (OSD) of the aircraft; the wireless channel from the terminal device to the mobile platform 100 is called the uplink channel, which is used to transmit remote control data; for example, when the mobile platform 100 is an aircraft, the uplink channel is used to transmit flight control Commands and control commands such as taking pictures, recording videos, and returning to home.

Exemplarily, indicators or defects such as performance and reliability of the chip design may be determined according to the motion state of the movable platform 100 .

In some embodiments, the mobile platform 100 introduced into the chip design can fly according to the control logic corresponding to the chip design, fly according to a preset flight route or according to the control of the terminal device, or perform preset tasks according to sensor data of several sensors during flight , such as avoiding obstacles, flying with the target object, etc. Of course it is not limited to this.

Exemplarily, the user or the terminal device may determine the performance, reliability and other indicators or defects of the chip design according to the motion state of the movable platform 100, or the movable platform 100 may determine the performance, reliability, etc. of the chip design according to its own motion state. indicator or defect.

By importing the chip design into the movable platform 100, the verification environment of the chip design can be more suitable for the actual application scenario of the movable platform 100, and the verification of the chip design can be more accurate.

The inventor of the present application found that, in the current chip design verification, the processor subsystem is usually synthesized and wired separately, and programmed into an FPGA as the processor subsystem, and integrated and verified with the functional subsystem. When verifying the chip design under this method, since the timing convergence of the FPGA is different from that of the hard-core processor 20, and the processor subsystem operates at a lower frequency, the timing convergence is more difficult.

The inventor also found that the logic gate capacity of the processor subsystem is huge, and if it is programmed into an FPGA for integration, it will occupy an FPGA with a larger capacity, and the occupied cost is relatively high. Due to the limited number of logic gates in the FPGA, even in some complex processor subsystem verification work, it is impossible to put the entire processor subsystem into one FPGA. Moreover, the verification of each functional subsystem is dependent on the processor subsystem, so the processor subsystem needs to be greatly prioritized over the development of other functional subsystems in terms of schedule dependencies. In other words, the processor subsystem will become a dependency and bottleneck for the development and verification of chip development and the development of other functional subsystems.

In response to this discovery, the inventors of the present application have improved the verification device 600 and the verification method for chip design, so that the functions of the processor subsystem can be realized through the hard-core processor 20, and the chip system integration can be completed without monopolizing a large-capacity FPGA. verify. In some embodiments, off-the-shelf stable processor subsystems can be used in combination, thereby reducing or eliminating the dependency on developing processor subsystems, making the verification process more flexible and time-efficient. In some embodiments, the hard-core processor 20 has a higher operating frequency and higher performance than a processor subsystem that is instantiated in an FPGA (program files of the processor subsystem are programmed), which facilitates timing closure and avoids the need for an FPGA. logical capacity and other limitations.

Specifically, as shown in FIG. 1 , the movable platform 100 includes a body 110 , a first FPGA module 10 and a hard core processor 20 .

The first FPGA module 10 and the hard core processor 20 are both disposed on the body 110 . Exemplarily, the first FPGA module 10 and the hard core processor 20 are integrally provided with the body 110 , or at least one of the first FPGA module 10 and the hard core processor 20 is detachably connected to the body 110 .

In some embodiments, the first FPGA module 10 and the hard core processor 20 may be provided on one or more circuit boards, and the circuit boards are provided on the body 110, for example, connected to the power component 111 on the body 110 to control the power The component 111 moves to control the body 110 to adjust the posture, for example, to control the body 110 to hover, change the course, and fly the speed.

The first FPGA module 10 can write a function program file to be configured as a function subsystem, and the function subsystem is used to execute the function task corresponding to the function program file. For example, the functional task includes controlling the body 110 to adjust the posture.

Exemplarily, the function program file can convert the chip functions and subsystems into FPGA logic units by dividing the chip functions and subsystems into multiple FPGA capacity spaces (which can be called division), and convert the digital chip codes of the chip functions and subsystems into FPGA logic units (which can be called synthesis). ), and laying out the converted FPGA logic unit in the FPGA (which can be called a comprehensive layout), and connecting the internal signal to the FPGA logic unit (which can be called a comprehensive wiring), and burning the function program file into the FPGA, and running it, can verify the correctness of the chip design.

In some embodiments, the functional subsystem includes at least one of the following: a control subsystem, an image signal processing subsystem, and a peripheral subsystem. Of course it is not limited to this.

Exemplarily, the image signal processing subsystem can process the image captured by the camera mounted on the movable platform 100, for example, the first FPGA module 10 burns the design file of the image signal processing (Image Signal Processing, ISP) chip to obtain image signal processing. subsystem.

Exemplarily, the peripheral subsystem can process at least one of the following sensor (peripheral) sensors: gyroscope, electronic compass, inertial measurement unit (Inertia1 Measurement Unit, IMU), vision sensor, global positioning system (G1oba1 Positioning System, GPS) ), barometer, airspeed meter. The peripheral subsystem processes the sensor data, and can determine the pose information of the movable platform 100, that is, the position information and state information of the movable platform 100 in space, such as three-dimensional position, three-dimensional angle, three-dimensional velocity, three-dimensional acceleration and three-dimensional angular velocity Wait. For example, the first FPGA module 10 can program a chip design capable of processing sensor data to obtain a peripheral subsystem.

Illustratively, a control subsystem may be used to control movement of the movable platform 100 . For example, the control subsystem may control the movable platform 100 according to preset program instructions. For example, the control subsystem can control the movement of the movable platform 100 according to the pose information of the movable platform 100 measured by the peripheral subsystem, can also control the movable platform 100 according to the control signal from the terminal device, or can control the movable platform 100 according to the image The signal processing subsystem controls the movement of the movable platform 100 with the result of processing the images captured by the imaging device mounted on the movable platform 100 . Exemplarily, when the movable platform 100 includes an unmanned aerial vehicle, the control subsystem includes a flight control subsystem. For example, the first FPGA module 10 burns the design file of the flight control system (flight control) chip to obtain the control subsystem.

It should be noted that, different functional subsystems may be configured in the same first FPGA module 10 , or may be configured in different first FPGA modules 10 . For example, one or more function program files can be programmed into each first FPGA module 10 according to the hardware resources of the first FPGA module 10 . In some embodiments, one functional program file can be programmed into one first FPGA module 10, or programmed into multiple first FPGA modules 10. For example, a chip design corresponding to a certain functional program file needs to occupy more space. When the hardware resource is used, it can be programmed in multiple first FPGA modules 10 .

Specifically, the hard core processor 20 is connected to the first FPGA module 10 for executing a computer program and scheduling the first FPGA module 10 when executing the computer program.

Exemplarily, the movable platform 100 further includes a memory, and the hard-core processor 20 is used for running the computer program stored in the memory and scheduling the first FPGA module 10 when executing the computer program.

For example, the memory may be a Flash chip, a read-only memory (ROM, Read-Only Memory) magnetic disk, an optical disk, a U disk, or a removable hard disk, and the like.

In some embodiments, the hard core processor 20 may be referred to as an application processor (Application Processor, AP) subsystem or a processor subsystem. Exemplarily, the application processor subsystem can cooperate with each functional subsystem to complete the task of the entire chip, wherein the application processor subsystem is the control center of the entire chip, and serves as the main overall scheduling, so that the chip completes the overall function.

Exemplarily, the hard-core processor 20 can access various functional subsystems, such as the flight control subsystem, when executing the computer program. The system transmits corresponding data to the hard-core processor 20, and after the data transmission is successful, the flight control subsystem can continue to perform subsequent operations, such as controlling the movement of the unmanned aerial vehicle.

In some embodiments, the hard core processor 20 includes at least one of the following: an ARM architecture processor, a PowerPC architecture processor, and an x86 architecture processor.

Exemplarily, the hard-core processor 20 may include one or more processor cores. For example, the hard-core processor 20 may include a multi-core processor (Multi-processor System on Chip, MPSoC). efficacy.

In some embodiments, as shown in FIG. 3 , a plurality of first FPGA modules 10 are connected in a ring topology, and a hard core processor 20 is connected to one of the first FPGA modules 10 .

Exemplarily, the hard core processor 20 sends information to a first FPGA module 10 directly connected to it, and the first FPGA module 10 can send corresponding information to the remaining first FPGA modules 10 . For example, the information sent by the hard core processor 20 includes identification information of the target functional subsystem, and the target functional subsystem is one or more of the multiple functional subsystems, and the corresponding functional subsystem receives the hard core processor When the information including the identification information of the functional subsystem is sent by 20, the corresponding preset task is executed according to the information sent by the hard core processor 20.

Exemplarily, the information sent by each first FPGA module 10 to the hard-core processor 20 includes the identification information of the corresponding functional subsystem, and the hard-core processor 20 can perform the corresponding preset task according to the information sent by the first FPGA module 10, For example, according to the pose information of the movable platform 100 determined by the peripheral subsystem, the peripheral subsystem is controlled to adjust the detection direction of the vision sensor.

In other embodiments, as shown in FIGS. 4 to 6 , the movable platform 100 further includes a second FPGA module 30 . The hard core processor 20 is connected to the first FPGA module 10 through the second FPGA module 30 . It can be understood that a plurality of first FPGA modules 10 can form a star topology connection with the second FPGA module 30 , and in some embodiments, the hard core processor 20 can be connected to a plurality of first FPGA modules 10 through the second FPGA module 30 . Multiple functional subsystems communicate concurrently.

Exemplarily, as shown in FIG. 4 to FIG. 6 , each of the plurality of first FPGA modules 10 is connected to the second FPGA module 30 . For example, a plurality of first FPGA modules 10 are connected to a plurality of interfaces of the second FPGA module 30 to implement a star topology communication network. It should be noted that, one interface of the second FPGA module 30 is not limited to being connected to one first FPGA module 10 .

Exemplarily, multiple first FPGA modules 10 communicate concurrently with the hard core processor 20 through the second FPGA modules 30 . In some embodiments, the hard-core processor 20 has a higher operating frequency and higher performance than a processor subsystem formed by instantiating (burning program files of the processor subsystem) in the FPGA, and can process multiple The data of one functional subsystem has better real-time performance for the scheduling of multiple functional subsystems.

Exemplarily, the second FPGA module 30 is configured to forward control information and/or data between the hard core processor 20 and/or the first FPGA module 10 . Exemplarily, the second FPGA module 30 can act as an agent to forward information such as signaling and/or data sent by the hard core processor 20 to one or more functional subsystems, and can also send one or more functional subsystems. The information such as signaling and/or data is forwarded to the hard core processor 20. In this way, signaling and data communication between the hard core processor 20 and the functional subsystem to be verified (DUT Device under Test) are realized.

In some embodiments, as shown in FIG. 4 , the second FPGA module 30 is connected to the hard core processor 20 through a first interface 41 , and the second FPGA module 30 is connected to the first FPGA module 10 through a second interface 42 . The data transmission speed of the first interface 41 is faster than that of the second interface 42 , and/or the data bandwidth of the first interface 41 is higher than that of the second interface 42 .

Exemplarily, the first FPGA module 10 and the second FPGA module 30 are connected through a SERDES (SERializer/DESerializer, serializer/deserializer) interface, which is certainly not limited thereto.

The SERDES interface is a time-division multiplexing (TDM), point-to-point (P2P) serial communication technology. The multi-channel low-speed parallel signals at the sending end can be converted into high-speed serial signals. After transmission, the high-speed serial signals at the receiving end are transmitted. Can be reconverted to low-speed parallel signals. In order to realize the fast transmission of control information and/or data between the second FPGA module 30 and the first FPGA module 10 .

Exemplarily, the second FPGA module 30 is connected to the hard core processor 20 through an AXI bus interface (or can be called as Advanced eXtensible Interface, advanced extension interface), of course, it is not limited to this, for example, the second FPGA module 30 is connected to the hard core processor 20. The processors 20 may be connected through an Advanced High Performance Bus (AHB) interface.

Connecting the second FPGA module 30 and the hard core processor 20 through the first interface 41 can realize fast data transmission between the second FPGA module 30 and the hard core processor 20, and the data bandwidth of the first interface 41 is higher than that of the second interface. The data bandwidth of 42 is high, and the speed and bandwidth of data transmission can be much higher than the transmission speed and bandwidth between multiple FPGAs through the PCB hard board connection mode. It is convenient for the hard-core processor 20 to communicate concurrently with multiple first FPGA modules 10 through the second FPGA module 30, and can make full use of the advantages of the working frequency and stronger performance of the hard-core processor 20, and process multiple functional subsystems more quickly. It has better real-time performance for scheduling of multiple functional subsystems.

In some embodiments, as shown in FIG. 5 , the second FPGA module 30 and the hard core processor 20 are integrally provided. The length of the data transmission path between the second FPGA module 30 and the hard core processor 20 can be shortened, thereby reducing power consumption and interference.

Exemplarily, the second FPGA module 30 and the hard core processor 20 are located in the same SoC chip 200 (System on Chip). Performance limitations caused by delays in data moving in and out of multiple chips can be avoided, and reliability and cost can be improved.

Exemplarily, inside the SoC chip 200, the hard core processor 20 and the second FPGA module 30 perform operation communication and data transmission through the AXI bus. By using the AXI bus inside the SoC chip 200 to communicate between the hard core processor 20 and the second FPGA module 30, the bandwidth rate of data transmission between the two is very high (bandwidth upper limit TBD), which is much higher than the traditional way of passing between multiple FPGAs. Data bandwidth via PCB hard board connection mode.

In some embodiments, as shown in FIG. 6 , the hard core processor 20 further includes a third interface 43 , and the hard core processor 20 is further configured to communicate with the external device 300 through the third interface 43 .

Exemplarily, the third interface 43 includes at least one of the following: a USB interface, an Ethernet interface, and a PCIe interface. Of course, it is not limited to this, for example, the third interface 43 may include a wireless communication component, and the hard core processor 20 may communicate with the external device 300 through the wireless communication component.

Exemplarily, the hard core processor 20 in the SoC chip 200 may perform high-bandwidth high-speed data communication with the external device 300 through a standard high-speed interface, that is, the third interface 43 .

Exemplarily, the hard-core processor 20 is further configured to acquire data from the external device 300 through the third interface 43, send the data acquired from the external device 300 to the first FPGA module 10, and the first FPGA module 10 to 300 The acquired data is processed. For example, the data includes at least one of the following: video, image, and data set, but of course, it is not limited thereto.

Exemplarily, the hard-core processor 20 may acquire video, images, data sets, and other data with a large amount of data from the external device 300 through the third interface 43, and distribute the acquired data to corresponding functional subsystem modules for processing. For example, the hard-core processor 20 sends the image acquired from the external device 300 to the image signal processing subsystem through the second FPGA module 30, so that the image signal processing subsystem can process the image and realize the image signal processing subsystem. 's verification. For example, the hard core processor 20 sends the sensor data obtained from the external device 300 to the peripheral subsystem through the second FPGA module 30, so that the peripheral subsystem can process the sensor data and realize the verification of the peripheral subsystem .

Exemplarily, the hard-core processor 20 is further configured to acquire data acquired and/or output by the first FPGA module 10 , and send the data acquired and/or output by the first FPGA module 10 through the third interface 43 . to the external device 300.

For example, the hard core processor 20 acquires data processed by each functional subsystem, and sends the data processed by each functional subsystem to the external device 300 through the third interface 43, so that the external device 300 can store and/or display each Data processed by the functional subsystem.

For example, by comparing the expected processing result corresponding to the data obtained according to the functional subsystem with the data processed by the functional subsystem received by the external device 300, the verification of the functional subsystem can be realized.

In the movable platform provided by the embodiments of the present application, by importing the chip design into the movable platform, the verification environment of the chip design can be more suitable for the actual application scenario of the movable platform, and the verification of the chip design can be more accurate. The first FPGA module can write a function program file to be configured as a function subsystem to execute the function task corresponding to the function program file, and schedule the first FPGA module through a hard-core processor, and the hard-core processor can realize the processor subsystem It can complete the verification of the chip design without the need for a large-capacity FPGA to program the processor subsystem, which can solve the dilemma of the processor subsystem monopolizing a large-capacity expensive FPGA for a long time during the verification process. Moreover, the operating frequency and performance of the hard-core processor are stronger, which is convenient for timing closure and avoids limitations such as the logic capacity of the FPGA.

In some embodiments, an off-the-shelf and stable processor subsystem can be used in combination without relying on a self-developed processor subsystem, so that the verification relationship between it and other subsystems can be decoupled, so as to improve verification efficiency and reduce overall verification costs. time. When the processor subsystem is still in the development process and has not been formed, the function of the functional subsystem can be controlled during the verification process, and the correctness of the function of the functional subsystem can be verified. The verification process is more flexible and time-efficient. When using an off-the-shelf hard-core processor for overall chip verification, there is no need for complex timing closure of the processor subsystem in the FPGA, which greatly increases the operating frequency of the processor subsystem and makes the overall verification environment closer to the real chip operating state.

In some implementations, the hard core processor 20 can often be connected to many standard high-speed interfaces, such as USB, Ethernet, PCIe, etc., and can communicate with the external device 300 through these standard interfaces with large bandwidth data, which is convenient for verification of chip design.

Please refer to FIG. 7 in conjunction with the above embodiments. FIG. 7 is a schematic block diagram of an apparatus 600 for verifying a chip design provided by an embodiment of the present application. It can be understood that the verification apparatus 600 can be used for the aforementioned movable platform 100, and is of course not limited to this, that is, the verification apparatus 600 is not limited to verifying the chip design of the mobile platform 100, for example, it can be used for the chip design of the terminal device. For verification, the terminal device includes, for example, a mobile phone 130, a tablet computer, a notebook computer, a desktop computer, a personal digital assistant, a wearable device 140, a remote control 120, and the like.

In some embodiments, the verification apparatus 600 may include the first FPGA module 10 and the hard core processor 20 in the aforementioned movable platform 100 . Exemplarily, the verification device 600 and the body 110 of the movable platform 100 may be integrally provided, or may be detachably connected to the body 110 of the movable platform 100 .

Specifically, as shown in FIGS. 2 to 6 , the verification apparatus 600 includes a first FPGA module 10 and a hard core processor 20 .

In some embodiments, the first FPGA module 10 and the hard core processor 20 may be provided on one or more circuit boards.

The first FPGA module 10 can write a function program file to be configured as a function subsystem, and the function subsystem is used to execute the function task corresponding to the function program file.

Exemplarily, the verification apparatus 600 further includes a memory, and the hard-core processor 20 is configured to run the computer program stored in the memory, and schedule the first FPGA module 10 when executing the computer program.

In other embodiments, as shown in FIG. 4 to FIG. 6 , the verification apparatus 600 further includes a second FPGA module 30 . The hard core processor 20 is connected to the first FPGA module 10 through the second FPGA module 30 . It can be understood that a plurality of first FPGA modules 10 can form a star topology connection with the second FPGA module 30 , and in some embodiments, the hard core processor 20 can be connected to a plurality of first FPGA modules 10 through the second FPGA module 30 . Multiple functional subsystems communicate concurrently.

Exemplarily, the hard core processor 20 in the SoC chip 200 can perform high-bandwidth high-speed data communication with the external device 300 through a standard high-speed interface, that is, the third interface 43.

The specific principles and implementation manners of the verification device 600 for chip design provided by the embodiment of the present application are similar to the movable platform 100 of the foregoing embodiment, and are not repeated here.

In the verification device of the chip design according to the embodiment of the present application, the first FPGA module can write a function program file to be configured as a function subsystem, so as to execute the function task corresponding to the function program file, and schedule the first FPGA module through a hard-core processor , which can solve the dilemma of the processor subsystem monopolizing a large-capacity and expensive FPGA for a long time during the verification process, and the operating frequency and performance of the hard-core processor are stronger, which is convenient for timing closure and avoids limitations such as the logic capacity of the FPGA.

Please refer to FIG. 8 in conjunction with the foregoing embodiment. FIG. 8 is a schematic flowchart of a verification method for a chip design provided by an embodiment of the present application. The verification method can be used to verify the chip design. Exemplarily, the verification method can be used in the aforementioned mobile platform 100 or the verification apparatus 600 of the chip design.

As shown in FIG. 8 , the verification method of the embodiment of the present application includes steps S110 to S140.

S110. Obtain a function program file.

In some embodiments, the function program file can convert the chip functions and subsystems into FPGA logic units by dividing the chip functions and subsystems into multiple FPGA capacity spaces (which may be called division), and convert the digital chip codes of the chip functions and subsystems into FPGA logic units (which may be called as divisions). For synthesis), and laying out the converted FPGA logic unit in the FPGA (may be called a synthesis layout), and connecting the internal signal to the FPGA logic unit (may be called a synthesis route).

S120. Write the acquired functional program file into the first FPGA module of the verification device to obtain a functional subsystem.

Exemplarily, the function program file is burned into the FPGA and run, so that the correctness of the chip design can be verified.

S130. Obtain a computer program.

S140. Configure the hard-core processor of the verification apparatus to execute the computer program and schedule the first FPGA module when executing the computer program.

Exemplarily, the computer program may be stored in the memory, and the hard-core processor 20 is used to execute the computer program stored in the memory, and schedule the first FPGA module 10 when executing the computer program.

Exemplarily, inside the SoC chip 200, the hard core processor 20 and the second FPGA module 30 perform operation communication and data transmission through the AXI bus. By using the AXI bus inside the SoC chip 200 to communicate between the hard core processor 20 and the second FPGA module 30, the bandwidth rate of data transmission between the two is very high (bandwidth upper limit TBD), which is much higher than the traditional way of passing between multiple FPGAs. Data bandwidth over PCB hard board connection mode.

In some embodiments, as shown in FIG. 6 , the hard core processor 20 further includes a third interface 43 , and the method further includes: the hard core processor 20 passes the third interface 43 of the hard core processor 20 through the hard core processor 20 . Communication with the external device 300 is performed.

Exemplarily, the hard-core processor 20 communicates with the external device 300 through the third interface 43 of the hard-core processor 20 , including: the hard-core processor 20 communicates with the external device through the third interface 43 . 300 acquires data, and sends the data acquired from the external device 300 to the first FPGA module 10 , so that the first FPGA module 10 processes the data acquired from the external device 300 . For example, the data includes at least one of the following: video, image, data set, but certainly not limited thereto.

Exemplarily, the communication between the hard-core processor 20 and the external device 300 through the third interface 43 of the hard-core processor 20 includes: the hard-core processor 20 obtains the information obtained by the first FPGA module 10 . data and/or output data, and the data acquired and/or output by the first FPGA module 10 are sent to the external device 300 through the third interface 43 .

The specific principles and implementation manners of the verification method for the chip design provided by the embodiment of the present application are similar to the verification apparatus 600 of the foregoing embodiment, and are not repeated here.

In the verification method for chip design provided by the embodiment of the present application, by writing a functional program file into the first FPGA module of the verification device, the first FPGA module is configured as a functional subsystem, and the hard-core processor of the verification device is configured to verify the first FPGA module of the verification device. Scheduling an FPGA module can solve the dilemma of the processor subsystem monopolizing a large-capacity and expensive FPGA for a long time during the verification process of the chip design, and the working frequency and performance of the hard-core processor are stronger, which is convenient for timing convergence and avoids the FPGA Limitations such as logical capacity.

It should be understood that the terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the application.

It will also be understood that, as used in this application and the appended claims, the term "and/or" refers to and including any and all possible combinations of one or more of the associated listed items.

The above are only specific implementations of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalents within the technical scope disclosed in the present application. Modifications or substitutions shall be covered by the protection scope of this application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

A movable platform, characterized in that, comprising:

body;

a first FPGA module, capable of writing a functional program file to be configured as a functional subsystem, where the functional subsystem is configured to execute a functional task corresponding to the functional program file, and the functional task includes controlling the body to adjust the pose;

a hard-core processor, connected to the first FPGA module, for executing a computer program and scheduling the first FPGA module when executing the computer program;

Both the first FPGA module and the hard core processor are arranged on the body.
The movable platform according to claim 1, wherein a plurality of the first FPGA modules are connected in a ring topology, and the hard core processor is connected to one of the first FPGA modules.
The movable platform according to claim 1 or 2, wherein the functional subsystem includes at least one of the following: a control subsystem, an image signal processing subsystem, and a peripheral subsystem.
The movable platform of claim 1, further comprising:

A second FPGA module, the hard-core processor is connected to the first FPGA module through the second FPGA module, and the second FPGA module is used to forward the hard-core processor and/or the first FPGA Control information and/or data between modules.
The movable platform according to claim 4, wherein each of the plurality of first FPGA modules is connected to the second FPGA module.
The movable platform according to claim 5, wherein a plurality of the first FPGA modules communicate concurrently with the second FPGA module through the second FPGA module.
The movable platform according to claim 4, wherein the second FPGA module and the hard core processor are connected through a first interface, and the second FPGA module and the first FPGA module are connected through a second interface The interface is connected, and the data transmission speed of the first interface is faster than the data transmission speed of the second interface.
The movable platform according to claim 7, wherein the first FPGA module and the second FPGA module are connected through a SERDES interface.
movable platform according to claim 7, is characterized in that, described second FPGA module and described hard core processor are connected by AXI bus interface.
The movable platform according to any one of claims 4-9, wherein the second FPGA module and the hard-core processor are integrally provided.
The movable platform according to claim 10, wherein the second FPGA module and the hard core processor are located in the same SoC chip.
The mobile platform according to any one of claims 1-11, wherein the hard-core processor comprises at least one of the following: an ARM architecture processor, a PowerPC architecture processor, and an x86 architecture processor.
The movable platform according to any one of claims 1-12, wherein the hard-core processor further comprises a third interface, and the hard-core processor is further configured to communicate with an external device through the third interface devices to communicate.
The mobile platform according to claim 13, wherein the hard-core processor is further configured to acquire data from an external device through the third interface, and send the data acquired from the external device to the first An FPGA module, and the first FPGA module processes data acquired from the external device.
The movable platform according to claim 13 or 14, wherein the hard-core processor is further configured to acquire data acquired and/or output by the first FPGA module, and The data acquired and/or output by the module is sent to the external device through the third interface.
The movable platform according to claim 13, wherein the third interface comprises at least one of the following: a USB interface, an Ethernet interface, and a PCIe interface.
A verification device for chip design, comprising:

a first FPGA module, capable of writing a functional program file to be configured as a functional subsystem, where the functional subsystem is used to execute a functional task corresponding to the functional program file;

A hard-core processor, connected to the first FPGA module, is configured to execute a computer program and schedule the first FPGA module when executing the computer program.
The verification device according to claim 17, wherein a plurality of the first FPGA modules are connected in a ring topology, and the hard core processor is connected to one of the first FPGA modules.
The verification device according to claim 17 or 18, wherein the functional subsystem includes at least one of the following: a control subsystem, an image signal processing subsystem, and a peripheral subsystem.
The verification device according to claim 17, further comprising:

A second FPGA module, the hard-core processor is connected to the first FPGA module through the second FPGA module, and the second FPGA module is used to forward the hard-core processor and/or the first FPGA Control information and/or data between modules.
The verification apparatus according to claim 20, wherein each of the plurality of first FPGA modules is connected to the second FPGA module.
The verification apparatus according to claim 21, wherein a plurality of the first FPGA modules communicate concurrently with the second FPGA module through the second FPGA module.
The verification device according to claim 20, wherein the second FPGA module and the hard core processor are connected through a first interface, and the second FPGA module and the first FPGA module are connected through a second interface connection, the data transmission speed of the first interface is faster than the data transmission speed of the second interface.
The verification device according to claim 23, wherein the first FPGA module and the second FPGA module are connected through a SERDES interface.
The verification device according to claim 23, wherein the second FPGA module is connected to the hard core processor through an AXI bus interface.
The verification device according to any one of claims 20-25, wherein the second FPGA module and the hard-core processor are integrally provided.
The verification apparatus according to claim 26, wherein the second FPGA module and the hard core processor are located in the same SoC chip.
The verification apparatus according to any one of claims 17-27, wherein the hard-core processor includes at least one of the following: an ARM architecture processor, a PowerPC architecture processor, and an x86 architecture processor.
The verification apparatus according to any one of claims 17-28, wherein the hard-core processor further comprises a third interface, and the hard-core processor is further configured to communicate with an external device through the third interface to communicate.
The verification apparatus according to claim 29, wherein the hard-core processor is further configured to acquire data from an external device through the third interface, and send the data acquired from the external device to the first The FPGA module, and the first FPGA module process data acquired from the external device.
The verification device according to claim 29 or 30, wherein the hard-core processor is further configured to acquire the data acquired and/or output by the first FPGA module, and the first FPGA module The acquired data and/or the output data are sent to the external device through the third interface.
The verification apparatus according to claim 29, wherein the third interface comprises at least one of the following: a USB interface, an Ethernet interface, and a PCIe interface.
A verification method for chip design, comprising:

Get function program files;

Write the acquired functional program file into the first FPGA module of the verification device to obtain a functional subsystem;

obtain computer programs;

The hard-core processor configuring the verification apparatus executes the computer program and schedules the first FPGA module when executing the computer program.
The verification method according to claim 33, wherein a plurality of the first FPGA modules are connected in a ring topology, and the hard core processor is connected to one of the first FPGA modules.
The verification method according to claim 33 or 34, wherein the functional subsystem includes at least one of the following: a control subsystem, an image signal processing subsystem, and a peripheral subsystem.
The verification method according to claim 33, wherein the hard-core processor is connected to the first FPGA module through a second FPGA module, and the second FPGA module is used for forwarding the hard-core processor and the /or control information and/or data between the first FPGA modules.
The verification method according to claim 36, wherein each of the plurality of first FPGA modules is connected to the second FPGA module.
The verification method according to claim 37, wherein a plurality of the first FPGA modules communicate concurrently with the second FPGA module through the second FPGA module.
The verification method according to claim 36, wherein the second FPGA module and the hard core processor are connected through a first interface, and the second FPGA module and the first FPGA module are connected through a second interface connection, the data transmission speed of the first interface is faster than the data transmission speed of the second interface.
The verification method according to claim 39, wherein the first FPGA module and the second FPGA module are connected through a SERDES interface.
The verification method according to claim 39, wherein the second FPGA module is connected to the hard core processor through an AXI bus interface.
The verification method according to any one of claims 36-41, wherein the second FPGA module and the hard-core processor are integrally provided.
The verification method according to claim 42, wherein the second FPGA module and the hard core processor are located in the same SoC chip.
The verification method according to any one of claims 33-43, wherein the hard-core processor includes at least one of the following: an ARM architecture processor, a PowerPC architecture processor, and an x86 architecture processor.
The verification method according to any one of claims 33-44, wherein the method further comprises:

The hard-core processor communicates with an external device through a third interface of the hard-core processor.
The verification method according to claim 45, wherein the hard-core processor communicates with an external device through a third interface of the hard-core processor, comprising:

The hard-core processor obtains data from an external device through the third interface, and sends the data obtained from the external device to the first FPGA module, so that the first FPGA module can obtain data from the external device. data are processed.
The verification method according to claim 45 or 46, wherein the hard-core processor communicates with an external device through a third interface of the hard-core processor, comprising:

The hard-core processor acquires data acquired and/or output by the first FPGA module, and sends the data acquired and/or output by the first FPGA module to an external device through the third interface .