CN115412580A

CN115412580A - PHY chip working mode determining method and device and automatic driving vehicle

Info

Publication number: CN115412580A
Application number: CN202211215624.6A
Authority: CN
Inventors: 孟令帅; 王浩; 李支园
Original assignee: Apollo Intelligent Technology Beijing Co Ltd
Current assignee: Apollo Intelligent Technology Beijing Co Ltd
Priority date: 2022-09-30
Filing date: 2022-09-30
Publication date: 2022-11-29

Abstract

The disclosure provides a PHY chip working mode determining method and device and an automatic driving vehicle, and relates to the technical field of automatic driving, in particular to the field of automatic driving hardware. The implementation scheme is as follows: setting a first PHY chip to work in a preset working mode, wherein the first PHY chip is in communication connection with a second PHY chip of which the working mode is to be determined; determining whether the first PHY chip and the second PHY chip are successfully connected; and responsive to determining that the first PHY chip and the second PHY chip successfully establish a connection, determining the second PHY chip to operate in a corresponding operating mode corresponding to the predetermined operating mode.

Description

PHY chip working mode determining method and device and automatic driving vehicle

Technical Field

The present disclosure relates to the field of automatic driving technologies, and in particular, to a method and an apparatus for determining a working mode of a PHY (Port Physical Layer) chip, an electronic device, a computer-readable storage medium, a computer program product, a vehicle-mounted ethernet device, and an automatic driving vehicle.

Background

With the development of the automatic driving technology, users have made higher demands on communication connection in automatic driving vehicles. When the vehicle-mounted ethernet PHY chip of the autonomous vehicle is in communication connection with PHY chips of other devices, the operating mode of the PHY chip of the opposite device needs to be determined to achieve normal communication connection. The current automatic driving vehicle generally has no scheme for automatically determining the working mode of the PHY chip of the opposite-end device, so that a user needs to know the working mode of the PHY chip of the opposite-end device in advance, and then manually set the vehicle-mounted ethernet PHY chip of the automatic driving vehicle to the corresponding working mode, so that the communication connection can be normally performed. How to automatically determine the operating mode of the PHY chip of the peer device of the vehicle-mounted ethernet PHY chip of the autonomous vehicle is still one of research hotspots and difficulties in the industry.

Disclosure of Invention

The disclosure provides a method and a device for determining the working mode of a port physical layer (PHY) chip, an electronic device, a computer readable storage medium, a computer program product, a vehicle-mounted Ethernet device and an automatic driving vehicle.

According to an aspect of the present disclosure, a method for determining an operating mode of a port physical layer PHY chip is provided, including setting a first PHY chip to operate in a predetermined operating mode, the first PHY chip being communicatively connected to a second PHY chip of which the operating mode is to be determined; determining whether the first PHY chip and the second PHY chip are successfully connected; and in response to determining that the first PHY chip and the second PHY chip successfully establish a connection, determining that the second PHY chip is operating in a corresponding operating mode corresponding to the predetermined operating mode.

According to another aspect of the present disclosure, an operation mode determining apparatus of a port physical layer PHY chip is provided, including an operation mode setting module configured to set a first PHY chip to operate in a predetermined operation mode, the first PHY chip being communicatively connected to a second PHY chip of which an operation mode is to be determined; a connection determination module configured to determine whether the first PHY chip and the second PHY chip successfully establish a connection; and an operating mode determination module configured to determine that the second PHY chip operates in a corresponding operating mode corresponding to the predetermined operating mode in response to determining that the first PHY chip and the second PHY chip successfully establish the connection.

According to another aspect of the present disclosure, there is provided an electronic device comprising at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to cause the at least one processor to perform the method of the present disclosure as provided above.

According to another aspect of the present disclosure, there is provided a non-transitory computer readable storage medium having stored thereon computer instructions for causing a computer to perform the method of the present disclosure as provided above.

According to another aspect of the present disclosure, a computer program product is provided, comprising a computer program, wherein the computer program, when executed by a processor, implements the method of the present disclosure as provided above.

According to another aspect of the present disclosure, there is provided a vehicle ethernet device, including a vehicle ethernet PHY chip; a controller coupled to the vehicle ethernet PHY chip; and a vehicle-mounted Ethernet connector coupled with the vehicle-mounted Ethernet PHY chip and configured to communicate with a peer device of the vehicle-mounted Ethernet device; the controller is configured to perform the method of the present disclosure as provided above to determine an operating mode of the PHY chip of the peer device.

According to another aspect of the present disclosure, there is provided an autonomous vehicle comprising an onboard ethernet device as provided above in the present disclosure.

According to one or more embodiments of the disclosure, a PHY chip of a local device may automatically determine an operating mode of a PHY chip of a peer device to which the local device is communicatively connected.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the embodiments and, together with the description, serve to explain the exemplary implementations of the embodiments. The illustrated embodiments are for purposes of illustration only and do not limit the scope of the claims. Throughout the drawings, identical reference numbers designate similar, but not necessarily identical, elements.

FIG. 1 illustrates a schematic diagram of an exemplary system in which various methods described herein may be implemented, according to an embodiment of the present disclosure;

fig. 2 shows a flow chart of an operation mode determination method of a port physical layer PHY chip according to an embodiment of the present disclosure;

FIG. 3 illustrates a schematic diagram of an operational mode correspondence between a first PHY chip and a second PHY chip according to an embodiment of the disclosure;

FIG. 4 is a schematic diagram illustrating a predetermined set of operating modes of a first PHY chip corresponding to the manner in which a second PHY chip operates according to an embodiment of the disclosure;

fig. 5 shows a flow chart of a method for determining an operation mode of a port physical layer PHY chip according to another embodiment of the present disclosure;

fig. 6 is a block diagram illustrating an operation mode determination apparatus of a port physical layer PHY chip according to an embodiment of the present disclosure;

fig. 7 shows a schematic diagram of PHY chip communication connections according to an embodiment of the disclosure;

fig. 8 is a block diagram showing an operation mode determination apparatus of a port physical layer PHY chip according to another embodiment of the present disclosure;

FIG. 9 shows a block diagram of an in-vehicle Ethernet device according to an embodiment of the disclosure;

FIG. 10 illustrates a block diagram of an exemplary electronic device that can be used to implement embodiments of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

In the present disclosure, unless otherwise specified, the use of the terms "first", "second", and the like to describe various elements is not intended to limit the positional relationship, the temporal relationship, or the importance relationship of the elements, and such terms are used only to distinguish one element from another. In some examples, a first element and a second element may refer to the same instance of the element, and in some cases, based on the context, they may also refer to different instances.

The terminology used in the description of the various described examples in this disclosure is for the purpose of describing particular examples only and is not intended to be limiting. Unless the context clearly indicates otherwise, if the number of elements is not specifically limited, the element may be one or a plurality of. Furthermore, the term "and/or" as used in this disclosure is intended to encompass any and all possible combinations of the listed items.

In the related art, the method for determining the operation mode of the port physical layer PHY chip is generally achieved through autonomous knowledge of a user. The working mode of the PHY chip of the opposite-end equipment is known in advance by a user, and then the vehicle-mounted Ethernet PHY chip of the automatic driving vehicle is manually set to be the corresponding working mode, so that the normal communication connection between the vehicle-mounted Ethernet PHY chip of the automatic driving vehicle and the PHY chips of other equipment is realized.

In the implementation of the method, the vehicle-mounted Ethernet PHY chip of the automatic driving vehicle cannot automatically acquire the working mode of the PHY chip of the opposite-end equipment, and a user must manually configure the working mode of the vehicle-mounted Ethernet PHY chip each time the connecting equipment is replaced, so that the operation is complex; moreover, the PHY chip of the on-board ethernet of the autonomous vehicle cannot be communicatively connected to a device with unknown operating mode, and therefore, a method for automatically determining the operating mode of the PHY chip of the peer device is needed.

In view of the above technical problem, according to an aspect of the present disclosure, a method for determining an operation mode of a port physical layer PHY chip is provided.

Before describing in detail the method for determining an operating mode of a port physical layer PHY chip according to an embodiment of the present disclosure, a schematic diagram of an exemplary system in which the various methods and apparatus described herein may be implemented is first described in conjunction with fig. 1.

Embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

Fig. 1 illustrates a schematic diagram of an example system 100 in which various methods and apparatus described herein may be implemented in accordance with embodiments of the present disclosure. Referring to fig. 1, the system 100 includes a motor vehicle 110, a server 120, and one or more communication networks 130 coupling the motor vehicle 110 to the server 120.

In embodiments of the present disclosure, motor vehicle 110 may include a computing device and/or be configured to perform a method in accordance with embodiments of the present disclosure.

The server 120 may run one or more services or software applications capable of performing the operation mode determination method of the port physical layer PHY chip according to the embodiment of the present disclosure. In some embodiments, the server 120 may also provide other services or software applications, which may include non-virtual environments and virtual environments. In the configuration shown in fig. 1, server 120 may include one or more components that implement the functions performed by server 120. These components may include software components, hardware components, or a combination thereof, which may be executed by one or more processors. A user of motor vehicle 110 may, in turn, utilize one or more client applications to interact with server 120 to take advantage of the services provided by these components. It should be understood that a variety of different system configurations are possible, which may differ from system 100. Accordingly, fig. 1 is one example of a system for implementing the various methods described herein, and is not intended to be limiting.

The server 120 may include one or more general purpose computers, special purpose server computers (e.g., PC (personal computer) servers, UNIX servers, mid-end servers), blade servers, mainframe computers, server clusters, or any other suitable arrangement and/or combination. The server 120 may include one or more virtual machines running a virtual operating system, or other computing architecture involving virtualization (e.g., one or more flexible pools of logical storage that may be virtualized to maintain virtual storage for the server). In various embodiments, the server 120 may run one or more services or software applications that provide the functionality described below.

The computing units in server 120 may run one or more operating systems including any of the operating systems described above, as well as any commercially available server operating systems. The server 120 can also run any of a variety of additional server applications and/or mid-tier applications, including HTTP servers, FTP servers, CGI servers, JAVA servers, database servers, and the like.

In some embodiments, server 120 may include one or more applications to analyze and consolidate data feeds and/or event updates received from motor vehicle 110. Server 120 may also include one or more applications to display data feeds and/or real-time events via one or more display devices of motor vehicle 110.

Network 130 may be any type of network known to those skilled in the art that may support data communications using any of a variety of available protocols, including but not limited to TCP/IP, SNA, IPX, etc. By way of example only, the one or more networks 130 may be a satellite communication network, a Local Area Network (LAN), an ethernet-based network, a token ring, a Wide Area Network (WAN), the internet, a virtual network, a Virtual Private Network (VPN), an intranet, an extranet, a blockchain network, a Public Switched Telephone Network (PSTN), an infrared network, a wireless network (including, for example, bluetooth, wiFi), and/or any combination of these and other networks.

The system 100 may also include one or more databases 150. In some embodiments, these databases may be used to store data and other information. For example, one or more of the databases 150 may be used to store information such as audio files and video files. The data store 150 may reside in various locations. For example, the data store used by the server 120 may be local to the server 120, or may be remote from the server 120 and may communicate with the server 120 via a network-based or dedicated connection. The data store 150 may be of different types. In certain embodiments, the data store used by the server 120 may be a database, such as a relational database. One or more of these databases may store, update, and retrieve data to and from the database in response to the command.

In some embodiments, one or more of the databases 150 may also be used by applications to store application data. The databases used by the application may be different types of databases, such as key-value stores, object stores, or regular stores supported by a file system.

Motor vehicle 110 may include sensors 111 for sensing the surrounding environment. The sensors 111 may include one or more of the following sensors: visual cameras, infrared cameras, ultrasonic sensors, millimeter wave radar, and laser radar (LiDAR). Different sensors may provide different detection accuracies and ranges. The camera may be mounted in front of, behind, or otherwise on the vehicle. The visual cameras may capture the conditions inside and outside the vehicle in real time and present them to the driver and/or passengers. In addition, by analyzing the pictures captured by the visual camera, information such as traffic signal light indication, intersection situation, other vehicle running state, and the like can be acquired. The infrared camera can capture objects under night vision conditions. The ultrasonic sensors can be arranged on the periphery of the vehicle and used for measuring the distance between an object outside the vehicle and the vehicle by utilizing the characteristics of strong ultrasonic directionality and the like. The millimeter wave radar may be installed in front of, behind, or other positions of the vehicle for measuring the distance of an object outside the vehicle from the vehicle using the characteristics of electromagnetic waves. The lidar may be mounted in front of, behind, or otherwise in the vehicle for detecting object edges, shape information, and thus object identification and tracking. The radar apparatus can also measure a speed variation of the vehicle and the moving object due to the doppler effect.

Motor vehicle 110 may also include a communication device 112. The communication device 112 may include a satellite positioning module capable of receiving satellite positioning signals (e.g., beidou, GPS, GLONASS, and GALILEO) from the satellites 141 and generating coordinates based on these signals. The communication device 112 may also comprise modules for communicating with a mobile communication base station 142, and the mobile communication network may implement any suitable communication technology, such as current or evolving wireless communication technologies (e.g. 5G technologies) like GSM/GPRS, CDMA, LTE, etc. The communication device 112 may also have a Vehicle-to-Vehicle (V2X) networking or Vehicle-to-anything (V2X) module configured to enable, for example, vehicle-to-Vehicle (V2V) communication with other vehicles 143 and Vehicle-to-Infrastructure (V2I) communication with Infrastructure 144. Further, the communication device 112 may also have a module configured to communicate with a user terminal 145 (including but not limited to a smartphone, tablet, or wearable device such as a watch), for example, by wireless local area network using IEEE802.11 standards or bluetooth. Motor vehicle 110 may also access server 120 via network 130 using communication device 112.

Motor vehicle 110 may also include a control device 113. The control device 113 may include a processor, such as a Central Processing Unit (CPU) or a Graphics Processing Unit (GPU), or other special purpose processor, etc., in communication with various types of computer-readable storage devices or media. The control device 113 may include an autopilot system for automatically controlling various actuators in the vehicle. The autopilot system is configured to control a powertrain (not shown), a steering system, and a braking system, etc., of a motor vehicle 110 (not shown) via a plurality of actuators in response to inputs from a plurality of sensors 111 or other input devices to control acceleration, steering, and braking, respectively, without or with limited human intervention. Part of the processing functions of the control device 113 may be implemented by cloud computing. For example, some processing may be performed using an onboard processor while other processing may be performed using the computing resources in the cloud. The control device 113 may be configured to perform a method according to the present disclosure. Furthermore, the control apparatus 113 may be implemented as one example of a computing device on the motor vehicle side (client) according to the present disclosure.

The system 100 of fig. 1 may be configured and operated in various ways to enable application of the various methods and apparatus described in accordance with the present disclosure. The operation mode determination method of the port physical layer PHY chip according to an embodiment of the present disclosure is described in detail below.

Fig. 2 shows a flow chart of a method 200 for determining an operation mode of a port physical layer PHY chip according to an embodiment of the disclosure. As shown in fig. 2, the method 200 includes steps S201, S202, and S203.

In step S201, a first PHY chip is set to operate in a predetermined operating mode, and the first PHY chip is communicatively connected to a second PHY chip whose operating mode is to be determined.

In an example, the predetermined operating mode may instruct the first PHY chip to operate in a master mode or a slave mode at a predetermined transmission rate. The predetermined transmission rate may be a giga-rate or a hundred mega-rate. The predetermined transmission rate may also be a Multi G (Multi giga) rate, which may be 10G, 5G, or 2.5G.

In an example, the first PHY chip and the second PHY chip whose operation mode is to be determined may be communicatively connected by a twisted pair line by means of a connector of the first PHY chip and a connector of the second PHY chip whose operation mode is to be determined.

In step S202, it is determined whether the first PHY chip and the second PHY chip successfully establish a connection.

In an example, a connection status register may be provided in the first PHY chip to store connection status information of the PHY chip of the local device. The connection status information in the PHY connection status register of the first PHY chip may be "1" to indicate "connection was successfully established" and "0" to indicate "connection was not successfully established". Whether the first PHY chip and the second PHY chip are successfully connected may be determined by reading a PHY connection status register of the first PHY chip in the local device.

In an example, when the first PHY chip receives connection information sent by the second PHY chip, the first PHY chip may also be instructed to successfully establish a connection with the second PHY chip; and when the first PHY chip does not receive the connection information sent by the second PHY chip, indicating that the first PHY chip and the second PHY chip are not successfully connected.

It can be understood that, when the second PHY chip receives the connection information sent by the first PHY chip, the first PHY chip may also be instructed to successfully establish a connection with the second PHY chip; and when the second PHY chip does not receive the connection information sent by the first PHY chip, indicating that the first PHY chip and the second PHY chip are not successfully connected.

In step S203, in response to determining that the first PHY chip and the second PHY chip successfully establish a connection, it is determined that the second PHY chip operates in a corresponding operation mode corresponding to the predetermined operation mode.

In an example, a corresponding operating mode of the second PHY chip that corresponds to the predetermined operating mode of the first PHY chip may have the same transmission rate as the predetermined operating mode of the first PHY chip, but a different master/slave mode than the predetermined operating mode of the first PHY chip. That is, when the predetermined operation mode of the first PHY chip is a master mode of a predetermined transmission rate, the second PHY chip operates in a slave mode of the predetermined transmission rate; when the preset working mode of the first PHY chip is a slave mode of a preset transmission rate, the second PHY chip works in a master mode of the preset transmission rate.

According to the method for determining the working mode of the port physical layer PHY chip of the embodiment of the disclosure, the first PHY chip is in communication connection with the second PHY chip of which the working mode is to be determined by setting the predetermined working mode of the first PHY chip, the PHY working mode of the second PHY chip is determined reckonively based on the predetermined working mode of the first PHY chip corresponding to the first PHY chip when the connection between the first PHY chip and the second PHY chip is successfully established, the PHY chip of the vehicle-mounted ethernet local device can automatically acquire the working mode of the PHY chip of the opposite device, and therefore the device of which the working mode is unknown can be in communication connection conveniently. In addition, when the opposite terminal equipment connected with the local equipment is replaced, a user does not need to manually configure the working mode of a PHY chip of the opposite terminal equipment, and the operation is simplified.

Various aspects of a method for determining an operating mode of a port physical layer PHY chip according to an embodiment of the disclosure are further described below.

According to some embodiments, the predetermined operating mode may instruct the first PHY chip to operate in one of the master mode and the slave mode at a predetermined transmission rate, and the corresponding operating mode may instruct the second PHY chip to operate in the other of the master mode and the slave mode at the predetermined transmission rate.

In an example, the predetermined operating mode may instruct the first PHY chip to operate in a master mode or a slave mode at a predetermined transmission rate. In some embodiments, the predetermined transmission rate may be a giga-rate or a hundred megabit-rate. In other embodiments, the predetermined transmission rate may also be a Multi G rate, which may be, for example, 10G, 5G, or 2.5G.

Fig. 3 shows a schematic diagram of an operating mode correspondence between a first PHY chip and a second PHY chip according to an embodiment of the disclosure. The rule corresponding to the operation mode between the first PHY chip and the second PHY chip may be combined with step S203 described in fig. 2, for example.

As shown in fig. 3, the operation mode of the first PHY chip 310 may include a giga/master mode, a giga/slave mode, a hundred mega/master mode, a hundred mega/slave mode, a 10G/master mode, a 10G/slave mode, a 5G/master mode, a 5G/slave mode, a 2.5G/master mode, or a 2.5G/slave mode, and the operation mode of the second PHY chip 320 may also include a giga/master mode, a giga/slave mode, a hundred mega/master mode, a hundred mega/slave mode, a 10G/master mode, a 10G/slave mode, a 5G/master mode, a 5G/slave mode, a 2.5G/master mode, or a 2.5G/slave mode.

In an example, as shown in fig. 3, the correspondence rule of the operation mode between the first PHY chip 310 and the second PHY chip 320 may be: when the predetermined operating mode of the first PHY chip 310 is the gigabit/master mode, the second PHY chip 320 operates in the gigabit/slave mode; when the predetermined operation mode of the first PHY chip 310 is a gigabit/slave mode, the second PHY chip 320 operates in the gigabit/master mode; when the predetermined operating mode of the first PHY chip 310 is a hundred mega/master mode, the second PHY chip 320 operates in a hundred mega/slave mode; when the predetermined operating mode of the first PHY chip 310 is a hundred mega/slave mode, the second PHY chip 320 operates in a hundred mega/master mode; when the predetermined operation mode of the first PHY chip 310 is the 10G/master mode, the second PHY chip 320 operates in the 10G/slave mode; when the predetermined operation mode of the first PHY chip 310 is the 10G/slave mode, the second PHY chip 320 operates in the 10G/master mode; when the predetermined operation mode of the first PHY chip 310 is the 5G/master mode, the second PHY chip 320 operates in the 5G/slave mode; when the predetermined operation mode of the first PHY chip 310 is the 5G/slave mode, the second PHY chip 320 operates in the 5G/master mode; when the predetermined operation mode of the first PHY chip 310 is 2.5G/master mode, the second PHY chip 320 operates in 2.5G/slave mode; when the predetermined operation mode of the first PHY chip 310 is the 2.5G/slave mode, the second PHY chip 320 operates in the 2.5G/master mode.

According to the working mode determining process of the second PHY chip in the embodiment of the disclosure, by means of the corresponding rule of the working modes between the first PHY chip and the second PHY chip, based on the predetermined working mode of the first PHY chip when the connection is successfully established between the first PHY chip and the second PHY chip, the working mode of the second PHY chip can be determined by calculation, so that the PHY chip of the local device can automatically obtain the working mode of the PHY chip of the peer device.

According to some embodiments, the predetermined operating mode may be selected from a set of predetermined operating modes having a limited number. Correspondingly, the method for determining the operating mode of the port physical layer PHY chip of the present disclosure may further include: in response to determining that the first PHY chip has not successfully established a connection with the second PHY chip, the predetermined operating mode is changed to a remaining predetermined operating mode of the set of predetermined operating modes.

In an example, a set of a limited number of predetermined operational modes can be as shown in FIG. 3, including a gigabit/master mode, a gigabit/slave mode, a hundred mega/master mode, a hundred mega/slave mode, a 10G/master mode, a 10G/slave mode, a 5G/master mode, a 5G/slave mode, a 2.5G/master mode, and a 2.5G/slave mode.

In an example, each predetermined operational mode in a set having a limited number of predetermined operational modes may be numbered to order them, as shown in fig. 3, for example, a gigabit/master mode may be numbered as "0", a gigabit/slave mode may be numbered as "1", a hundred mega/master mode may be numbered as "2", a hundred mega/slave mode may be numbered as "3", a 10G/master mode may be numbered as "4", a 10G/slave mode may be numbered as "5", a 5G/master mode may be numbered as "6", a 5G/slave mode may be numbered as "7", a 2.5G/master mode may be numbered as "8", and a 2.5G/slave mode may be numbered as "9".

In an example, the predetermined operating modes may be sequentially changed to a next predetermined operating mode in the set of predetermined operating modes in an order numbered from 0 to 9. For example, the first PHY chip 310 may be first set to operate in a predetermined operating mode 0, i.e., gigabit/master mode; determining whether the first PHY chip 310 and the second PHY chip 320 successfully establish a connection; in response to determining that the first PHY chip 310 successfully establishes a connection with the second PHY chip 320, the second PHY chip 320 may be determined to operate in a gigabit/slave mode; in response to determining that the first PHY chip 310 and the second PHY chip 320 have not successfully established a connection, the predetermined operating mode is changed to a next predetermined operating mode of the set of predetermined operating modes, i.e., the first PHY chip 310 is set to operate in a predetermined operating mode 1, i.e., a gigabit/slave mode, and the determination of whether the first PHY chip 310 and the second PHY chip 320 have successfully established a connection is repeated.

It is to be understood that the ordering of the predetermined operating modes shown in fig. 3 is merely an example, and that the predetermined operating modes may be ordered differently than shown in fig. 3.

According to the predetermined operating mode modification and adjustment process of the embodiment of the disclosure, when the first PHY chip and the second PHY chip are not successfully connected, the predetermined operating mode is changed to the remaining predetermined operating modes in the predetermined operating mode set with the limited number, connection establishment with the PHY chip of the peer device in various different operating modes can be automatically attempted, so that the PHY operating mode of the second PHY chip can be determined by calculation based on the predetermined operating mode of the first PHY chip when the first PHY chip and the second PHY chip are successfully connected, and automatic acquisition of the operating mode of the PHY chip of the peer device by the PHY chip of the local device is realized.

According to some embodiments, the predetermined set of operating modes may be determined corresponding to whether the second PHY chip operates in a legacy manner or a compatible manner, which may provide a higher transmission rate than the legacy manner.

Fig. 4 is a schematic diagram illustrating a predetermined operation mode set of a first PHY chip corresponding to an operation manner of a second PHY chip according to an embodiment of the present disclosure. The predetermined set of operating modes of the first PHY chip may include, for example, the operating modes of the first PHY chip 310 shown in connection with fig. 3.

As shown in fig. 4, the second PHY chip may operate in a compatible mode 410 and a legacy mode 420. The compatible mode 410 and the legacy mode 420 may each correspond to a set of predetermined operating modes having a limited number.

In an example, as shown in fig. 4, corresponding to the second PHY chip operating in a compatible manner 410, the set of predetermined operating modes may include a gigabit/master mode, a gigabit/slave mode, a hundred mega/master mode, a hundred mega/slave mode, a 10G/master mode, a 10G/slave mode, a 5G/master mode, a 5G/slave mode, a 2.5G/master mode, and a 2.5G/slave mode. The predetermined set of operating modes may include a gigabit/master mode and a gigabit/slave mode, corresponding to the second PHY chip operating in a conventional manner 420.

It is understood that the predetermined operation mode set of the first PHY chip corresponding to the operation mode of the second PHY chip shown in fig. 4 is only an example, and the compatible mode 410 and the legacy mode 420 may also correspond to different predetermined operation mode sets from those shown in fig. 3, respectively.

According to the determination process of the predetermined operation mode set according to the embodiment of the present disclosure, the predetermined operation mode set is determined by corresponding to whether the second PHY chip operates in a legacy manner or in a compatible manner, and the first PHY chip can realize communication connection with the second PHY chip operating in the legacy manner and communication connection with the second PHY chip operating in the compatible manner, respectively. The corresponding preset working mode set is determined according to whether the second PHY chip works in a traditional mode or a compatible mode, so that the range of the corresponding preset working mode set can be narrowed, and the working mode of the PHY chip can be determined more efficiently.

According to some embodiments, the method for determining an operating mode of a port physical layer PHY chip of the present disclosure may further include: it is determined whether the second PHY chip is operating in a legacy or compatible manner.

According to the embodiment of the present disclosure, by determining whether the second PHY chip operates in a legacy manner or in a compatible manner, the corresponding predetermined operating mode set can be determined, so that the range of the corresponding predetermined operating mode set can be narrowed, making the determination of the operating mode of the PHY chip more efficient.

According to some embodiments, determining whether the second PHY chip is operating in a legacy manner or a compatible manner may include: reading a first register of a first PHY chip, the first register being configured to store transmission rate information corresponding to a legacy manner when a second PHY chip interacts with the first PHY chip in the legacy manner; determining whether the first register stores transmission rate information corresponding to a conventional manner; determining that the second PHY chip operates in a legacy manner in response to determining that the first register has transmission rate information corresponding to the legacy manner stored therein; and responsive to determining that no transmission rate information corresponding to the legacy manner is stored in the first register, determining that the second PHY core is operating in a compatible manner.

In an example, the first register of the first PHY chip may be a legacy mode register.

In an example, a first register of a first PHY chip may store information used to determine whether a second PHY chip is operating in a legacy manner. The stored information may be information regarding whether the first PHY chip interacts with and is transmitted by the second PHY chip regarding whether it is operating in a conventional manner during a debugging or training process prior to successful connection of the local device with the peer device, such as capability data, indicating that its rate may be up to giga or hundred megabytes, for example. The second PHY chip will only send the information to the first PHY chip when operating in a conventional manner.

By reading the first register of the first PHY chip, it can be reliably determined whether the second PHY chip is operating in a legacy manner or in a compatible manner, so that the corresponding set of predetermined operating modes can be determined, whereby the range of the corresponding set of predetermined operating modes can be narrowed, making the determination of the operating mode of the PHY chip more efficient.

According to some embodiments, determining whether the first PHY chip and the second PHY chip successfully establish the connection may include: reading a second register of the first PHY chip at least once within a preset time range, wherein the second register is configured to store information indicating a connection state between the first PHY chip and the second PHY chip; and determining whether the first PHY chip and the second PHY chip are successfully connected or not based on the information which is read in the preset time range and indicates the connection state between the first PHY chip and the second PHY chip.

In an example, the second register of the first PHY chip may be a status connection register.

In an example, the connection latency may be taken as a preset time. The connection latency may be preset to a time longer than the time to read the second register of the first PHY chip once, for example, the connection latency may be preset to a time to read the second register of the first PHY chip approximately 20 times, or the connection latency may be preset to 200 milliseconds, for example.

By reading the second register of the first PHY chip for multiple times within the preset time range to determine whether the connection between the first PHY chip and the second PHY chip is successfully established, the problem that the working mode of the PHY chip cannot be determined due to misjudgment of the connection state caused by accidental errors possibly occurring in the process of reading the second register of the first PHY chip can be avoided, and therefore the accuracy of judging whether the connection is successfully established is improved.

According to some embodiments, determining whether the first PHY chip and the second PHY chip successfully establish the connection based on the information indicating the connection status between the first PHY chip and the second PHY chip may include: determining that the first PHY chip and the second PHY chip have successfully established connection in response to reading information indicating that the first PHY chip and the second PHY chip are connected from the second register within a preset time range; and determining that the first PHY chip and the second PHY chip are not successfully connected in response to the information indicating that the first PHY chip and the second PHY chip are connected is not read from the second register within the preset time range.

In an example, the information stored in the second register of the first PHY chip indicating the connection state between the first PHY chip and the second PHY chip may be "1" to indicate "connection was successfully established" and "0" to indicate "connection was not successfully established".

By determining whether the first PHY chip and the second PHY chip are successfully connected based on the information indicating the connection state between the first PHY chip and the second PHY chip, the accuracy of determining the operating mode of the PHY chips can be improved.

Fig. 5 shows a flow chart of a method 500 for determining an operation mode of a port physical layer PHY chip according to another embodiment of the present disclosure. As shown in fig. 5, the method 500 may include steps S510, S520, S521, S522, S530, S540, S550, S560, S570, S571, S572, and S573.

At S510, a first register of the first PHY chip may be read, and the first register may be configured to store transmission rate information corresponding to a legacy manner when the second PHY chip interacts with the first PHY chip in the legacy manner.

After reading the first register of the first PHY chip, S520 may be executed to determine whether the first register stores therein transmission rate information corresponding to a conventional manner.

In response to determining that the transmission rate information corresponding to the legacy scheme is not stored in the first register, the second PHY chip may be determined to operate in a compatible manner at S521.

In response to determining that the transmission rate information corresponding to the legacy manner is stored in the first register, at S522, it may be determined that the second PHY chip operates in the legacy manner.

After determining whether the second PHY chip is operating in a legacy manner or a compatible manner, S530 may be performed to determine whether there is a limited number of predetermined sets of operating modes corresponding to whether the second PHY chip is operating in a legacy manner or a compatible manner.

The process may continue to perform S540. At S540, a predetermined operating mode may be selected and determined among the set of predetermined operating modes based on the set of predetermined operating modes determined at S530.

After determining the predetermined operating mode, S550 may be executed to set the first PHY chip to operate in the predetermined operating mode. The first PHY chip is in communication connection with a second PHY chip of which the working mode is to be determined.

The process may continue to execute S560. At S560, a second register of the first PHY chip may be read, and the second register may be configured to store information indicating a connection state between the first PHY chip and the second PHY chip.

After reading the second register of the first PHY chip, S570 may be performed to determine whether the first PHY chip and the second PHY chip are successfully connected.

In response to determining that the first PHY chip and the second PHY chip successfully establish a connection, S571 may be performed to determine the second PHY chip to operate in a corresponding operating mode corresponding to the predetermined operating mode.

In an example, the connection latency may be preset. S572 may be performed to determine whether a predetermined time is exceeded in response to no reading from the second register of information indicating that the first PHY chip and the second PHY chip are connected.

In response to the predetermined time not being exceeded, it may jump to perform S560 to read the second register of the first PHY chip again.

In response to the predetermined time being exceeded, i.e., the information indicating that the first PHY chip and the second PHY chip are connected is not read from the second register within the preset time range, the predetermined operation mode may be changed to the remaining predetermined operation modes in the predetermined operation mode set in S573. Then jumps to execute S550 to set the first PHY chip to operate in the changed predetermined operating mode.

Until it is determined that the first PHY chip and the second PHY chip successfully establish a connection, S550, S560, S570, S572, and S573 may be repeatedly performed according to the above logic until it is determined that the first PHY chip and the second PHY chip successfully establish a connection, so that the operation mode of the PHY chip is determined in S571.

According to some embodiments, the predetermined operating mode may also instruct the first PHY chip to operate in an auto-negotiation mode, the auto-negotiation mode indicating that the first PHY chip is to determine in a negotiated manner a transmission rate at which the first PHY chip is to operate in one of the master mode and the slave mode and to operate after a successful connection establishment with the second PHY chip, and the corresponding operating mode instructing the second PHY chip to operate in the other of the master mode and the slave mode at the transmission rate.

In an example, the transmission rate at which the first PHY chip operates in the master mode or the slave mode and operates, and the transmission rate at which the second PHY chip operates in the master mode or the slave mode and operates, may be determined by comparing the transmission performance of the first PHY chip to that of the second PHY chip. The lower performance one of the first PHY chip and the second PHY chip may be set to operate in a slave mode at a transmission rate appropriate for its performance, while the other one of the first PHY chip and the second PHY chip may be set to operate in a master mode at the same transmission rate.

By enabling the first PHY chip to work in the auto-negotiation mode, the flexibility of communication connection between the first PHY chip and the second PHY chip can be improved, and therefore the work mode of the PHY chip can be determined more efficiently.

According to some embodiments, the method for determining the operating mode of the port physical layer PHY chip of the present disclosure may be applied to conversion devices such as a vehicle-mounted ethernet to an industrial ethernet, an optical port, and the like, and may also be applied to products such as a vehicle-mounted ethernet diagnostic apparatus, a recorder, and the like, where these conversion devices and products may correspond to the local device having the first PHY chip in the embodiments of the present disclosure.

According to another aspect of the present disclosure, an operation mode determination apparatus of a port physical layer PHY chip is also provided.

Fig. 6 shows a block diagram of an operation mode determining apparatus 600 of a port physical layer PHY chip according to an embodiment of the present disclosure.

As shown in fig. 6, the operation mode determination device 600 includes: an operation mode setting module 610 configured to set a first PHY chip to operate in a predetermined operation mode, the first PHY chip being communicatively connected to a second PHY chip of which an operation mode is to be determined; a connection determination module 620 configured to determine whether the first PHY chip and the second PHY chip successfully establish a connection; and an operating mode determining module 630 configured to determine that the second PHY chip operates in a corresponding operating mode corresponding to the predetermined operating mode in response to determining that the first PHY chip and the second PHY chip successfully establish a connection.

Since the operation mode setting module 610, the connection determining module 620, and the operation mode determining module 630 in the operation mode determining apparatus 600 may respectively correspond to steps S201 to S203 as described in fig. 2, details of various aspects thereof are not repeated here.

In addition, the operation mode determining apparatus 600 and the modules included therein may further include further sub-modules, which will be described in detail below with reference to fig. 8.

Fig. 7 shows a schematic diagram of a PHY chip communication connection according to an embodiment of the disclosure.

As shown in fig. 7, the first PHY chip 711 may be a part of the local device 710, and the second PHY chip 721 for determining the operation mode may be a part of the peer device 720. The first PHY chip 711 and the second PHY chip 721 may be communicatively coupled via a twisted pair 730 by way of a local connector 712 of the local device 710 and a peer connector 722 of the peer device 720.

According to the embodiment of the disclosure, the first PHY chip is in communication connection with the second PHY chip of which the working mode is to be determined by setting the preset working mode of the first PHY chip, the PHY working mode of the second PHY chip is determined by calculation based on the preset working mode of the corresponding first PHY chip when the connection between the first PHY chip and the second PHY chip is successfully established, the PHY chip of the vehicle-mounted Ethernet local device can automatically acquire the working mode of the PHY chip of the opposite-end device, and therefore the vehicle-mounted Ethernet local device can be in communication connection with the device of which the working mode is unknown conveniently. In addition, when the opposite terminal equipment connected with the local equipment is replaced, a user does not need to manually configure the working mode of a PHY chip of the opposite terminal equipment, and the operation is simplified.

Fig. 8 is a block diagram illustrating an operation mode determination apparatus 800 of a port physical layer PHY chip according to another embodiment of the present disclosure.

As shown in fig. 8, apparatus 800 may include an operating mode setting module 810, a connection determination module 820, and an operating mode determination module 830. The operation mode setting module 810, the connection determining module 820 and the operation mode determining module 830 may correspond to the operation mode setting module 610, the connection determining module 620 and the operation mode determining module 630 shown in fig. 6, and thus the details thereof will not be described herein.

In an example, the predetermined operating mode may instruct the first PHY chip to operate in one of the master mode and the slave mode at a predetermined transmission rate, and the corresponding operating mode may instruct the second PHY chip to operate in the other of the master mode and the slave mode at the predetermined transmission rate.

Therefore, by means of the corresponding rule of the working modes between the first PHY chip and the second PHY chip, the working mode of the second PHY chip can be determined by calculation based on the preset working mode of the first PHY chip when the first PHY chip and the second PHY chip are successfully connected, and the PHY chip of the local device can automatically acquire the working mode of the PHY chip of the opposite device.

In an example, the predetermined operation mode may be selected from a set having a limited number of predetermined operation modes, and the operation mode determining apparatus 800 of the port physical layer PHY chip of the present disclosure may further include: an operating mode modification module 840 configured to change the predetermined operating mode to a remaining predetermined operating mode of the set of predetermined operating modes in response to determining that the first PHY chip is not successfully establishing a connection with the second PHY chip.

Therefore, when the connection between the first PHY chip and the second PHY chip is not successfully established, the preset working mode is changed into the rest preset working modes in the preset working mode set with the limited number, connection establishment with the PHY chip of the opposite terminal device in various different working modes can be automatically tried, therefore, the PHY working mode of the second PHY chip can be determined by calculation based on the preset working mode of the first PHY chip when the connection between the first PHY chip and the second PHY chip is successfully established, and the PHY chip of the local device can automatically acquire the working mode of the PHY chip of the opposite terminal device.

In an example, the predetermined set of operating modes may be determined corresponding to whether the second PHY chip operates in a legacy manner or a compatible manner, which may provide a higher transmission rate than the legacy manner.

Thus, by determining the predetermined set of operating modes corresponding to whether the second PHY chip is operating in a legacy manner or a compatible manner, the first PHY chip may effect a communication connection with the second PHY chip operating in the legacy manner and a communication connection with the second PHY chip operating in the compatible manner, respectively. The corresponding preset working mode set is determined according to whether the second PHY chip works in a traditional mode or a compatible mode, so that the range of the corresponding preset working mode set can be narrowed, and the working mode of the PHY chip can be determined more efficiently.

In an example, the operation mode determining apparatus 800 of the port physical layer PHY chip of the present disclosure may further include: an operation mode determination module 850 configured to determine whether the second PHY chip operates in a legacy mode or a compatible mode.

Thus, by determining whether the second PHY chip is operating in a legacy manner or in a compatible manner, the corresponding set of predetermined operating modes can be determined, thereby enabling a narrowing of the corresponding set of predetermined operating modes, making the determination of the operating mode of the PHY chip more efficient.

In an example, the operation mode determination module 850 may include: a first register reading module 851 configured to read a first register of the first PHY chip, the first register being configured to store transmission rate information corresponding to a conventional manner when the second PHY chip interacts with the first PHY chip in the conventional manner; an operation mode judging module 852 configured to determine whether the first register stores transmission rate information corresponding to a conventional mode; a legacy scheme determining module 853 configured to determine that the second PHY chip operates in a legacy scheme in response to determining that the first register stores therein transmission rate information corresponding to the legacy scheme; and a compatible manner determining module 854 configured to determine that the second PHY core is operating in a compatible manner in response to determining that the first register does not have transmission rate information corresponding to the legacy manner stored therein.

Thus, by reading the first register of the first PHY chip, it can be reliably determined whether the second PHY chip is operating in a legacy manner or in a compatible manner, so that the corresponding set of predetermined operating modes can be determined, whereby the range of the corresponding set of predetermined operating modes can be narrowed, making the determination of the operating mode of the PHY chip more efficient.

In an example, the connection determination module 820 may include: a second register reading module 821 configured to read a second register of the first PHY chip at least once within a preset time range, the second register being configured to store information indicating a connection state between the first PHY chip and the second PHY chip; and a connection state determination module 822 configured to determine whether the first PHY chip and the second PHY chip are successfully connected based on information indicating a connection state between the first PHY chip and the second PHY chip read within a preset time range.

Therefore, the second register of the first PHY chip is read for multiple times within the preset time range to determine whether the connection between the first PHY chip and the second PHY chip is successfully established, so that the problem that the working mode of the PHY chip cannot be determined due to misjudgment of the connection state caused by accidental errors possibly occurring in the process of reading the second register of the first PHY chip can be avoided, and the accuracy of judging whether the connection is successfully established is improved.

In an example, the connection status determination module 822 may include: a connection success determining module 822a configured to determine that the first PHY chip and the second PHY chip have successfully established a connection in response to reading, from the second register, information indicating that the first PHY chip and the second PHY chip are connected within a preset time range; and a connection failure determination module 822b configured to determine that the first PHY chip and the second PHY chip have not successfully established a connection in response to information indicating that the first PHY chip and the second PHY chip have been connected being not read from the second register within a preset time range.

Therefore, the accuracy of the work mode determination of the PHY chip can be improved by determining whether the connection between the first PHY chip and the second PHY chip is successfully established or not based on the information indicating the connection state between the first PHY chip and the second PHY chip.

In an example, the predetermined operating mode may also instruct the first PHY chip to operate in an auto-negotiation mode, which may indicate that the first PHY chip is to determine in a negotiated manner a transmission rate at which the first PHY chip is to operate in one of the master mode and the slave mode and to operate after a successful connection establishment with the second PHY chip, and the corresponding operating mode may instruct the second PHY chip to operate in the other of the master mode and the slave mode at the transmission rate.

Therefore, the first PHY chip works in the auto-negotiation mode, so that the flexibility of communication connection between the first PHY chip and the second PHY chip can be improved, and the work mode of the PHY chip can be determined more efficiently.

According to another aspect of the present disclosure, there is also provided an electronic device including: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of the above embodiments.

According to another aspect of the present disclosure, there is also provided a non-transitory computer readable storage medium storing computer instructions for causing a computer to perform the method in the above-described embodiments.

According to another aspect of the present disclosure, there is also provided a computer program product comprising a computer program, wherein the computer program, when executed by a processor, implements the method in the above embodiments.

According to another aspect of the present disclosure, a vehicle-mounted ethernet device is also provided.

Fig. 9 shows a block diagram of an in-vehicle ethernet device 900 according to an embodiment of the present disclosure.

As shown in fig. 9, in-vehicle ethernet device 900 may include: an on-board ethernet PHY chip 910; a controller 920 coupled to the in-vehicle ethernet PHY chip 910; and a vehicle ethernet connector 930 coupled to vehicle ethernet PHY chip 910 configured to communicate with a peer device of vehicle ethernet device 900; the controller 920 may be configured to perform the method in the above embodiment to determine an operating mode of a PHY chip of a peer device.

According to another aspect of the present disclosure, there is also provided an autonomous vehicle including the in-vehicle ethernet device in the above embodiments.

Referring to fig. 10, a block diagram of a structure of an electronic device 1000, which may be a server or a client of the present disclosure, which is an example of a hardware device that may be applied to aspects of the present disclosure, will now be described. Electronic device is intended to represent various forms of digital electronic computer devices, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions, are meant to be examples only, and are not intended to limit implementations of the disclosure described and/or claimed herein.

As shown in fig. 10, the electronic device 1000 includes a computing unit 1001 that can perform various appropriate actions and processes according to a computer program stored in a Read Only Memory (ROM) 1002 or a computer program loaded from a storage unit 1008 into a Random Access Memory (RAM) 1003. In the RAM1003, various programs and data necessary for the operation of the electronic apparatus 1000 can be stored. The calculation unit 1001, the ROM 1002, and the RAM1003 are connected to each other by a bus 1004. An input/output (I/O) interface 1005 is also connected to bus 1004.

A number of components in the electronic device 1000 are connected to the I/O interface 1005, including: input section 1006, output section 1007, storage section 1008, and communication section 1009. The input unit 1006 may be any type of device capable of inputting information to the electronic device 1000, and the input unit 1006 may receive input numeric or character information and generate key signal inputs related to user settings and/or function controls of the electronic device, and may include, but is not limited to, a mouse, a keyboard, a touch screen, a track pad, a track ball, a joystick, a microphone, and/or a remote controller. Output unit 1007 may be any type of device capable of presenting information and may include, but is not limited to, a display, speakers, a video/audio output terminal, a vibrator, and/or a printer. The storage unit 1008 may include, but is not limited to, a magnetic disk, an optical disk. The communications unit 1009 allows the electronic device 1000 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunications networks, and may include, but is not limited to, modems, network cards, infrared communication devices, wireless communication transceivers, and/or chipsets, such as bluetooth (TM) devices, 802.11 devices, wiFi devices, wiMax devices, cellular communication devices, and/or the like.

Computing unit 1001 may be a variety of general and/or special purpose processing components with processing and computing capabilities. Some examples of the computing unit 1001 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various dedicated Artificial Intelligence (AI) computing chips, various computing units running machine learning model algorithms, a Digital Signal Processor (DSP), and any suitable processor, controller, microcontroller, and so forth. The calculation unit 1001 executes the respective methods and processes described above, such as the operation mode determination method of the port physical layer PHY chip. For example, in some embodiments, the method of determining an operating mode of a port physical layer PHY chip may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 1008. In some embodiments, part or all of the computer program may be loaded and/or installed onto electronic device 1000 via ROM 1002 and/or communications unit 1009. When the computer program is loaded into the RAM1003 and executed by the computing unit 1001, one or more steps of the operation mode determination method of the port physical layer PHY chip described above may be performed. Alternatively, in other embodiments, the calculation unit 1001 may be configured by any other suitable means (e.g. by means of firmware) to perform the operation mode determination method of the port physical layer PHY chip.

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuitry, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), system on a chip (SOCs), complex Programmable Logic Devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs that are executable and/or interpretable on a programmable system including at least one programmable processor, which may be special or general purpose, receiving data and instructions from, and transmitting data and instructions to, a storage system, at least one input device, and at least one output device.

Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/operations specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which a user can provide input to the computer. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic, speech, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a back-end component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such back-end, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), the Internet, and blockchain networks.

The computer system may include clients and servers. A client and server are generally remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server may be a cloud server, a server of a distributed system, or a server with a combined blockchain.

It should be understood that various forms of the flows shown above may be used, with steps reordered, added, or deleted. For example, the steps described in the present disclosure may be performed in parallel, sequentially or in different orders, and are not limited herein as long as the desired results of the technical solutions disclosed in the present disclosure can be achieved.

Although embodiments or examples of the present disclosure have been described with reference to the accompanying drawings, it is to be understood that the above-described methods, systems and apparatus are merely exemplary embodiments or examples and that the scope of the present invention is not limited by these embodiments or examples, but only by the claims as issued and their equivalents. Various elements in the embodiments or examples may be omitted or may be replaced with equivalents thereof. Further, the steps may be performed in an order different from that described in the present disclosure. Further, various elements in the embodiments or examples may be combined in various ways. It is important that as technology evolves, many of the elements described herein may be replaced with equivalent elements that appear after the present disclosure.

Claims

1. A method for determining the working mode of a port physical layer (PHY) chip comprises the following steps:

setting a first PHY chip to work in a preset working mode, wherein the first PHY chip is in communication connection with a second PHY chip of which the working mode is to be determined;

determining whether the first PHY chip and the second PHY chip successfully establish a connection; and

in response to determining that the first PHY chip and the second PHY chip successfully establish a connection, determining that the second PHY chip operates in a corresponding operating mode corresponding to the predetermined operating mode.

2. The method of claim 1, wherein the predetermined operating mode instructs the first PHY chip to operate in one of a master mode and a slave mode at a predetermined transmission rate, and

wherein the corresponding operating mode instructs the second PHY chip to operate in the other of the master mode and the slave mode at the predetermined transmission rate.

3. The method of claim 1 or 2, wherein the predetermined operating mode is selected from a set of a limited number of predetermined operating modes, wherein the method further comprises:

in response to determining that the first PHY chip and the second PHY chip have not successfully established a connection, changing the predetermined operating mode to a remaining predetermined operating mode of the set of predetermined operating modes.

4. The method of claim 3, wherein the predetermined set of operating modes is determined corresponding to whether the second PHY chip operates in a legacy manner or a compatible manner, wherein the compatible manner provides a higher transmission rate than the legacy manner.

5. The method of claim 4, further comprising: determining whether the second PHY chip is to operate in the legacy mode or the compatible mode.

6. The method of claim 5, wherein the determining whether the second PHY chip is to operate in the legacy manner or the compatible manner comprises:

reading a first register of the first PHY chip, wherein the first register is configured to store transmission rate information corresponding to the legacy mode when the second PHY chip interacts with the first PHY chip in the legacy mode;

determining whether the first register stores the transmission rate information corresponding to the legacy scheme;

determining that the second PHY chip is operating in the legacy mode in response to determining that the transmission rate information corresponding to the legacy mode is stored in the first register; and

determining that the second PHY chip is operating in the compatible manner in response to determining that the transmission rate information corresponding to the legacy manner is not stored in the first register.

7. The method of any of claims 1-6, wherein the determining whether the first PHY chip and the second PHY chip successfully establish a connection comprises:

reading a second register of the first PHY chip at least once within a preset time range, wherein the second register is configured to store information indicating a connection state between the first PHY chip and the second PHY chip; and

determining whether the first PHY chip and the second PHY chip are successfully connected or not based on the information which is read in the preset time range and indicates the connection state between the first PHY chip and the second PHY chip.

8. The method of claim 7, the determining whether the first PHY chip and the second PHY chip successfully establish a connection based on the information indicative of a connection status between the first PHY chip and the second PHY chip comprising:

determining that the first PHY chip and the second PHY chip have successfully established a connection in response to reading the information indicating that the first PHY chip and the second PHY chip are connected from the second register within the preset time range; and

determining that the first PHY chip and the second PHY chip have not successfully established a connection in response to the information indicating that the first PHY chip and the second PHY chip have been connected not being read from the second register within the preset time range.

9. The method of claim 1, wherein the predetermined operating mode indicates that the first PHY chip is operating in an auto-negotiation mode, the auto-negotiation mode indicating that the first PHY chip is to determine in a negotiated manner a transmission rate at which the first PHY chip is operating in and operating in one of a master mode and a slave mode after successfully establishing a connection with the second PHY chip, and wherein

Wherein the corresponding operating mode instructs the second PHY chip to operate in the other of the master mode and the slave mode at the transmission rate.

10. An operation mode determination device of a port physical layer (PHY) chip comprises the following steps:

the system comprises an operating mode setting module, a first PHY chip and a second PHY chip, wherein the operating mode setting module is configured to set the first PHY chip to operate in a preset operating mode, and the first PHY chip is in communication connection with the second PHY chip of which the operating mode is to be determined;

a connection determination module configured to determine whether the first PHY chip and the second PHY chip successfully establish a connection; and

an operating mode determination module configured to determine that the second PHY chip operates in a corresponding operating mode corresponding to the predetermined operating mode in response to determining that the first PHY chip and the second PHY chip successfully establish a connection.

11. The apparatus of claim 10, wherein the predetermined operating mode instructs the first PHY chip to operate in one of a master mode and a slave mode at a predetermined transmission rate, and

12. The apparatus of claim 10 or 11, wherein the predetermined operating mode is selected from a set of a limited number of predetermined operating modes, wherein the apparatus further comprises:

an operating mode modification module configured to change the predetermined operating mode to a remaining predetermined operating mode of the set of predetermined operating modes in response to determining that the first PHY chip and the second PHY chip have not successfully established a connection.

13. The apparatus of claim 12, wherein the predetermined set of operating modes is determined corresponding to whether the second PHY chip is to operate in a legacy manner or in a compatible manner, wherein the compatible manner provides a higher transmission rate than the legacy manner.

14. The apparatus of claim 13, further comprising: an operation mode determination module configured to determine whether the second PHY chip operates in the legacy mode or the compatible mode.

15. The apparatus of claim 14, wherein the mode of operation determination module comprises:

a first register reading module configured to read a first register of the first PHY chip, wherein the first register is configured to store transmission rate information corresponding to the legacy mode when the second PHY chip interacts with the first PHY chip in the legacy mode;

a working mode judging module configured to determine whether the first register stores the transmission rate information corresponding to the legacy mode;

a legacy scheme determination module configured to determine that the second PHY chip operates in the legacy scheme in response to determining that the transmission rate information corresponding to the legacy scheme is stored in the first register; and

a compatible manner determination module configured to determine that the second PHY core is to operate in the compatible manner in response to determining that the transmission rate information corresponding to the legacy manner is not stored in the first register.

16. The apparatus of any of claims 10-15, wherein the connection determination module comprises:

a second register reading module configured to read a second register of the first PHY chip at least once within a preset time range, wherein the second register is configured to store information indicating a connection state between the first PHY chip and the second PHY chip; and

a connection state determination module configured to determine whether the first PHY chip and the second PHY chip are successfully connected based on the information indicating the connection state between the first PHY chip and the second PHY chip read within the preset time range.

17. The apparatus of claim 16, the connection status determination module comprising:

a connection success determination module configured to determine that the first PHY chip and the second PHY chip have successfully established a connection in response to reading the information indicating that the first PHY chip and the second PHY chip are connected from the second register within the preset time range; and

a connection failure determination module configured to determine that the first PHY chip and the second PHY chip have not successfully established a connection in response to the information indicating that the first PHY chip and the second PHY chip have been connected being not read from the second register within the preset time range.

18. The apparatus of claim 10, wherein the predetermined operating mode indicates that the first PHY chip is operating in an auto-negotiation mode, the auto-negotiation mode indicating that the first PHY chip is to determine in a negotiated manner a transmission rate at which the first PHY chip is operating in and operating in one of a master mode and a slave mode after successfully establishing a connection with the second PHY chip, and wherein

19. An electronic device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein

The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-9.

20. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-9.

21. A computer program product comprising a computer program, wherein the computer program realizes the method according to any of claims 1-9 when executed by a processor.

22. An in-vehicle ethernet device comprising:

a vehicle-mounted Ethernet PHY chip;

a controller coupled to the in-vehicle Ethernet PHY chip; and

a vehicle-mounted Ethernet connector coupled to the vehicle-mounted Ethernet PHY chip and configured to communicate with a peer device of the vehicle-mounted Ethernet device;

wherein the controller is configured to perform the method of any of claims 1-9 to determine an operating mode of a PHY chip of the peer device.

23. An autonomous vehicle comprising the onboard ethernet device of claim 22.