CN107196642A - A kind of tri-state generation circuit - Google Patents
A kind of tri-state generation circuit Download PDFInfo
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- CN107196642A CN107196642A CN201710395043.8A CN201710395043A CN107196642A CN 107196642 A CN107196642 A CN 107196642A CN 201710395043 A CN201710395043 A CN 201710395043A CN 107196642 A CN107196642 A CN 107196642A
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- diode
- termination
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- resistance
- phase inverter
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/017509—Interface arrangements
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- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
The invention provides a kind of tri-state generation circuit, belong to semiconductor integrated circuit technical field.The circuit includes：The termination power of first resistor one, the anode of another diode of termination first；The negative terminal of first diode connects the anode of the second diode；The negative terminal of second diode connects input port；One termination input port of second resistance, other end ground connection；The termination power of 3rd resistor one, the drain electrode and the input of the first phase inverter of another NMOS tube of termination first；The grid of first NMOS tube connects input port, source ground；The output of first phase inverter connects the first output port；The source electrode of first PMOS connects power supply, and grid connects input port, and drain electrode connects one end of the 4th resistance and the input of the second phase inverter；The other end ground connection of 4th resistance；The output of second phase inverter connects the second output port.The input IO of the tri-state generation circuit can just characterize 3 logic states with an IO, so as to reduce chip area, save cost.
Description
Technical field
The invention belongs to semiconductor integrated circuit technical field, and in particular to a kind of tri-state generation circuit.
Background technology
In many large-scale circuit systems, the particularly system of processor work, functional module is very more, necessarily causes
The signal of input and output increases, for chip, and this necessarily causes the increase of chip I/O port number.In IO due to including driving and
ESD logics, its area is generally larger, for much control class chips, because IO numbers are a lot, necessarily causes chip power-consumption
Increase, the cost increase of chip package the problems such as.
In view of the above-mentioned problems, traditional solution is to use I/O port multiplexing technology, this technology solves chip well
The problem of area is limited to IO numbers, but it also increases inner control logic simultaneously.
The content of the invention
To solve the too many technical problem of I/O port number in existing large scale circuit system, the invention provides a kind of production of tri-state
Raw circuit.
A kind of tri-state generation circuit, including：First resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4,
One diode D1, the second diode D2, the first nmos pass transistor N1, the first PMOS transistor P1, the first phase inverter INV1, second
Phase inverter INV2；The termination power V of first resistor R1 mono-DD, the first diode D1 of another termination anode；First diode D1's is negative
Terminate the second diode D2 anode；Second diode D2 negative terminal meets input port IN；A second resistance R2 termination input
Port IN, other end ground connection；The termination powers of 3rd resistor R3 mono-, another the first nmos pass transistor of termination N1 drain electrode and first anti-
Phase device INV1 input；First nmos pass transistor N1 grid meets input port IN, source ground；First phase inverter INV1's is defeated
Go out to connect the first output port OUT1；First PMOS transistor P1 source electrode meets power supply VDD, grid meets input port IN, and drain electrode connects the
Four resistance R4 one end and the second phase inverter INV2 input；4th resistance R4 other end ground connection；Second phase inverter INV2's
Output meets the second output port OUT2.
In the tri-state generation circuit of the present invention, when input port IN is low, the first nmos pass transistor N1 cut-offs, first
PMOS transistor P1 is turned on, and the first output port OUT1 and the second output port OUT2 are respectively 0 and 0；When input port IN is
Gao Shi, the first nmos pass transistor N1 are turned on, the first PMOS transistor P1 cut-offs, the first output port OUT1 and the second output port
OUT2 is respectively 1 and 1；When input port IN is hanging, the voltage on input port IN subtracts two diodes for supply voltage
Forward voltage, as long as supply voltage is sufficiently high, the first nmos pass transistor N1 and the first PMOS transistor P1 can be turned on, at this moment
First output port OUT1 and the second output port OUT2 is respectively 1 and 0.Thus three logic shapes have been levied with an I O table
State.
In theory, a 2 value IO can only characterize two logic states, and characterizing 3 logic states at least needs two IO, and
The input IO of tri-state generation circuit can just characterize 3 logic states with an IO, thus reduce chip area, saved into
This.
Brief description of the drawings
Fig. 1 is the tri-state generation circuit structural representation that embodiment of the present invention is provided.
Embodiment
To make the object, technical solutions and advantages of the present invention of greater clarity, with reference to embodiment and join
According to accompanying drawing, the present invention is described in more detail.It should be understood that these descriptions are merely illustrative, and it is not intended to limit this hair
Bright scope.In addition, in the following description, the description to known features and technology is eliminated, to avoid unnecessarily obscuring this
The concept of invention.
In order to which the problem of I/O port is multiplexed can be solved, and the inner control logic of chip is not increased, the invention provides one
Tri-state generation circuit is planted, as shown in figure 1, including：First resistor R1, second resistance R2,3rd resistor R3, the 4th resistance R4,
One diode D1, the second diode D2, the first nmos pass transistor N1, the first PMOS transistor P1, the first phase inverter INV1, second
Phase inverter INV2；The termination power V of first resistor R1 mono-DD, the first diode D1 of another termination anode；First diode D1's is negative
Terminate the second diode D2 anode；Second diode D2 negative terminal meets input port IN；A second resistance R2 termination input
Port IN, other end ground connection；The termination powers of 3rd resistor R3 mono-, another the first nmos pass transistor of termination N1 drain electrode and first anti-
Phase device INV1 input；First nmos pass transistor N1 grid meets input port IN, source ground；First phase inverter INV1's is defeated
Go out to connect the first output port OUT1；First PMOS transistor P1 source electrode meets power supply VDD, grid meets input port IN, and drain electrode connects the
Four resistance R4 one end and the second phase inverter INV2 input；4th resistance R4 other end ground connection；Second phase inverter INV2's
Output meets the second output port OUT2.
In the tri-state generation circuit of the present invention, when input port IN is low, the first nmos pass transistor N1 cut-offs, first
PMOS transistor P1 is turned on, and the first output port OUT1 and the second output port OUT2 are respectively 0 and 0；When input port IN is
Gao Shi, the first nmos pass transistor N1 are turned on, the first PMOS transistor P1 cut-offs, the first output port OUT1 and the second output port
OUT2 is respectively 1 and 1；When input port IN is hanging, the voltage on input port IN subtracts two diodes for supply voltage
Forward voltage, as long as supply voltage is sufficiently high, the first nmos pass transistor N1 and the first PMOS transistor P1 can be turned on, at this moment
First output port OUT1 and the second output port OUT2 is respectively 1 and 0.Thus three logic shapes have been levied with an I O table
State.
In theory, a 2 value IO can only characterize two logic states, and characterizing 3 logic states at least needs two IO, and
The input IO of tri-state generation circuit can just characterize 3 logic states with an IO, thus reduce chip area, saved into
This.
It should be appreciated that the above-mentioned embodiment of the present invention is used only for exemplary illustration or explains the present invention's
Principle, without being construed as limiting the invention.Therefore, that is done without departing from the spirit and scope of the present invention is any
Modification, equivalent substitution, improvement etc., should be included in the scope of the protection.In addition, appended claims purport of the present invention
Covering the whole changes fallen into scope and border or this scope and the equivalents on border and repairing
Change example.
Claims (1)
1. a kind of tri-state generation circuit, it is characterised in that including：First resistor R1, second resistance R2,3rd resistor R3, the 4th
Resistance R4, the first diode D1, the second diode D2, the first nmos pass transistor N1, the first PMOS transistor P1, the first phase inverter
INV1, the second phase inverter INV2；The termination power V of first resistor R1 mono-DD, the first diode D1 of another termination anode；One or two
Pole pipe D1 negative terminal connects the second diode D2 anode；Second diode D2 negative terminal meets input port IN；Second resistance R2's
One termination input port IN, other end ground connection；The termination powers of 3rd resistor R3 mono-, another the first nmos pass transistor of termination N1 leakage
Pole and the first phase inverter INV1 input；First nmos pass transistor N1 grid meets input port IN, source ground；First is anti-phase
Device INV1 output meets the first output port OUT1；First PMOS transistor P1 source electrode meets power supply VDD, grid connects input port
IN, drain electrode connects the 4th resistance R4 one end and the second phase inverter INV2 input；4th resistance R4 other end ground connection；Second is anti-
Phase device INV2 output meets the second output port OUT2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710395043.8A CN107196642A (en) | 2017-05-30 | 2017-05-30 | A kind of tri-state generation circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710395043.8A CN107196642A (en) | 2017-05-30 | 2017-05-30 | A kind of tri-state generation circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107196642A true CN107196642A (en) | 2017-09-22 |
Family
ID=59875991
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710395043.8A Pending CN107196642A (en) | 2017-05-30 | 2017-05-30 | A kind of tri-state generation circuit |
Country Status (1)
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| CN (1) | CN107196642A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201698195U (en) * | 2010-05-28 | 2011-01-05 | 宁波海诚电器有限公司 | Expansion circuit of single chip microcomputer IO ports |
| CN202058138U (en) * | 2010-12-10 | 2011-11-30 | 深圳市广和通实业发展有限公司 | Serial data interface multiplexing device |
| US8174284B1 (en) * | 2010-03-03 | 2012-05-08 | Altera Corporation | Repairable IO in an integrated circuit |
| CN103439905A (en) * | 2013-08-29 | 2013-12-11 | 广州视源电子科技股份有限公司 | IO input port expansion circuit |
| US20140229649A1 (en) * | 2011-12-15 | 2014-08-14 | Sundeep Raniwala | Implementing io expansion cards |
| US20150346279A1 (en) * | 2013-05-06 | 2015-12-03 | International Business Machines Corporation | Managing redundancy repair using boundary scans |
| CN206117636U (en) * | 2016-10-18 | 2017-04-19 | 佛山市顺德区美的电热电器制造有限公司 | IO output port expander circuit and domestic appliance |
-
2017
- 2017-05-30 CN CN201710395043.8A patent/CN107196642A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8174284B1 (en) * | 2010-03-03 | 2012-05-08 | Altera Corporation | Repairable IO in an integrated circuit |
| CN201698195U (en) * | 2010-05-28 | 2011-01-05 | 宁波海诚电器有限公司 | Expansion circuit of single chip microcomputer IO ports |
| CN202058138U (en) * | 2010-12-10 | 2011-11-30 | 深圳市广和通实业发展有限公司 | Serial data interface multiplexing device |
| US20140229649A1 (en) * | 2011-12-15 | 2014-08-14 | Sundeep Raniwala | Implementing io expansion cards |
| US20150346279A1 (en) * | 2013-05-06 | 2015-12-03 | International Business Machines Corporation | Managing redundancy repair using boundary scans |
| CN103439905A (en) * | 2013-08-29 | 2013-12-11 | 广州视源电子科技股份有限公司 | IO input port expansion circuit |
| CN206117636U (en) * | 2016-10-18 | 2017-04-19 | 佛山市顺德区美的电热电器制造有限公司 | IO output port expander circuit and domestic appliance |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170922 |