CN107148159A - The method for manufacturing printed substrate - Google Patents
The method for manufacturing printed substrate Download PDFInfo
- Publication number
- CN107148159A CN107148159A CN201710594161.1A CN201710594161A CN107148159A CN 107148159 A CN107148159 A CN 107148159A CN 201710594161 A CN201710594161 A CN 201710594161A CN 107148159 A CN107148159 A CN 107148159A
- Authority
- CN
- China
- Prior art keywords
- film
- catch point
- printed substrate
- via hole
- welding resistance
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/285—Permanent coating compositions
- H05K3/287—Photosensitive compositions
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Non-Metallic Protective Coatings For Printed Circuits (AREA)
Abstract
The invention provides a kind of method for manufacturing printed substrate, including：Step (a) carries out silk-screen printing to printed substrate；Step (b) the preliminary dryings printed substrate；The printed substrate and the first film aligning are exposed by step (c)；Step (d) rinses the printed substrate with developer solution and developed；The printed substrate and the second film aligning are exposed by step (e)；And step (f) rinses the printed substrate with developer solution again and developed.The problem of can effectively improving via hole plug-hole by using method provided by the present invention.
Description
Technical field
The present invention relates to the method for manufacture printed substrate, more particularly to a kind of method that solder mask is made on PCB.
Background technology
Variation and precise treatment development with electronic product, printed substrate（Printed circuit board,
PCB）Also the direction towards variation and precise treatment is developed.Many electronic products require PCB a part of via hole in conducting work(
The functions such as bearing function test, radiating are also needed on the basis of energy, in other words, the via hole of this part carrying multi-functional is not
Can be by solder mask plug-hole.In the prior art, the method typically printed using white twine carries out the printing of solder mask.However, white
Twine print is easily caused part ink and entered in the less via hole of size, causes plug-hole, influences PCB performance.
Have at present a kind of method for avoiding plug-hole be before ink for screen printing is carried out to PCB plate face, make one it is special
Silk-screen half tone, be provided with the silk-screen half tone and cross the corresponding catch point in hole site with wiring board, by these catch points by wiring board
On via block, so as to realize that, in follow-up ink for screen printing, ink can not be entered in via.But this method requires silk
The design of printed network version need to correspond to PCB, and silk-screen half tone does not have versatility, and cost of manufacture is high, adds Making programme.
Also a kind of method for avoiding plug-hole is exposed by using film aligning, the solder mask of reservation is occurred light and is consolidated
Change, the solder mask not retained（The ink such as entered in via hole）Blocked not photosensitive, then washed by the weak base that develops by the film
Wash without photosensitive ink, so as to avoid plug-hole.But this method is not suitable for copper thickness in 2 OZ（About 70 microns）More than
Plate.Because silk-screen pressure is larger in its process, more ink are made to enter in via hole, normal development only rinses one
It is secondary, it is impossible to rinse the ink in via hole well.If extending developing time, although the ink in via hole can be rinsed
Totally, but easily cause welding resistance overlay area be connected with no-coverage solder mask side etching quantity increase（Develop excessive）, lead
Cause welding resistance bridge come off, be surface-treated after pad（PAD）The problems such as side welding resistance falls oil, influences PCB performance.
The content of the invention
In view of the foregoing, it is necessary to the method that a kind of manufacture PCB of the anti-welding plug-hole of improvement PCB via holes is provided.
The invention provides a kind of method for manufacturing printed substrate, comprise the following steps：
(a) carries out silk-screen printing to printed substrate；
(b) printed substrate described in preliminary dryings；
(c) printed substrate and the first film aligning are exposed by；
(d) rinses the printed substrate with developer solution and developed；
(e) by the printed substrate and the second film aligning, it is exposed；And
(f) rinses the printed substrate with the developer solution again and developed；
Wherein, via hole is provided with the printed substrate, the printed substrate includes welding resistance no-coverage and welding resistance
The half tone of no catch point is used in overlay area, the step (a), first film has corresponding described for blocking
The catch point of welding resistance no-coverage.
Further, the welding resistance no-coverage of via hole, second film are contained corresponding to the printed substrate
With corresponding catch point.
Further, the welding resistance no-coverage of via hole is not contained corresponding to the printed substrate, described second is luxuriant and rich with fragrance
Woods does not have corresponding catch point.
Further, corresponding to the catch point of the same via hole of the printed substrate, the catch point of second film compares institute
The corresponding catch point for stating first film is unilateral small 25.4-50.8 microns.
Further, the small size of the via hole corresponding to the printed wire board finished product back aperture below 0.6 millimeter
Catch point, the small size catch point of second film is more unilateral than the corresponding small size catch point of first film small 25.4 microns.
Further, the large scale that 0.6 millimeter of via hole is more than corresponding to the printed wire board finished product back aperture is kept off
Point, the large scale catch point of second film is more unilateral than the corresponding large scale catch point of first film small 50.8 microns.
Further, the aperture of the via hole of the catch point of second film printed substrate more corresponding than its is unilateral
More than or equal to 25.4 microns.
Further, in the step (e), complete after contraposition, the aperture of each via hole of the printed substrate
Covered completely by the catch point of second film, and the printed substrate the welding resistance area of coverage not by the gear of second film
Point is covered.
Further, in the step (e), exposure energy is between 500-800 millijoules.
Further, the developing time of the step (f) is between 90-120 seconds.
Compare prior art, exposed and developed to effectively improve PCB via holes anti-welding stifled by aligning twice by the present invention
The problem of hole.After the welding resistance of prior art aligns exposed and developed step, then once align it is exposed and developed, both
It can ensure that welding resistance side etching quantity is unaffected, the solder mask that residual in via hole can be effectively cleaned again avoids via hole ink from blocking up
Hole.
Brief description of the drawings
Fig. 1 shows the flow chart of an embodiment of method provided by the present invention.
Fig. 2 schematically shows the finished product PCB obtained by manufacture in one embodiment of the invention.
Fig. 3 schematically shows first film used in the PCB prepared shown in Fig. 2.
Fig. 4 schematically shows second film used in the PCB prepared shown in Fig. 2.
Embodiment
Fig. 1 shows an embodiment of manufacture PCB provided by the present invention method, mainly includes the following steps that：
S110, pre-treatment；
S120, silk-screen solder mask；
S130, preliminary drying；
S140, is exposed using the first film aligning；
S150, development；
S160, is exposed using the second film aligning；
S170, redevelopment；
S180, solidify afterwards.
In step S110, pre-treatment is carried out to PCB, plate face oxide, oil stain and impurity is such as removed, increases the coarse of plate face
Degree is to strengthen the adhesive force of solder mask and plate face.
In step S120, the silk-screen solder mask on PCB.Specifically, in the present embodiment, the side printed using white twine
Formula prints solder mask, and especially, the white net used is the half tone without catch point.
In step S130, the PCB for being printed with solder mask is subjected to prebake conditions, the solvent content in solder mask is waved
Hair, so that a certain degree of hardening occurs for ink.
In step S140, PCB and the first film aligning are exposed.It will be appreciated by those skilled in the art that, first
There are multiple lightproof areas on the film, PCB welding resistance no-coverage is corresponded to after contraposition.Fig. 2 schematically shows this
Invent in an embodiment and be provided with via hole 33 on the finished product PCB 30 obtained by manufacture, the PCB 30.For ease of illustrating the present invention's
Spirit, can be welding resistance no-coverage 35 and welding resistance overlay area 37 by 30 points of PCB.In welding resistance no-coverage 35, including
The welding resistance no-coverage 310 of via hole and the welding resistance no-coverage 330 containing via hole are not contained.Fig. 3 schematically shows
First film 50 used in PCB shown in Fig. 2 is gone out to prepare.There are multiple lightproof areas on first film 50, that is, hinder
Weldering windowing catch point.After first film 50 is aligned with the PCB 30 in processing, each lightproof area of first film 50 can be right
PCB 30 each welding resistance no-coverage 35 that should be shown in ground Occlusion Map 2.As shown in Figures 2 and 3, the first kind of first film
Catch point 510 corresponds to the welding resistance no-coverage 310 for not containing via hole, and the Equations of The Second Kind catch point 530 of first film, which corresponds to, to be contained
There are the welding resistance no-coverage 330 and via hole 33 of via hole.Therefore, by first film 50 and corresponding PCB workpieces pair
It is exposed behind position, due to being blocked by catch point photocuring reaction does not occur for the solder mask of welding resistance no-coverage 35 substantially,
And by illumination photocuring reaction is occurred for the solder mask of welding resistance overlay area 37.
Developed in step S150, the PCB rinsed with developer solution after exposure.Developer solution can be using concentration in 0.8%-
The weakly alkaline solutions such as sodium carbonate or potassium carbonate between 1.2%.The ink that photocuring reaction does not occur can be molten except simultaneously with developed liquid
Wash off, and there occurs the ink of photocuring reaction can not be dissolved in developer solution to be retained on PCB.In other words, step is passed through
Rapid S140 and S150 contraposition is exposed and developed, can be by the pattern transfer on first film to PCB, and being formed has identical figure
The solder mask of shape.
In step S160, the PCB and the second film aligning of gained in step S150 are exposed.Second film with
First film employed in step S140 is in lightproof area（Catch point）Design on there may be difference, will carry out below
It is described in detail.
In step S170, developed with the PCB obtained by developer solution rinsing step S160, will not occur photocuring reaction
Solder mask is washed with developer solution.
In step S180, by the solder mask baking-curing on the PCB obtained by step S170.
Manufacture PCB provided by the present invention method can be reached similar to use by using step S160 and S170
Catch point net carries out the effect of silk-screen solder mask, it is to avoid the solder mask solidification for flowing into via hole blocks via hole.Below will knot
Fig. 2, Fig. 3 and Fig. 4 is closed the preferred embodiment of second film in this method is described in detail.
Fig. 3 schematically shows first film 50 used in the PCB prepared shown in Fig. 2, including two kinds of
Catch point.Wherein, the first kind catch point 510 of first film is non-corresponding to the welding resistance that via hole is not contained in the PCB 30 shown in Fig. 2
Overlay area 310, the Equations of The Second Kind catch point 530 of first film is non-corresponding to the welding resistance containing via hole in the PCB 30 shown in Fig. 2
Overlay area 330.
Fig. 4 schematically shows second film 70 used in the PCB prepared shown in Fig. 2.With first shown in Fig. 3
The film 50 is compared, and second film 70 only remains Equations of The Second Kind catch point, and the Equations of The Second Kind catch point 730 of second film corresponds to Fig. 2 institutes
Welding resistance no-coverage 330 containing via hole in the PCB 30 shown.In other words, to eliminate those on second film 70 right
The first kind catch point of the welding resistance no-coverage 310 of via hole should not be contained in PCB 30.When second film 70 is pointed to PCB
When 30, PCB 30 each via hole 33 is completely covered by the Equations of The Second Kind catch point 730 of second film, and the second of second film
Class catch point 730 will not block PCB 30 welding resistance overlay area 37.
Based on the above-mentioned design method to second film, in step S160, the welding resistance covering in the PCB 30 shown in Fig. 2
Region 37 is exposed with not containing the welding resistance no-coverage 310 of via hole.Wherein, welding resistance overlay area 37 is in step S140
The solder mask for occurring photocuring can be photosensitive again, makes the sufficient photocuring of solder mask positioned at the welding resistance overlay area 37.
And in step S160, the welding resistance no-coverage 330 containing via hole of the PCB 30 shown in Fig. 2 is by the second of second film
Class catch point 730 is blocked, substantially not photosensitive, it is to avoid the resistance for being cleaned not in step S150 removing is remained in via hole 33
Photoresponse occurs for solder paste ink.Further, the exposure energy being exposed in this step S160 is in 500-1000 millijoules
（mJ）Between.For example, when the exposure machine using 80 kW, the time for exposure is about 15-35 seconds.It will be appreciated by those skilled in the art that
, if exposure energy is too low, the photocuring degree for being likely to result in welding resistance overlay area 37 is not enough, in the secondary of step S170
Welding resistance overlay area 37 is likely to result in during development and the solder mask side etching quantity of the joining place of welding resistance no-coverage 35 increases, influence
Finished product PCB performance；If exposure energy is too high, exposure efficiency can be influenceed again.
Next, in step S170 developing process, for PCB 30 welding resistance overlay area 37, due to being printed in this
The solder mask in region is by sufficient photocuring, and developer will not further corrode the edge of solder mask, so as to avoid welding resistance
The solder mask side etching quantity increase of overlay area 37 and the joining place of welding resistance no-coverage 35 causes welding resistance bridge to come off, be surface-treated after
Pad（PAD）The generation for the problems such as side welding resistance falls oil.And for the PCB 30 welding resistance no-coverage 330 containing via hole,
If still remaining the solder mask for being cleaned removing not in step S150 in via hole 33, it can be shown in step S170
Shadow agent is cleaned again, so as to sufficiently remove the residual ink in via hole 33, realizes the purpose for avoiding plug-hole.It is preferred that step
Rapid S170 developing time is between 90-120 seconds.It will be appreciated by those skilled in the art that, the developing time can be according to reality
The degree of residual ink is adjusted in via hole 33 in the production process of border., can be with proper extension if residual ink is more
Developing time.
Further, when designing second film, the size of the Equations of The Second Kind catch point 730 of second film can be with first phenanthrene
The size of the Equations of The Second Kind catch point 530 of woods is slightly different.It is preferred that the Equations of The Second Kind catch point 730 of second film is than corresponding finished product
The aperture of via hole 33 unilateral big 2 mil and 2 more than mil on PCB 30, and the Equations of The Second Kind catch point 730 of second film compares phase
The unilateral small 1-2 mil of Equations of The Second Kind catch point 530 for first film answered（1mil is approximately equal to 25.4 microns, the catch point ratio of second film
The catch point of corresponding first film is unilateral small about 25.4-50.8 microns）.It should be understood that when catch point is circle, second film
Catch point of each position of the catch point on its circumference than corresponding first film closer to center of circle 1-2 mil, in other words
Diameter small 2-4 mil of the diameter of the catch point of second film than the catch point of corresponding first film.Similar, when catch point is four sides
During shape, each position of the catch point of second film on their outer circumference than corresponding first film catch point closer in quadrangle
Side 1-2 mil.It should be understood that if the catch point of second film 70 is oversized, after step S160 completes contraposition, catch point will
The edge of welding resistance overlay area 37 is blocked, this can make the edge blocked by catch point can not be further photo-curing, be likely to result in
After step S170 developments, the edge lateral erosion quantitative change that this part is blocked is big, causes so-called " development is excessive ".If second is luxuriant and rich with fragrance
The catch point of woods 70 is undersized, for the less via hole in aperture, is influenceed by resist thickness, vacuumizes second film after contraposition
It can not be in close contact with PCB, catch point at the aperture of small-bore via hole with that can produce gap, ink sense when causing to expose in hole
Photocuring, can not clean when step S170 develops and remove, it is impossible to avoid plug-hole.
Further, can be according to the aperture difference of via hole 33 on finished product PCB 30 to gear when designing second film
The size of point carries out differentiation design.For example, the via hole 33 that aperture on finished product PCB 30 is more than 0.6 millimeter is defined as into aperture
Larger via hole, schematically, reference can be made to the via hole 33a in Fig. 2；Correspondingly, aperture on finished product PCB 30 is not more than
0.6 millimeter of via hole 33 is defined as the less via hole in aperture, schematically, reference can be made to the via hole 33b in Fig. 2.Correspondence
It is used for the catch point 530a for blocking via hole 33a accordingly in having on the via hole 33a that aperture is larger, first film 50, the
There is the corresponding catch point 730a for being used to block via hole 33a, catch point 730a to be opened a window than catch point 530a unilateral on two films 70
Small 2 mil, about 50.8 microns.Have corresponding to the less via hole 33b in aperture, on first film 50 corresponding for blocking this
There is the corresponding catch point 730b for being used to block via hole 33b, catch point on via hole 33b catch point 530b, second film 70
730b is than unilateral small 1 mil of catch point 530b windowings, about 25.4 microns.
It should be pointed out that the specific implementation method in presently disclosed each step, such as production equipment, production work
Tool and manufacturing parameter etc., such as nothing are clearly limited, or phase identical with the prior art that this area those skilled in the art are understood
Seemingly, no longer go to live in the household of one's in-laws on getting married and chat herein.The above via hole, refers to the conducting that another top layer is extended to from a PCB top layer
Hole.
Compared with prior art, the present invention, will be possible in PCB via hole by develop twice (step S150 and S170)
The solder mask of residual is cleaned up, it is to avoid the influence of welding resistance plug-hole make obtained by finished product PCB performance, while by using the
Two film alignings expose, and welding resistance overlay area have been carried out photo-curing twice, improve the resistance for being printed on welding resistance overlay area
The curing degree of solder paste ink, so as to eliminate second development step to a certain extent to welding resistance overlay area and non-coverage area
Domain is connected the lateral erosion of solder mask.The present invention effectively improves asking for PCB ink plug-holes on the basis of the white twine print of welding resistance
Topic, maintains the efficiency of welding resistance silk-screen and the PCB of manufacture performance.
Above-described embodiment is preferably embodiment, but embodiments of the present invention are not by above-described embodiment of the invention
Limitation, embodiment of above is only for explaining claims.Right protection scope of the present invention is not limited to specification.Appoint
What those familiar with the art is in the technical scope of present disclosure, the change or replacement that can be readily occurred in,
It is included within protection scope of the present invention.
Claims (10)
1. a kind of method for manufacturing printed substrate, comprises the following steps：(a) carries out silk-screen printing to printed substrate；(b).
Printed substrate described in preliminary drying；(c) printed substrate and the first film aligning are exposed by；(d) is rushed with developer solution
The printed substrate is washed to be developed；(e) by the printed substrate and the second film aligning, it is exposed；And
(f) rinses the printed substrate with developer solution again and developed；Wherein, via hole is provided with the printed substrate,
The printed substrate includes using no catch point in welding resistance no-coverage and welding resistance overlay area, the step (a)
Half tone, first film has the corresponding catch point for being used to block the welding resistance no-coverage.
2. the method as described in claim 1, it is characterised in that the welding resistance for containing via hole corresponding to the printed substrate is non-
Overlay area, second film has corresponding catch point.
3. method as claimed in claim 2, it is characterised in that the welding resistance of via hole is not contained corresponding to the printed substrate
No-coverage, second film does not have corresponding catch point.
4. method as claimed in claim 3, it is characterised in that corresponding to the catch point of the same via hole of the printed substrate,
The catch point of second film is more unilateral than the corresponding catch point of first film small 25.4-50.8 microns.
5. method as claimed in claim 3, it is characterised in that corresponding to the printed wire board finished product back aperture in 0.6 milli
The small size catch point of via hole below rice, corresponding small size of the small size catch point than first film of second film
Catch point is unilateral small 25.4 microns.
6. method as claimed in claim 3, it is characterised in that be more than 0.6 corresponding to the printed wire board finished product back aperture
The large scale catch point of the via hole of millimeter, the large scale catch point of second film is kept off than the corresponding large scale of first film
Point is unilateral small 50.8 microns.
7. method as claimed in claim 2, it is characterised in that catch point track more corresponding than its of second film
The via hole of road plate is unilateral to be more than or equal to 25.4 microns.
8. the method as described in claim 1, it is characterised in that in the step (e), is completed after contraposition, the track
The aperture of each via hole of road plate is covered completely by the catch point of second film, and the welding resistance covering of the printed substrate
Area is not covered by the catch point of second film.
9. the method as described in claim 1, it is characterised in that in the step (e), exposure energy is at 500-800 MJs
Between ear.
10. the method as described in claim 1, it is characterised in that the developing time of the step (f) is between 90-120 seconds.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710594161.1A CN107148159A (en) | 2017-07-20 | 2017-07-20 | The method for manufacturing printed substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710594161.1A CN107148159A (en) | 2017-07-20 | 2017-07-20 | The method for manufacturing printed substrate |
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| Publication Number | Publication Date |
|---|---|
| CN107148159A true CN107148159A (en) | 2017-09-08 |
Family
ID=59776606
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| CN201710594161.1A Pending CN107148159A (en) | 2017-07-20 | 2017-07-20 | The method for manufacturing printed substrate |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107995794A (en) * | 2017-11-09 | 2018-05-04 | 建业科技电子（惠州）有限公司 | One kind solves welding resistance blind hole and hides oily exposure film production method |
| CN108834330A (en) * | 2018-06-29 | 2018-11-16 | 惠州市金百泽电路科技有限公司 | A kind of processing method of PCB " D " font abnormal shape pad |
| CN109041443A (en) * | 2018-09-05 | 2018-12-18 | 清远市富盈电子有限公司 | A kind of pcb board prevents solder mask from entering the method in hole |
| CN109275278A (en) * | 2018-11-14 | 2019-01-25 | 大连崇达电路有限公司 | A kind of welding resistance process improving welding resistance ghost |
| CN109287076A (en) * | 2018-11-14 | 2019-01-29 | 大连崇达电路有限公司 | The method of the single side opening bleed of aperture 0.8mm or more is prevented in welding resistance technique |
| CN110475435A (en) * | 2019-08-14 | 2019-11-19 | 江西景旺精密电路有限公司 | A kind of method of anti-welding small-bore production through-hole |
| CN110856361A (en) * | 2019-11-18 | 2020-02-28 | 高德（江苏）电子科技有限公司 | Improvement method applied to solder mask ink inlet holes of PCB plug-in board holes |
| CN113365436A (en) * | 2021-06-16 | 2021-09-07 | 珠海中京电子电路有限公司 | Production method for solving solder resist ink inlet hole |
| CN114375106A (en) * | 2021-12-23 | 2022-04-19 | 深圳中富电路股份有限公司 | Method for improving hole plugging of PCB solder-resisting conducting hole |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107995794A (en) * | 2017-11-09 | 2018-05-04 | 建业科技电子（惠州）有限公司 | One kind solves welding resistance blind hole and hides oily exposure film production method |
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| CN110856361A (en) * | 2019-11-18 | 2020-02-28 | 高德（江苏）电子科技有限公司 | Improvement method applied to solder mask ink inlet holes of PCB plug-in board holes |
| CN113365436A (en) * | 2021-06-16 | 2021-09-07 | 珠海中京电子电路有限公司 | Production method for solving solder resist ink inlet hole |
| CN114375106A (en) * | 2021-12-23 | 2022-04-19 | 深圳中富电路股份有限公司 | Method for improving hole plugging of PCB solder-resisting conducting hole |
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