CN107145299B - Multi-channel wide band signal high speed acquisition and repeater system based on JESD204B agreements - Google Patents
Multi-channel wide band signal high speed acquisition and repeater system based on JESD204B agreements Download PDFInfo
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- CN107145299B CN107145299B CN201710307478.2A CN201710307478A CN107145299B CN 107145299 B CN107145299 B CN 107145299B CN 201710307478 A CN201710307478 A CN 201710307478A CN 107145299 B CN107145299 B CN 107145299B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/05—Digital input using the sampling of an analogue quantity at regular intervals of time, input from a/d converter or output to d/a converter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0024—Peripheral component interconnect [PCI]
Abstract
The invention belongs to data collecting fields, propose a kind of multi-channel wide band signal high speed acquisition and repeater system based on JESD204B agreements, including analog signal conditioner module, high-speed ADC array, high-speed data acquisition control module, multichannel cache controller, cache module, SFP interface modules, PCIe endpoint 1590 interface module, high-speed data acquisition control module includes JESD204B receiving modules, collecting flowchart management module and transmission control module, transmission control module respectively with JESD204B receiving modules, collecting flowchart management module is connected with multichannel cache controller；JESD204B receiving modules are connect by high-speed transceiver with high-speed ADC array module, collecting flowchart management module is connect by SPI interface with high-speed ADC array module, and transmission control module is connect with communication test set by SFP interface modules and realizes that bus is connect with embedded computer by PCIe interface module.The present invention realizes high speed acquisition and the forwarding of data, can be widely applied to radar, navigation, the communications field.
Description
Technical field
The present invention relates to the acquisition of the data in the fields such as radar, navigation, communication and repeater systems, and in particular to one kind is based on
The multi-channel wide band signal high speed acquisition and repeater system of JESD204B agreements.
Background technology
In order to closely follow international latest development dynamic, develop the related high-grade, precision and advanced science and technology such as efficient fast information data chain,
It studies novel different Communications Protocol Specification and applies most important in actual product.International mainstream trend shows that modularization is set
Meter and Open architecture.Wherein, the development of advanced radar equipment embodies the standard modular and integration of equipments of anti-missile system；
It builds high-performance novel communication base station and promotes information flow, meet people's lives production requirement, service defence equipment construction.
The country has been achieved for very big progress and development in high speed information transmission field at present.Data-link formed with
During realization, High speed data acquisition has irreplaceable supporting role.Currently, not with acquisition transmission speed
There is problems of Signal Integrity in the multi-channel high-speed collecting device based on concurrent technique and occupies resource mistake in disconnected upgrading
More disadvantages.In order to solve problems, international JESDC associations propose JESD204 standards, it is intended that adapt to data converter with
Very high speediness transmission between logical device, and it is also seldom to the development and application of JESD204 standards in currently available technology, without energy
The system for enough realizing the acquisition and forwarding of high-speed wideband signal, cannot fully meet the actual demand of high speed transmission of signals.
Invention content
The present invention overcomes the shortcomings of the prior art, technical problem to be solved to be：One kind is provided to be based on
The multi-channel wide band signal high speed acquisition and repeater system of JESD204B agreements realize high-speed transfer and the forwarding of sampled data,
It provides safeguard to obtain gathered data in real time for computer and carry out data analysis, data branch is provided for equipment performance test
It holds.
In order to solve the above-mentioned technical problem, the technical solution adopted by the present invention is：It is a kind of based on the more of JESD204B agreements
Channel wideband high-speed signal acquisition and repeater system, including analog signal conditioner module, high-speed ADC array module, high-speed data
Acquisition control module, multichannel cache controller, cache module, SFP interface modules, PCIe endpoint 1590 interface module, the high speed
Data acquisition and control module includes JESD204B receiving modules, collecting flowchart management module and transmission control module；The transmission
Control module is connect with the JESD204B receiving modules, collecting flowchart management module and multichannel cache controller respectively, institute
Multichannel cache controller is stated to connect with cache module；The JESD204B receiving modules include multiple high-speed transceivers, are led to
It crosses high-speed transceiver to connect with high-speed ADC array module, the collecting flowchart management module includes SPI interface module, passes through SPI
Interface module is connect with the high-speed ADC array module, the transmission control module also by the SFP interface modules with communicate
Test equipment connects, and the transmission control module also realizes that bus is connect by PCIe endpoint 1590 interface module with host computer；It is described
Transmission control module is used to receive the control stream signal of host computer transmission, and is converted by the collecting flowchart management module
ADC control stream signals give high-speed ADC array module, the transmission control module to be additionally operable to through the JESD204B receiving modules
Data are received from the high-speed ADC array module, and pass through multichannel cache controller storage to the cache module；
The control signal that the multichannel cache controller is used to be sent according to transmission control module realizes the different cachings for flowing to data
Management；The transmission control module is additionally operable to respectively send the data in cache module by the PCIe endpoint 1590 interface module
It is sent to communication test set to host computer and by the SFP interface modules.
The high-speed data acquisition control module, SFP interface modules, PCIe endpoint 1590 interface module are integrated in fpga chip
In.
The JESD204B receiving modules further include multiple monitoring decoding modules, link monitoring module, error handling module
With Clock management module, the multiple high-speed transceiver from high-speed ADC array module for receiving data, the multiple monitoring
Each in decoding module is connect with one of in the multiple high-speed transceiver respectively, link monitoring module with it is described
Multiple monitoring decoding module connections, error handling module are connect with link monitoring module, and the monitoring decoding module is used for right
The JESD204B data that the gigabit high-speed transceiver GTX answered is received carry out comma detection and character decoding, the link monitoring
The operation of counting and monitoring high-speed transceiver feedback of the module for monitoring the control character occurred in respective links in real time differs
Marking signal, the error handling module is caused to be used to, when mistake occurs for link, judge whether link needs to re-establish, and
Give up the data received at this time.
The cache module is the SDRAM chips based on DDR3 interfaces, and the multichannel cache controller caches for SDRAM
Controller；The multichannel cache controller passes through the MIG IP kernels realization built in fpga chip, the multichannel buffer control
Device includes that MIG IP modules, write process module, reading scheduler module, command process module, an input interface and two outputs connect
Mouthful, for being directly controlled to SDRAM chips, the write process module and reading scheduler module lead to the MIG IP modules respectively
It crosses input interface and output interface to communicate with the user interface of MIG IP, is respectively utilized to complete the write-in and reading of data, it is described
Command process module is distributed for receiving and decoding top level control signal, realization sampled data to the selection in two different paths,
Read-write operation is returned simultaneously completes signal.
The SFP interface modules include the combination of four-way high-speed transceiver, link initialization unit, flow control unit,
Status control unit receives data unwrapper unit, transmission data packaged unit and fifo module, the PCIe endpoint 1590 interface module
Including 8 channel high-speed transceiver combinations, PCIe stones, PIO modules and dma module, the PIO modules are for realizing fpga chip
Control signal stream between host computer exchanges, and the dma module is for realizing sampled data to the high speed between host computer
It uploads.
A kind of the multi-channel wide band signal high speed acquisition and repeater system based on JESD204B agreements, data are adopted
Collection includes the following steps with forwarding：
（1）JESD204B receiving modules first determine whether link is correctly established, after link is completely established, the acquisition
Workflow management module acquires array to high-speed ADC by SPI interface and sends ADC control stream signals, and high-speed ADC acquisition array starts
Gathered data, and it is output to JESD204B receiving modules after converting data to JESD204B data formats；
（2）JESD204B receiving modules receive data by high-speed transceiver and are sent into cache module caching；
（3）Transmission control module initiates DMA request by PCIe endpoint 1590 interface module to host computer, and passes through PCIe endpoint 1590
Interface module is converted to the data in cache module after PCIe format through 8 channel link high-speed uploadings to host computer；
（4）Transmission control module sends out the handshake with communication test set by Aurora agreements, and is connect by SFP
After mouth mold block is encoded the data in cache module by the coding mode of 8B/10B, uploaded to by 4 channel links logical
Believe test equipment.
The host computer is embedded computer, and the communication test set is Mass Data Storage Facility or large capacity
Data Analysis Services equipment.
The present invention has the advantages that compared with prior art：The present invention is based on the multi-channel wides of JESD204B agreements
Band signal high speed acquisition and repeater system include the PCIe interface of the high speed x8 links communicated with embedded computer, transmission
Rate completes PIO up to 40GT/s（Programmable input and output）And DMA（Direct memory read-write）Two distinct types of TLP
（Transfer layer packet）Packing, unpacking and control, wherein realized using PIO patterns and controlled between board and PC
The high-speed uploading PC of sampled data is realized in the exchange of signal stream using DMA mode, ensures that PC host computers can real-time analytical sampling
Data；Further include the SFP interfaces of the x4 links communicated with other communication test sets, using the coding mode of 8B/10B, transmission
Rate can reach 25GT/s, meet the data transmission index of high speed acquisition system；And including simulation input bandwidth 800Mhz,
The JESD204B interfaces of 14 sampling rate for each channel 2GMSPS, conversion accuracy high-speed AD arrays, and be provided with inside FPGA
Multichannel cache controller based on DDR3 communication protocols, can control external SDRAM storage chips realize data flow multithread to
Distribution and caching, moreover, being provided with collecting flowchart based on SPI specifications in high-speed data acquisition control module manages mould
Block is realized and is accurately controlled to ADC array modules.
Description of the drawings
Fig. 1 be the embodiment of the present invention propose a kind of multi-channel wide band signal high speed acquisition based on JESD204B agreements with
The structural schematic diagram of repeater system；
Fig. 2 is the schematic diagram of high speed data acquisition and control module of the embodiment of the present invention；
Fig. 3 is the schematic diagram of multichannel cache controller control cache module in the embodiment of the present invention；
Fig. 4 is PCIe endpoint 1590 module principle figure in the embodiment of the present invention；
Fig. 5 is SFP interface modules schematic diagram in the embodiment of the present invention.
Specific implementation mode
It in order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below will be in the embodiment of the present invention
Technical solution be clearly and completely described, it is clear that described embodiment be the present invention a part of the embodiment, without
It is whole embodiment；Based on the embodiments of the present invention, those of ordinary skill in the art are not before making creative work
The every other embodiment obtained is put, shall fall within the protection scope of the present invention.
As shown in Figure 1, it is high to propose a kind of multi-channel wide band signal based on JESD204B agreements for the embodiment of the present invention
Speed acquisition and repeater system, including it is analog signal conditioner module, high-speed ADC array module, high-speed data acquisition control module, more
Channel cache controller（Multi Port Memroy Controler, MPMC）, cache module, SFP interface modules, the ends PCIe
Point interface module, the high-speed data acquisition control module include JESD204B receiving modules, collecting flowchart management module and biography
Defeated control module, the transmission control module respectively with the JESD204B receiving modules, collecting flowchart management module and Duo Tong
Road cache controller connection, the multichannel cache controller are connect with cache module；The JESD204B receiving modules include
Multiple high-speed transceivers are connect by high-speed transceiver with high-speed ADC array module, and the collecting flowchart management module passes through
SPI interface is connect with the high-speed ADC array module, the transmission control module also by the SFP interface modules with communicate
Test equipment connects, and the transmission control module also realizes that bus connects by PCIe endpoint 1590 interface module and embedded computer
It connects；Wherein, the transmission control module is used to receive the control stream signal of embedded computer transmission, and is flowed by the acquisition
Thread management module converter is that ADC control stream signals give high-speed ADC array module, the transmission control module to be additionally operable to by described
JESD204B receiving modules receive data from the high-speed ADC array module, and are deposited by the multichannel cache controller
Store up the cache module；The control signal that the multichannel cache controller is used to be sent according to transmission control module is realized
Difference flows to the cache management of data, i.e., flows to data by different（SFP interface modules and PCIe endpoint 1590 interface module）Delay respectively
It is stored to the buffer unit；The transmission control module is additionally operable to the data in cache module respectively by the PCIe endpoint 1590
Interface module is sent to embedded computer and is sent to communication test set by the SFP interface modules.
Wherein, as shown in Figure 1, the high-speed data acquisition control module, SFP interface modules, PCIe endpoint 1590 interface module
It is integrated in fpga chip.
As shown in Fig. 2, for the principle schematic of high-speed data acquisition control module, wherein JESD204B receiving module packets
Include multiple gigabit high-speed transceiver GTX, multiple monitoring decoding modules, link monitoring module, error handling module and clock pipe
Module is managed, excessively a high-speed transceiver from high-speed ADC array module for receiving data, the multiple monitoring decoding module
In each connect respectively with one of in the multiple high-speed transceiver, link monitoring module and multiple monitorings decoding mould
Block connects, error handling moduleWithLink monitoring module connects, and the monitoring decoding module is used for corresponding gigabit high speed
The JESD204B data that transceiver GTX is received carry out comma detection and character decoding, and the link monitoring module for supervising in real time
The inconsistent marking signal of operation of the counting and monitoring high-speed transceiver feedback of the control character occurred in respective links is surveyed, it is described
Error handling module is used to, when mistake occurs for link, judge whether link needs to re-establish, and give up and receive at this time
Data.After the JESD204B interface modules receive data progress 64bit data conversions, after the transmission control module,
By in multichannel cache controller control storage to cache module.Wherein, collecting flowchart management module includes SPI interface mould
Block and collecting flowchart state machine, the control stream signal that collecting flowchart machine is used to be transmitted according to transmission control module generate idle shape
State information, initialization information or normal acquisition information simultaneously transmit the ADC array modules.Before acquisition starts, collecting flowchart shape
State machine controls ADC completion link initializations by SYNC signal and the operating mode of ADC is become test pattern；It is normal when starting
When sampling, collecting flowchart state machine sends formal sampling information, and the operating mode of ADC restores normal.
As shown in figure 3, the cache module can be the SDRAM chips based on DDR3 interfaces, the multichannel caching control
Device processed can be SDRAM cache controllers, and the storage space of SDRAM chips can be 2GB or bigger；The multichannel caching
Controller realizes that the multichannel cache controller includes MIG IP modules, writes by the MIG IP kernels built in fpga chip
Journey module, reading scheduler module, command process module, an input interface and two output interfaces, the MIG IP modules are used for
DDR3SDRAM chips are directly controlled, the write process module and reading scheduler module pass through input interface and output respectively
Interface is communicated with the user interface of MIG IP, is respectively utilized to complete the write-in and reading of data；The command process module is used for
It is received by input interface and decodes top level control signal, realized the data stream management strategy of this system " one into have more ", complete
Sampled data flows to two different paths（SFP interface modules and PCIe endpoint 1590 interface module）Selection distribution, while returning to reading
Write operation status signal.Therefore the present invention in multichannel cache controller may be implemented to data flow multithread to it is real-time caching and
Control, system of the invention control multi-disc ADC implementation process management functions, the conversion master of system acquisition state by fpga logic
The variation of chip acquisition state is realized in the switching that rely on ADC working conditions by changing the register inside ADC；Work as acquisition
It is formal start after, the whereabouts problem of sampled data stream is controlled by multichannel cache controller according to actual needs, one is by
FPGA sends out DMA request to PC, then by realizing high-speed communication based on PCIe buses and PC；Another kind be by FPGA send out with
The handshake of other equipment carries out high-speed communication using four-way SFP interfaces and other equipment, realizes data forwarding；No matter
What the flow direction of sampled data is, the specific transmission rate in conjunction with involved high-speed interface is required for delay Large Volume Data
It deposits, the rate difference for compensating distinct interface.
As shown in figure 4, the PCIe endpoint 1590 interface module is hard including 8 channel gigabit high-speed transceiver GTX combinations, PCIe
Core, control module, PIO modules and dma module, the PIO modules by by x8 links realize fpga chip with it is embedded based on
The exchange of control signal stream between calculation machine, the dma module are used to realize sampled data to embedding assembly by x8 links
High-speed uploading between machine.The physics in PCIe link is completed by PCIe stones in application gigabit high-speed transceiver and FPGA
Layer and link layer, devise the two kinds of transport layer structures of PIO and DMA, complete decoding and the coding of different types of TLP,
Realize data, command communication between PC and collection plate.
As shown in figure 5, the SFP interface modules include four-way gigabit high-speed transceiver GTX combinations, link initialization
Unit, status control unit, receives data unwrapper unit, transmission data packaged unit and fifo module, base at flow control unit
It is used to communicate the sampled data in memory module with other by x4 links in the four-way SFP interface modules of Aurora agreements
Test equipment high speed exchanges.Aurora agreements are the lightweight protocols of increasing income by matching the exploitation of company of Sentos, are had convenient for exploitation, dimension
Protect the advantages that simple；Communication test set application HSSI High-Speed Serial Interface communicates, wherein the SFP optic modules based on Aurora agreements
The high speed interconnection being widely used between general purpose test equipment.
Wherein, a kind of multi-channel wide band signal high speed acquisition and repeater system based on JESD204B agreements of the invention,
Its workflow includes the following steps：
（1）JESD204B receiving modules first determine whether link is correctly established, after link is completely established, the acquisition
Workflow management module acquires array to high-speed ADC by SPI interface and sends ADC control stream signals, and high-speed ADC acquisition array starts
Gathered data, and it is output to JESD204B receiving modules after converting data to JESD204B data formats；
（2）JESD204B receiving modules receive data by high-speed transceiver and are sent by multichannel cache controller slow
Storing module caches；
（3）Transmission control module initiates DMA request by PCIe interface to embedded computer, and is connect by PCIe endpoint 1590
Data in cache module are converted to and upload to embedded computer by x8 speed links after PCIe format by mouth mold block；
（4）Transmission control module sends out the handshake with communication test set by Aurora agreements, and is connect by SFP
After mouth mold block is encoded the data in cache module by the coding mode of 8B/10B, communication is uploaded to by x4 links and is surveyed
Try equipment.
When sampled data is uploaded to host computer, i.e., after embedded computer, these data can be by Digital Signal Processing software
Analysis, and then obtain being sampled the static parameter and dynamic parameter of radiofrequency signal, it is adopted to reach test ADC performances or analysis
The function of sample signal characteristic；It, can be by four-way SFP communication interfaces by sampled data if necessary to forwarding these data in real time
It is distinguished according to acquisition channel, is transferred to the communication test set of rear end, i.e. Mass Data Storage Facility or Large Volume Data point
Analyse processing equipment.
Finally it should be noted that：The above embodiments are only used to illustrate the technical solution of the present invention., rather than its limitations；To the greatest extent
Present invention has been described in detail with reference to the aforementioned embodiments for pipe, it will be understood by those of ordinary skill in the art that：Its according to
So can with technical scheme described in the above embodiments is modified, either to which part or all technical features into
Row equivalent replacement；And these modifications or replacements, various embodiments of the present invention technology that it does not separate the essence of the corresponding technical solution
The range of scheme.
Claims (7)
1. a kind of multi-channel wide band signal high speed acquisition and repeater system based on JESD204B agreements, which is characterized in that including
Analog signal conditioner module, high-speed ADC array module, high-speed data acquisition control module, multichannel cache controller, caching mould
Block, SFP interface modules, PCIe endpoint 1590 interface module, the high-speed data acquisition control module include JESD204B receiving modules,
Collecting flowchart management module and transmission control module；
The transmission control module caches with the JESD204B receiving modules, collecting flowchart management module and multichannel control respectively
Device connection processed, the multichannel cache controller are connect with cache module；The JESD204B receiving modules include multiple high speeds
Transceiver is connect by high-speed transceiver with high-speed ADC array module, and the collecting flowchart management module includes SPI interface
Module is connect by SPI interface module with the high-speed ADC array module, and the transmission control module also passes through the SFP
Interface module is connect with communication test set, and the transmission control module is also realized by PCIe endpoint 1590 interface module and host computer
Bus connects；
The transmission control module is used to receive the control stream signal of host computer transmission, and passes through the collecting flowchart management module
Being converted into ADC control stream signals to high-speed ADC array module, the transmission control module to be additionally operable to connect by the JESD204B
It receives module and receives data from the high-speed ADC array module, and delayed to described by multichannel cache controller storage
Storing module；The control signal that the multichannel cache controller is used to be sent according to transmission control module, realization is different to flow to number
According to cache management；The transmission control module is additionally operable to the data in cache module respectively by the PCIe endpoint 1590 interface
Module is sent to host computer and is sent to communication test set by the SFP interface modules.
2. a kind of multi-channel wide band signal high speed acquisition based on JESD204B agreements according to claim 1 is with forwarding
System, which is characterized in that the high-speed data acquisition control module, SFP interface modules, PCIe endpoint 1590 interface module are integrated in FPGA
In chip.
3. a kind of multi-channel wide band signal high speed acquisition based on JESD204B agreements according to claim 1 or 2 with turn
Hair system, which is characterized in that the JESD204B receiving modules further include multiple monitoring decoding modules, link monitoring module, mistake
Accidentally processing module and Clock management module, the multiple high-speed transceiver from high-speed ADC array module for receiving data, institute
Each stated in multiple monitoring decoding modules is connect with one of in the multiple high-speed transceiver respectively, the link
Monitoring module is connect with the multiple monitoring decoding module, and error handling module is connect with link monitoring module, and the monitoring is translated
Code module is used to carry out comma detection to the JESD204B data that corresponding gigabit high-speed transceiver GTX is received and character is translated
Code, counting and monitoring high-speed transceiver of the link monitoring module for monitoring the control character occurred in respective links in real time
The inconsistent marking signal of operation of feedback, the error handling module are used to, when mistake occurs for link, judge whether link needs
It re-establishes, and gives up the data received at this time.
4. a kind of multi-channel wide band signal high speed acquisition based on JESD204B agreements according to claim 2 is with forwarding
System, which is characterized in that the cache module is the SDRAM chips based on DDR3 interfaces, and the multichannel cache controller is
SDRAM cache controllers；The multichannel cache controller passes through the MIG built in fpga chipIPVerify existing, the multichannel
Cache controller includes MIG IP modules, write process module, reads scheduler module, command process module, an input interface and two
A output interface, the MIG IP modules are for directly controlling SDRAM chips, the write process module and reading process mould
Block is communicated by input interface and output interface with the user interface of MIG IP respectively, is respectively utilized to complete the write-in and reading of data
Go out, the command process module realizes choosing of the sampled data to two different paths for receiving and decoding top level control signal
Distribution is selected, while returning to read-write operation and completing signal.
5. a kind of multi-channel wide band signal high speed acquisition based on JESD204B agreements according to claim 4 is with forwarding
System, which is characterized in that the SFP interface modules include the combination of four-way high-speed transceiver、Link initialization unit, Row control
Unit, status control unit, reception data unwrapper unit, transmission data packaged unit and fifo module, the PCIe endpoint 1590 connect
Mouth mold block includes 8 channel high-speed transceiver combinations, PCIe stones, PIO modules and dma module, the PIO modules for realizing
Control signal stream between fpga chip and host computer exchanges, the dma module for realizing sampled data to host computer it
Between high-speed uploading.
6. a kind of multi-channel wide band signal high speed acquisition based on JESD204B agreements according to claim 5 is with forwarding
System, which is characterized in that the acquisition of its data includes the following steps with forwarding：
（1）JESD204B receiving modules first determine whether link is correctly established, after link is completely established, the collecting flowchart
Management module acquires array to high-speed ADC by SPI interface and sends ADC control stream signals, and high-speed ADC acquisition array starts to acquire
Data, and it is output to JESD204B receiving modules after converting data to JESD204B data formats；
（2）JESD204B receiving modules receive data by high-speed transceiver and are sent into cache module caching；
（3）Transmission control module initiates DMA request by PCIe endpoint 1590 interface module to host computer, and passes through PCIe endpoint 1590 interface
Module is converted to the data in cache module after PCIe format through 8 channel link high-speed uploadings to host computer；
（4）Transmission control module sends out the handshake with communication test set by Aurora agreements, and passes through SFP interface moulds
After block is encoded the data in cache module by the coding mode of 8B/10B, uploads to communication by 4 channel links and survey
Try equipment.
7. a kind of multi-channel wide band signal high speed acquisition based on JESD204B agreements according to claim 6 is with forwarding
System, which is characterized in that the host computer be embedded computer, the communication test set be Mass Data Storage Facility or
Large Volume Data analyzing processing equipment.
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| CN108322483B (en) * | 2018-04-10 | 2020-12-29 | 北京航空航天大学 | Realization method of receiving end circuit based on JESD204B protocol |
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| CN110618963A (en) * | 2018-06-19 | 2019-12-27 | 上海威固信息技术股份有限公司 | Heterogeneous computing hardware acceleration system and method integrating computing and storage |
| CN109783418B (en) * | 2018-12-21 | 2020-05-01 | 中北大学 | High-speed acquisition and waveform storage analysis system for broadband signals |
| CN110445727B (en) * | 2019-07-11 | 2023-04-18 | 南京理工大学 | Data cache transmission device for high-speed ADC performance test |
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