CN107134479A - Self assembly FET and its manufacture method based on two dimensional crystal material - Google Patents
Self assembly FET and its manufacture method based on two dimensional crystal material Download PDFInfo
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The present invention discloses a kind of self assembly FET based on two dimensional crystal material, it is a kind of three-dimensional FET of micro-tubular that the FET buries gate field-effect transistor self assembly using planar of the silicon nitride SiNx stressor layers driving based on two dimensional crystal material, including monocrystalline substrate, stressor layers, dielectric layer, two dimensional crystal material layer, gate electrode, source electrode and drain electrode；Stressor layers, two dimensional crystal material layer, the gate electrode in stressor layers, dielectric layer, the source electrode in two dimensional crystal material layer and drain electrode are into curly.Invention additionally discloses a kind of preparation method of the self assembly FET based on two dimensional crystal material.The present invention can batch micro operations three-dimensional micro formula FET at lower cost, significantly reduce chip area footprints, and be combined the advantage of FET sensitivity height, strong applicability with the excellent electricity of two dimensional crystal material, optics, magnetism characteristic to improve device performance, expand device application.
Description
Technical field
The present invention relates to semi-conductor electronic device technical field.More particularly, to a kind of based on two dimensional crystal material
Self assembly FET and its manufacture method.
Background technology
Field-effect transistor (Field Effect Transistor, FET) abbreviation FET, mainly there is two types：
Junction field effect transistor (Junction Field-Effect Transistor, JFET) and Metal-Oxide Semiconductor
Effect pipe (metal-oxide semiconductor FET, abbreviation MOS-FET).FET is to utilize control input loop
Field effect carry out a kind of semiconductor devices of output control loop electric current, and named with this.It belongs to voltage-controlled type and partly led
Body device, with input resistance high (107~1015 Ω), noise is small, low in energy consumption, dynamic range is big, be easily integrated, not secondary
The advantages of punch-through, safety operation area field width, the powerful competitor as bipolar transistor and power transistor.By
The majority carrier only leaned in it in semiconductor is conductive, also known as unipolar transistor.FET is by changing applied voltage
The electric-field intensity of generation controls the semiconductor devices of its conductive capability.It is not only the elementary cell of electronic circuit, Er Qie
The numerous areas such as energy harvester, inverter, stabilizer, sensor have a wide range of applications.And based on two dimensional crystal material
FET, can be by the excellent electricity of microcosmic lower two dimensional crystal material, magnetics, light on the premise of FET advantage is kept
Learn performance with it is macroscopical under ultra-thin property, the transparency, pliability be organically combined together, realize miniaturization and the function of device
Maximize.
The existing FET based on two dimensional crystal material, its structure is limited in two dimensional surface mostly, in structure
Many deficiencies in the application that limitation is brought.First, the existing FET based on two dimensional crystal material is due to its plane
The limitation of two-dimensional structure is, it is necessary to take larger chip area, it is difficult to make full use of chip space resource.By reducing field-effect
The characteristic size of pipe can reach the purpose for reducing chip area, but the reduction of characteristic size can bring the non-linear of R＆D costs
Increase.Secondly, the planar structure based on two dimensional crystal material FET greatly limit it as sensor
Performance.Plane field-effect cast photodetector for example based on two dimensional crystal material, it is brilliant as the planar of light-sensitive material
Body material is relatively low to the absorptivity of light, and the light radiation that planar monolayer light-sensitive material is received can be with the increase of angle of light
Reduce, cause its absorptivity and light utilization efficiency wretched insufficiency.And for example, the plane field-effect cast life based on two dimensional crystal material
Change sensor and often use backgate or liquid grid structure so that two dimensional crystal materials conductive raceway groove is sufficiently exposed in test environment.
The work grid voltage of backgate plane FET is often higher (~50V), causes it to be difficult to meet weak electric signal and implanted detection
Requirement so that seriously limit its application.Liquid grid plane FET causes its electricity due to the presence of solid liquid interface electric double layer
Learn characteristic and be difficult Accurate Analysis, so that the sensitivity of its detection and precision have much room for improvement.
Compared with the plane field-effect tube structure based on two dimensional crystal material, the three-dimensional field-effect based on two dimensional crystal material
Pipe is expected to obtain more preferable device performance, is expected to due to its unique space structure advantage while chip utilization rate is improved
Fundamentally solve the above problems.Duy in 2014 et al. takes the lead in reporting a kind of three-dimensional (3D) graphene field effect tube sensor.
The devices use photoresist makes miniature cylinder array in sensor conductive channel region, and coats stone on cylindrical-array surface
Black alkene material so that graphene and the haptoreaction area of tested substance are greatly increased in unit chip area, so as to improve
The sensitivity of sensor.The internal stress that Deng in 2015 et al. is formed under non-abundant exposure using SU-8 photoresists is by graphite
Alkene film is assembled into programmable graphics 3D devices, realizes the detection to acetone.But, because SU-8 stress direction can not
Adjust, stress value is smaller, radius of curvature is larger (>=250 μm), and graphene field effect tubular construction relatively difficult to achieve, so as to limit it
Using.
Accordingly, it is desirable to provide a kind of self assembly FET and its manufacture method based on two dimensional crystal material.
The content of the invention
In view of the above-mentioned problems, the present invention propose it is a kind of based on the self assembly FET of two dimensional crystal material and its manufacture
Method, can three-dimensional (3D) micro-tubular FET of batch micro operations at lower cost, significantly reduce chip area footprints, and
The advantage of FET sensitivity height, strong applicability is combined with the excellent electricity of two dimensional crystal material, optics, magnetism characteristic
To improve device performance, device application is expanded.
It is an object of the present invention to provide a kind of self assembly FET based on two dimensional crystal material.On reaching
Purpose is stated, the present invention uses following technical proposals：
A kind of self assembly FET based on two dimensional crystal material, the FET is driven using silicon nitride SiNx stressor layers
It is a kind of three-dimensional FET of micro-tubular, specific bag that the dynamic planar based on two dimensional crystal material, which buries gate field-effect transistor self assembly,
Include：
Monocrystalline substrate 1；
The sacrifice layer 2 of monocrystalline substrate 1 is arranged in manufacturing process；
It is arranged on the stressor layers 3 on monocrystalline substrate 1 and sacrifice layer 2；
After completing, sacrifice layer 2 is etched；
A part is arranged in monocrystalline substrate 1, and another part is arranged on the gate electrode 7 in stressor layers 3；
It is arranged on the dielectric layer 6 in stressor layers 3 and gate electrode 7；
It is arranged on the two dimensional crystal material layer 4 on dielectric layer 6；
A part is arranged in monocrystalline substrate 1, another part be arranged in two dimensional crystal material layer 4 with gate electrode 7
Parallel and equidistant source electrode 8 and drain electrode 5；
Two dimensional crystal material layer 4, dielectric layer 6, source electrode 8, drain electrode 5 and the formation of gate electrode 7 one are based on two dimensional crystal
The planar of material buries gate field-effect transistor；
Wherein, stressor layers 3, two dimensional crystal material layer 4, the gate electrode 7 in stressor layers 3, dielectric layer 6, two dimensional crystal material
5 one-tenth of source electrode 8 and drain electrode on layer 4 are curly.
Preferably, sacrifice layer 2 will not be to two dimensional crystal material for the etching liquid of the metal material such as aluminium Al or copper Cu and sacrifice layer 2
The bed of material 4, drain electrode 5, dielectric layer 6, gate electrode 7, source electrode 8 and stressor layers 3 produce influence.
Preferably, two dimensional crystal material layer 4 is graphene or class grapheme material.
Preferably, dielectric layer 6 is silica SiO2Etc. dielectric layer material, or alundum (Al2O3) Al2O3, hafnium oxide
HfO2Deng the dielectric layer material of high-k.
Preferably, drain electrode 5, gate electrode 7 and source electrode 8 are using chrome gold (Cr/Au), titanium/gold (Ti/Au), palladium/gold
(Pd/Au), the conventional two dimensional crystal electrode material such as titanium/platinum (Ti/Pt) makes, wherein, chromium (Cr), titanium (Ti), palladium (Pd) etc. glue
Attached layer material thickness is 5nm-30nm, and the conductive layer thickness such as golden (Au), platinum (Pt) is 10nm-100nm.
Preferably, stressor layers 3 are SiNx double membrane structures, heavy using PECVD on sacrifice layer 2
The SiNx films with compression and tension that product technology is sequentially prepared.Wherein, the upper strata in double membrane structure is with pressure
Lower floor in the SiNx films of stress, double membrane structure is the SiNx films with tension.
It is further preferred that there is the SiNx films of tension to have the trend expanded along film surface for lower floor, upper strata has pressure
The SiNx films of stress have the trend shunk along film surface so that the driving two dimensional crystal of stressor layers 3 material layer 4, dielectric layer 6, leakage
The two dimension based on two dimensional crystal material that electrode 5, gate electrode 7 and source electrode 8 are constituted buries gate field-effect transistor self assembly for micro-tubular
Self assembled three-dimensional FET based on two dimensional crystal material.
It is further preferred that 360 ° of the stress intensity and curl direction of stressor layers 3 are strict controllable；Micro-tubular structure radius is by answering
The stress intensity decision of power layer 3, micro-tubular structure radius controllable precise in 4~500 μ ms.
It is another object of the present invention to provide a kind of making of the self assembly FET based on two dimensional crystal material
Method.To reach above-mentioned purpose, the present invention uses following technical proposals：
A kind of preparation method of the self assembly FET based on two dimensional crystal material, this method comprises the following steps：
S1：Cleaning silicon chip simultaneously makes sacrifice layer：It is 1 that monocrystalline silicon piece 1 is placed in into proportioning:4 hydrogen peroxide and sulfuric acid mixture liquid
In, silicon chip is boiled into 15min under 85 degrees Celsius, superficial stain is removed, with deionized water rinsing, drying；It is sharp on monocrystalline silicon piece 1
Sacrifice layer 2 is made with photoetching technique, film deposition technique and lift-off technology, the thickness of sacrifice layer 2 is 10~200nm；
S2：Make stressor layers：Pass through plasma-reinforced chemical vapor deposition deposition techniques SiNx layer；Existed using photoetching technique
The region of stressor layers 3 forms photoresist mask layer；The SiNx layer of unglazed photoresist covering is removed using reactive ion etching；It is clear with acetone
Photoresist is washed, the figure of stressor layers 3 is left, the preparation of stressor layers 3 is completed；
S3：Make gate electrode：Photoresist perforate is formed in the region of gate electrode 7 by photoetching；Steamed with thermal evaporation or electron beam
Hair or magnetron sputtering technique deposit metal material；The metal material of photoresist and attachment on a photoresist is removed using stripping technology
Material, leaves electrode pattern, completes the preparation of gate electrode 7；
S4：Make dielectric layer：Pass through the thin-film deposition skill such as plasma-reinforced chemical vapor deposition technology or atomic layer deposition
Art deposition of dielectric layer 6, thickness is 5-50nm；Using photoetching technique photoresist mask layer is formed in the region of dielectric layer 6；Using reaction
Ion etching removes the dielectric layer 6 of unglazed photoresist covering；Photoresist is cleaned with acetone, the figure of dielectric layer 6 is left, dielectric layer is completed
6 preparation；
S5：Shift and graphical two dimensional crystal material layer：Two dimensional crystal is shifted in stressor layers (3) and dielectric layer (6)
Material layer (4)；Using photoetching technique, with photoresist as barrier layer, unglazed photoresist is etched with oxygen gas plasma lithographic technique
The two dimensional crystal material layer 4 of covering；The photoresist on the surface of two dimensional crystal material layer 4 is cleaned with acetone, two dimensional crystal material is completed
The transfer of layer 4 and graphical；
S6：Make source electrode and drain electrode：Photoresist perforate is formed in gate electrode 7 and the region of drain electrode 5 by photoetching；With
Thermal evaporation or electron beam evaporation technique deposit metal material；The gold of photoresist and attachment on a photoresist is removed using stripping technology
Belong to material, leave electrode pattern, complete the making of gate electrode 7 and drain electrode 5；
S7：Etching sacrificial layer：In the etching solution of chip immersion sacrifice layer 2, etching sacrificial layer 2；SiNx stressor layers 3 drive
Two dimensional crystal material layer 4, dielectric layer 6, source electrode 8, the two dimension based on two dimensional crystal material of the gate electrode 7 of drain electrode 5 composition are buried
Gate field-effect transistor self assembly is self assembled three-dimensional FET of the micro-tubular based on two dimensional crystal material.
Beneficial effects of the present invention are as follows：
(1) buried grid structure make it that ultra-thin dielectric layer is used, and enhances grid voltage to two dimensional crystal conductivity of material
Ability of regulation and control.The present invention innovatively proposes a kind of three-dimensional based on two dimensional crystal material using self-assembling technique and buries grating
Field-effect tube structure, on the one hand overcomes the problem of backgate device grid voltage is high, control ability is poor, on the other hand avoids liquid grid device
Part stability is poor, output signal and the nonlinear problem of charge-doping amount.FET has been widened in weak electric signal and implanted
The application in the fields such as detection, while being expected to realize higher sensitivity.
(2) introducing of three-dimensional structure reduces chip area footprints, improves space availability ratio, saved cost.This hair
It is bright under the conditions of existing process, utilize plane machining technology, obtain self assembly three dimensional field effect pipe.With two dimensional surface FET
Compare, self assembled three-dimensional FET is saved in high degree on the basis of research and development and the plate-making expense of new technology, is significantly subtracted
Lack chip area footprints, reduce cost.
(3) unique micro-tubular structure reduces the structural complexity and manufacture difficulty of FET sensor, improves
The performance of sensor.For the field-effect cast biochemical sensor based on two dimensional crystal material, in the μ m of radius 4~500
Adjustable micro-tubular structure has stronger capillarity to liquid test substance, can be by the solution to be measured of denier during work
It is automatically drawn into conduction channel region and completes detection.This self assembly FET is auxiliary without extra fluid channel, sealing device etc.
Part is helped, the structure of gate electrode and the application of gate voltage are also greatly simplified.And to the field-effect cast based on two dimensional crystal material
For photodetector, coaxial multi-layer micro-tubular structure provides a kind of new way to improve the absorptivity of two dimensional crystal material.
Individual layer two dimensional crystal material is relatively low to the absorptivity of light, but its absorptivity tends to vary with the increase of the number of plies and increased.Pass through adjustment
The stress intensity of high transmission rate SiNx stressor layers can control the number of plies of coaxial micro-pipe, you can increase individual layer two dimensional crystal material
Stacking number, thus improve its to absorptivity.Meanwhile, micro-tubular structure cause light source in the plane vertical with micro-pipe around
When micro-pipe axle moves in a circle, angle of light remains constant, that is, the light radiation received keeps constant.So as to significantly
Absorptivity and light utilization efficiency are improved, turning into the appearance based on the high sensitive photo detector of individual layer two dimensional crystal material can
Energy.
Brief description of the drawings
The embodiment to the present invention is described in further detail below in conjunction with the accompanying drawings.
Fig. 1 shows the structural representation of the self assembly FET based on two dimensional crystal material.
Fig. 2 shows the preparation method schematic diagram of the self assembly FET based on two dimensional crystal material.
Fig. 3 a show cleaning silicon chip and make sacrifice layer schematic diagram.
Fig. 3 b show to make stressor layers schematic diagram.
Fig. 3 c show to make gate electrode schematic diagram.
Fig. 3 d show to make dielectric layer schematic diagram.
Fig. 3 e show transfer and graphical two dimensional crystal material schematic diagram.
Fig. 3 f show to make source electrode and drain electrode schematic diagram.
Fig. 3 g show etching sacrificial layer schematic diagram.
It is the three-dimensional FET of micro-tubular that Fig. 3 h, which show that the two dimensional field based on two dimensional crystal material buries the self assembly of matrix effect pipe,
Schematic diagram.
Embodiment
In order to illustrate more clearly of the present invention, the present invention is done further with reference to preferred embodiments and drawings
It is bright.Similar part is indicated with identical reference in accompanying drawing.It will be appreciated by those skilled in the art that institute is specific below
The content of description is illustrative and be not restrictive, and should not be limited the scope of the invention with this.
As shown in figure 1, a kind of self assembly FET based on two dimensional crystal material, the FET utilizes silicon nitride
Planar of the SiNx stressor layers driving based on two dimensional crystal material buries gate field-effect transistor self assembly for a kind of micro-tubular three dimensional field
Effect pipe, is specifically included：Monocrystalline substrate 1；The sacrifice layer 2 of monocrystalline substrate 1 is arranged in manufacturing process；It is arranged on monocrystalline silicon
Stressor layers 3 on substrate 1 and sacrifice layer 2；After completing, sacrifice layer 2 is etched；A part is arranged on monocrystalline substrate 1
On, another part is arranged on the gate electrode 7 in stressor layers 3；It is arranged on the dielectric layer 6 in stressor layers 3 and gate electrode 7；It is arranged on
Two dimensional crystal material layer 4 on dielectric layer 6；A part is arranged in monocrystalline substrate 1, and another part is arranged on two dimensional crystal material
The source electrode 8 parallel and equidistant with gate electrode 7 and drain electrode 5 on the bed of material 4；Two dimensional crystal material layer 4, dielectric layer 6, source electrode
8th, drain electrode 5 and one planar based on two dimensional crystal material of formation of gate electrode 7 bury gate field-effect transistor；Wherein, stressor layers
3rd, two dimensional crystal material layer 4, the gate electrode 7 in stressor layers 3, dielectric layer 6, the source electrode 8 in two dimensional crystal material layer 4 and electric leakage
Pole 5 is into curly.
In the present invention, sacrifice layer 2 will not be to two dimensional crystal for the etching liquid of the metal material such as aluminium Al or copper Cu and sacrifice layer 2
Material layer 4, drain electrode 5, dielectric layer 6, gate electrode 7, source electrode 8 and stressor layers 3 produce influence.Two dimensional crystal material layer 4 is stone
Black alkene or class grapheme material.Dielectric layer 6 is silica SiO2Etc. dielectric layer material, or alundum (Al2O3) Al2O3, dioxy
Change hafnium HfO2Deng the dielectric layer material of high-k.Drain electrode 5, gate electrode 7 and source electrode 8 using chrome gold (Cr/Au), titanium/
The conventional two dimensional crystal electrode material such as golden (Ti/Au), palladium/gold (Pd/Au), titanium/platinum (Ti/Pt) makes, wherein, chromium (Cr), titanium
(Ti), the adhesive layer material thickness such as palladium (Pd) is 5nm-30nm, and the conductive layer thickness such as golden (Au), platinum (Pt) is 10nm-100nm.
In the present invention, self assembly principle is as follows：Stressor layers 3 are SiNx double membrane structures, and plasma is utilized on sacrifice layer 2
The SiNx films with compression and tension that body enhancing chemical vapour deposition technique is sequentially prepared.Wherein, double membrane structure
In upper strata be the SiNx films with compression, the lower floor in double membrane structure is the SiNx films with tension.Lower floor
SiNx films with tension have the trend that is expanded along film surface, and upper strata there is the SiNx films of compression to have receive along film surface
The trend of contracting so that the driving two dimensional crystal of stressor layers 3 material layer 4, dielectric layer 6, drain electrode 5, gate electrode 7 and source electrode 8 are constituted
The two dimension based on two dimensional crystal material bury gate field-effect transistor self assembly for self assembly three of the micro-tubular based on two dimensional crystal material
Tie up FET.
In the present invention, 360 ° of the stress intensity and curl direction of stressor layers 3 are strict controllable；Micro-tubular structure radius is by stressor layers
3 stress intensity and thickness decision, micro-tubular structure radius controllable precise in 4~500 μ ms.
In the present invention, micro-pipe Micro-tubular structures are stressor layers 3, two dimensional crystal material layer 4, the grid in stressor layers 3
Electrode 7, dielectric layer 6, a kind of tubular structure of 5 one-tenth curly formation of source electrode 8 and drain electrode in two dimensional crystal material layer 4.
As shown in Fig. 2 present invention also offers a kind of making side of the self assembly FET based on two dimensional crystal material
Method, this method comprises the following steps：
S1：As shown in Figure 3 a, cleaning silicon chip and sacrifice layer is made：
S101：It is 1 that monocrystalline silicon piece 1 is placed in into proportioning:In 4 hydrogen peroxide and sulfuric acid mixture liquid, by silicon under 85 degrees Celsius
Piece boils 15min, removes superficial stain, with deionized water rinsing, drying；
S102：Sacrifice layer 2 is made using photoetching technique, film deposition technique and lift-off technology on monocrystalline silicon piece 1, is sacrificed
The thickness of layer 2 is 10~200nm；
S2：As shown in Figure 3 b, stressor layers are made：
S201：Pass through plasma-reinforced chemical vapor deposition deposition techniques SiNx layer；
S202：Using photoetching technique photoresist mask layer is formed in the region of stressor layers 3；
S203：The SiNx layer of unglazed photoresist covering is removed using reactive ion etching；
S204：Photoresist is cleaned with acetone, the figure of stressor layers 3 is left, the preparation of stressor layers 3 is completed；
S3：As shown in Figure 3 c, gate electrode is made：
S301：Photoresist perforate is formed in the region of gate electrode 7 by photoetching；
S302：With thermal evaporation or electron beam evaporation or magnetron sputtering technique deposit metal material；
S303：The metal material of photoresist and attachment on a photoresist is removed using stripping technology, electrode pattern is left, it is complete
Into the preparation of gate electrode 7；
S4：As shown in Figure 3 d, dielectric layer is made：
S401：Dielectric is deposited by film deposition techniques such as plasma-reinforced chemical vapor deposition technology or atomic layer depositions
Layer 6, thickness is 5-50nm；
S402：Using photoetching technique photoresist mask layer is formed in the region of dielectric layer 6；
S403：The dielectric layer 6 of unglazed photoresist covering is removed using reactive ion etching；
S404：Photoresist is cleaned with acetone, the figure of dielectric layer 6 is left, the preparation of dielectric layer 6 is completed；
S5：As shown in Figure 3 e, transfer and graphical two dimensional crystal material layer：
S501：Two dimensional crystal material layer is shifted in stressor layers and dielectric layer；
S502：Using photoetching technique, with photoresist as barrier layer, etched with oxygen gas plasma lithographic technique non-lithography
The two dimensional crystal material layer 4 of glue covering；
S503：The photoresist on the surface of two dimensional crystal material layer 4 is cleaned with acetone, the transfer of two dimensional crystal material layer 4 is completed
With it is graphical；
S6：As illustrated in figure 3f, source electrode and drain electrode are made：
S601：Photoresist perforate is formed in gate electrode 7 and the region of drain electrode 5 by photoetching；
S602：With thermal evaporation or electron beam evaporation technique deposit metal material；
S603：The metal material of photoresist and attachment on a photoresist is removed using stripping technology, electrode pattern is left, it is complete
Into the making of gate electrode 7 and drain electrode 5；
S7：As shown in figure 3g, etching sacrificial layer：
S701：In the etching solution of chip immersion sacrifice layer 2, etching sacrificial layer 2；
S702：The driving two dimensional crystal of SiNx stressor layers 3 material layer 4, dielectric layer 6, source electrode 8,7 groups of 5 gate electrode of drain electrode
Into the two dimension based on two dimensional crystal material bury gate field-effect transistor self assembly for self assembly of the micro-tubular based on two dimensional crystal material
Three-dimensional FET, as illustrated in figure 3h,.
Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair
The restriction of embodiments of the present invention, for those of ordinary skill in the field, may be used also on the basis of the above description
To make other changes in different forms, all embodiments can not be exhaustive here, it is every to belong to this hair
Row of the obvious changes or variations that bright technical scheme is extended out still in protection scope of the present invention.
Claims (8)
1. a kind of self assembly FET based on two dimensional crystal material, it is characterised in that including：
Monocrystalline substrate (1)；
It is arranged on the stressor layers (3) in the monocrystalline substrate (1)；
A part is arranged in the monocrystalline substrate (1), and another part is arranged on the gate electrode (7) in the stressor layers (3)；
It is arranged on the dielectric layer (6) in the stressor layers (3) and gate electrode (7)；
It is arranged on the two dimensional crystal material layer (4) on the dielectric layer (6)；
A part is arranged in the monocrystalline substrate (1), another part be arranged on the two dimensional crystal material layer (4) with
The parallel and equidistant source electrode (8) of the gate electrode (7) and drain electrode (5)；
Wherein, stressor layers (3), the two dimensional crystal material layer (4), the gate electrode (7) in the stressor layers (3), described
The source electrode (8) and the drain electrode (5) on dielectric layer (6), the two dimensional crystal material layer (4) are into curly.
2. the self assembly FET according to claim 1 based on two dimensional crystal material, it is characterised in that the two dimension
Crystal material layer (4) is graphene or class grapheme material.
3. the self assembly FET according to claim 1 based on two dimensional crystal material, it is characterised in that the dielectric
Layer (6) is SiO2The gate dielectric material of gate dielectric material or high-k.
4. the self assembly FET according to claim 1 based on two dimensional crystal material, it is characterised in that the electric leakage
In pole (5), gate electrode (7) and source electrode (8), adhesive layer material thickness is 5nm-30nm, and conductive layer thickness is 10nm-100nm.
5. the self assembly FET according to claim 1 based on two dimensional crystal material, it is characterised in that the stress
Layer (3) is SiNx double membrane structures, wherein, the upper strata in double membrane structure is the SiNx films with compression, duplicature knot
Lower floor in structure is the SiNx films with tension.
6. the self assembly FET according to claim 5 based on two dimensional crystal material, it is characterised in that the stress
Layer (3) drives the two dimensional crystal material layer (4), the dielectric layer (6), the drain electrode (5), the gate electrode (7) and institute
State source electrode (8) composition the two dimension based on two dimensional crystal material bury gate field-effect transistor self assembly for micro-tubular be based on two dimensional crystal
The self assembled three-dimensional FET of material.
7. the self assembly FET according to claim 6 based on two dimensional crystal material, it is characterised in that described
The stress intensity and curl direction of stressor layers (3) are controllable；Micro-tubular structure radius determines by the stress intensity of the stressor layers (3),
The micro-tubular structure radius is controllable in 4~500 μ ms.
8. a kind of preparation method of the self assembly FET based on two dimensional crystal material, it is characterised in that this method include with
Lower step：
S1：Cleaning silicon chip simultaneously makes sacrifice layer：It is 1 that monocrystalline silicon piece (1) is placed in into proportioning:In 4 hydrogen peroxide and sulfuric acid mixture liquid,
Silicon chip is boiled into 15min under 85 degrees Celsius, superficial stain is removed, with deionized water rinsing, drying；It is sharp on monocrystalline silicon piece (1)
Make sacrifice layer (2) with photoetching technique, film deposition technique and lift-off technology, the thickness of the sacrifice layer (2) for 10~
200nm；
S2：Make stressor layers：Pass through plasma-reinforced chemical vapor deposition deposition techniques SiNx layer；Using photoetching technique in stress
Layer (3) region forms photoresist mask layer；The SiNx layer of unglazed photoresist covering is removed using reactive ion etching；Cleaned with acetone
Photoresist, leaves stressor layers (3) figure, completes the preparation of stressor layers (3)；
S3：Make gate electrode：Photoresist perforate is formed in gate electrode (7) region by photoetching；With thermal evaporation or electron beam evaporation
Or magnetron sputtering technique deposit metal material；The metal material of photoresist and attachment on a photoresist is removed using stripping technology
Material, leaves electrode pattern, completes the preparation of gate electrode (7)；
S4：Make dielectric layer：Formed sediment by film deposition techniques such as plasma-reinforced chemical vapor deposition technology or atomic layer depositions
Product dielectric layer (6), thickness is 5-50nm；Using photoetching technique photoresist mask layer is formed in dielectric layer (6) region；Using reaction
Ion etching removes the dielectric layer (6) of unglazed photoresist covering；Photoresist is cleaned with acetone, dielectric layer (6) figure is left, completes to be situated between
The preparation of electric layer (6)；
S5：Shift and graphical two dimensional crystal material layer：Two dimensional crystal material is shifted in stressor layers (3) and dielectric layer (6)
Layer (4)；Using photoetching technique, with photoresist as barrier layer, etch unglazed photoresist with oxygen gas plasma lithographic technique and cover
Two dimensional crystal material layer (4)；The photoresist on two dimensional crystal material layer (4) surface is cleaned with acetone, two dimensional crystal material is completed
The transfer of layer (4) and graphical；
S6：Make source electrode and drain electrode：Photoresist perforate is formed in gate electrode (7) and drain electrode (5) region by photoetching；With
Thermal evaporation or electron beam evaporation technique deposit metal material；The gold of photoresist and attachment on a photoresist is removed using stripping technology
Belong to material, leave electrode pattern, complete the making of gate electrode (7) and drain electrode (5)；
S7：Etching sacrificial layer：In the etching solution of chip immersion sacrifice layer (2), etching sacrificial layer (2)；SiNx stressor layers (3) are driven
Dynamic two dimensional crystal material layer (4), dielectric layer (6), source electrode (8), drain electrode (5) gate electrode (7) composition based on two dimensional crystal
The two dimension of material buries gate field-effect transistor self assembly for self assembled three-dimensional FET of the micro-tubular based on two dimensional crystal material.
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