CN112151629A - Micro-tube type three-dimensional heterojunction device structure and preparation method and application thereof - Google Patents

Micro-tube type three-dimensional heterojunction device structure and preparation method and application thereof Download PDF

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CN112151629A
CN112151629A CN202011003961.XA CN202011003961A CN112151629A CN 112151629 A CN112151629 A CN 112151629A CN 202011003961 A CN202011003961 A CN 202011003961A CN 112151629 A CN112151629 A CN 112151629A
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heterojunction
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wall electrode
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CN112151629B (en
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王�琦
徐际宇
刘昊
袁学光
柴昭尔
刘凯
任晓敏
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Beijing University of Posts and Telecommunications
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Abstract

The invention relates to a micro-tube type three-dimensional heterojunction device structure and a preparation method and application thereof, wherein the structure comprises the following components: the micro-tube type semiconductor three-dimensional heterojunction device comprises a micro-tube type semiconductor two-dimensional material three-dimensional heterojunction, an inner wall electrode, an outer wall electrode and a substrate; the inner wall electrode only forms electric contact with the inner wall material of the micro-tube type three-dimensional heterojunction; the outer wall electrode only forms electric contact with the outer wall material of the micro-tube type three-dimensional heterojunction; the inner wall electrode and the outer wall electrode are insulated from the substrate; the microtube type semiconductor two-dimensional material three-dimensional heterojunction is a tubular three-dimensional heterojunction formed by self-curling of a semiconductor two-dimensional material planar heterojunction on a substrate. The invention solves the problem that a tubular three-dimensional heterojunction device cannot be prepared, has simple process, can simultaneously realize the preparation of the micro-tube type three-dimensional heterojunction and the electric contact between the outer wall material and the outer wall electrode, ensures that the current only passes through the micro-tube type three-dimensional heterojunction in the radial direction and does not pass through the plane heterojunction, and can be widely applied to the fields of photoelectric detection, photovoltaics, gas sensing, electronic components and the like.

Description

Micro-tube type three-dimensional heterojunction device structure and preparation method and application thereof
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a micro-tube type three-dimensional heterojunction device structure and a preparation method and application thereof.
Background
The strain-driven micro-nano self-curling technology is the three-dimensional assembly (3D assembly) technology which is put forward at the earliest time, can convert a planar semiconductor structure into a tubular three-dimensional structure with a hollow channel, has a simple preparation process, is completely compatible with the existing microelectronic process and optoelectronic process, and has important application prospects in various fields. In 2000, Prinz et al, Russian academy of sciences, successfully produced InGaAs/GaAs self-curling nanotubes (Prinz V Y, Seleznev V A, Gutakovsky A K, et al. free-standing and overgrown InGaAs/GaAs nanotubes, nanohelixes and their arrays [ J ]. Physica E,2000,6(1-4):828-831) on GaAs substrates using self-curling technology for the first time. In 2001, Schmidt et al, the institute for solid and materials, Labunitz, Germany, reported the work of fabricating self-curling SiGe microtubes on Si substrates, further expanding the material systems for which the micro-nano self-curling technology is applicable (Schmidt O G, Eberl K. thin dissolved films up into nano tubes [ J ] Nature,2001,410(6825): 168-. In 2017, the royal topic group of beijing postal and telecommunications university realizes the simultaneous self-curling of the CVD graphene and InGaAs/GaAs strain double-layer structure, and a tubular InGaAs/GaAs/graphene three-dimensional heterostructure, also called a micropipe-type InGaAs/GaAs/graphene three-dimensional heterojunction (guest Mao, Qi Wang, et al. reaction of unified strain, rolled-up monocrystalline CVD graphene on a Si planar for a via epitaxial/GaAs bilayers [ J ] RSC Advances,2017,7(24):14481 14486 @), is prepared for the first time, so that the self-curling range of the nanotube and the heterostructure is greatly expanded, but the tubular heterojunction cannot be applied as a device because the electrode cannot be provided for the tubular heterojunction, that is, the tubular heterojunction does not have a device function.
At present, no microtube type three-dimensional heterojunction is used for devices such as a photoelectric detector, a gas sensor, a solar cell and the like, and the reason is that to ensure the normal work of the microtube type three-dimensional heterojunction device, an inner wall electrode and an outer wall electrode of the microtube type three-dimensional heterojunction are required to be configured, so that current can only flow through the heterojunction along the radial direction of a tubular structure when the device works, the influence of the current flowing through a planar heterojunction on the microtube type three-dimensional heterojunction device is avoided, and meanwhile, the preparation process of the electrode is completely compatible with the self-curling tube manufacturing process, and the difficulty is extremely high. The design concept and the preparation process of the existing heterojunction device serve for a planar two-dimensional heterojunction device, and the problem of electrode preparation of a micro-tube type three-dimensional heterojunction device cannot be solved.
Disclosure of Invention
The embodiment of the invention provides a micro-tube type three-dimensional heterojunction device structure, which solves the problem that a micro-tube type three-dimensional heterojunction device in the prior art cannot be prepared.
The embodiment of the invention provides a micro-tube type three-dimensional heterojunction device structure, which comprises: the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction, an inner wall electrode, an outer wall electrode and a substrate; wherein the inner wall electrode only forms an electric contact with the inner wall material of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction; the outer wall electrode only forms electrical contact with the outer wall material of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction; the inner wall electrode and the outer wall electrode are insulated from the substrate; the microtube type semiconductor/two-dimensional material three-dimensional heterojunction is a tubular three-dimensional heterojunction formed by self-coiling of a semiconductor/two-dimensional material planar heterojunction on the substrate.
In some embodiments, the semiconductor/two-dimensional material planar heterojunction is a planar heterojunction in which a two-dimensional material and a semiconductor are stacked up and down by van der waals force. Preferably, the two-dimensional material is stacked with van der waals forces on top and the semiconductor on the bottom.
In some embodiments, the semiconductor/two-dimensional material planar heterojunction has a strain, preferably the strain is introduced by the semiconductor; the bottom of the semiconductor/two-dimensional material plane heterojunction is provided with a sacrificial layer; and after the sacrificial layer is removed, the semiconductor/two-dimensional material planar heterojunction is separated from the substrate, stress is released, and the semiconductor/two-dimensional material planar heterojunction is self-curled into a micro tube or a nano tube to form the semiconductor/two-dimensional material micro tube type three-dimensional heterojunction, wherein the number of self-curling turns is more than or equal to 1 turn. The semiconductor/two-dimensional material planar heterojunction is preferably upwards self-curled to form a microtube, namely upwards self-curled to form a microtube type semiconductor/two-dimensional material three-dimensional heterojunction, and the number of curling turns of the microtube type semiconductor/two-dimensional material planar heterojunction is at least one.
In some embodiments, the inner wall electrode and the outer wall electrode are flat plate electrodes in a coplanar configuration without any cross-over overlap between the inner wall electrode and the outer wall electrode; and/or before the semiconductor/two-dimensional material plane heterojunction is curled, the inner wall electrode and the outer wall electrode are positioned at the same side of the semiconductor/two-dimensional material plane heterojunction, and part of the inner wall electrode is pressed on the semiconductor/two-dimensional material plane heterojunction, namely, the contact between the inner wall electrode and the semiconductor/two-dimensional material plane heterojunction is realized; a space is reserved between the outer wall electrode and the semiconductor/two-dimensional material plane heterojunction, namely the outer wall electrode does not contact with the semiconductor/two-dimensional material plane heterojunction at all; and/or the curling direction of the semiconductor/two-dimensional material plane heterojunction is towards the inner wall electrode and the outer wall electrode, the inner wall electrode curls along with the semiconductor/two-dimensional material plane heterojunction, or the inner wall electrode does not curl along with the semiconductor/two-dimensional material plane heterojunction, and preferably the inner wall electrode does not curl along with the semiconductor/two-dimensional material plane heterojunction; and/or the semiconductor/two-dimensional material planar heterojunction is self-curled into a micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction, the distance between the three-dimensional heterojunction and the outer wall electrode is gradually reduced, the curling action is continued until the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction advances to the outer wall electrode area, and the outer wall electrode and the outer wall material of the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction form electric contact.
In some embodiments, the semiconductor is selected from the group consisting of one or more of group IV, III-V, II-VI, IV-VI semiconductors, and other types of semiconductors that remain; and/or the two-dimensional material is selected from one or more of graphene, doped graphene, graphene derivatives, graphene alkyne, silylene, germylene, borolene, plumbene, stannene, black phosphorus, hexagonal boron nitride, transition metal sulfide TMDS, transition metal carbide, nitride or carbonitride MXene, transition metal nitride, metal oxide, exo semimetal, layered hydroxide LDH, two-dimensional superlattice, ternary and higher ternary multi-element two-dimensional materials; and/or the materials of the inner wall electrode and the outer wall electrode are respectively selected from one or more of Au, Pt, Ti, Cr, Ni, Ge, Pd, Cu, Ag, Fe and Co elements, and/or Indium Tin Oxide (ITO), and/or low-melting-point alloy consisting of low-melting-point metal elements such as Ga, In, Sn, Pb, Bi and the like. The semiconductor is a single layer or a plurality of layers; and/or the two-dimensional material is a single layer, a double layer, a few layers (3-10 layers) or a plurality of layers (more than 10 layers).
The embodiment of the invention also provides a preparation method of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction device structure, which comprises the following steps:
s01: depositing a buffer layer on a substrate;
s02: depositing a sacrificial layer on the buffer layer;
s03: depositing a semiconductor compressive strain layer and a semiconductor top layer on the sacrificial layer, thereby forming a semiconductor strain double layer and obtaining a complete epitaxial structure;
s04: photoetching and etching the epitaxial structure to form a U-shaped table top with two U-shaped arms, and exposing the sacrificial layer;
s05: depositing an insulating layer, and photoetching and etching a pattern on the insulating layer to enable the insulating layer to cover the rear end regions of the U-shaped arms on the two sides of the U-shaped table top and the region between the two U-shaped arms;
s06: transferring the two-dimensional material to a U-shaped table board, carrying out U-shaped patterning treatment on the two-dimensional material to form a semiconductor/two-dimensional material planar heterojunction, and extending the two-dimensional material to the insulating layer along a U-shaped arm;
s07: depositing an inner wall electrode and an outer wall electrode on the insulating layer, enabling the inner wall electrode to press the two-dimensional material, enabling the outer wall electrode to be located on the insulating layer between the two U-shaped arms, and enabling the outer wall electrode not to be in contact with the two-dimensional material and the U-shaped table top;
s08: covering the inner wall electrode, the outer wall electrode, the insulating layer and part of the U-shaped table top by photoresist with rectangular patterns;
s09: the sacrificial layer is laterally corroded by a wet method, so that the semiconductor/two-dimensional material planar heterojunction uncovered by the photoresist is separated from the substrate to release stress to generate directional curling, a micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction is formed, and meanwhile, the U-shaped table surface part covered by the photoresist is not curled due to the pressing of the photoresist;
s10: and removing the photoresist to expose the inner wall electrode and the outer wall electrode, continuously curling the U-shaped table surface part pressed by the photoresist, continuously curling the two U-shaped arms to form a suspended microtubule type semiconductor/two-dimensional material three-dimensional heterojunction, and climbing to the top area of the outer wall electrode to form electric contact between the outer wall of the microtubule type semiconductor/two-dimensional material three-dimensional heterojunction and the outer wall electrode.
The embodiment of the invention also provides a preparation method of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction device structure, which comprises the following steps:
s 01: depositing a buffer layer on a substrate;
s 02: depositing a sacrificial layer on the buffer layer;
s 03: depositing a semiconductor compressive strain layer and a semiconductor top layer on the sacrificial layer, thereby forming a semiconductor strain double layer and obtaining a complete epitaxial structure;
s 04: photoetching and etching the epitaxial structure to form a U-shaped table top with two U-shaped arms, so that a part of semiconductor compressive strain layer is left below the U-shaped table top, and the sacrificial layer is not exposed;
s 05: depositing an insulating layer, and photoetching and etching a pattern on the insulating layer to enable the insulating layer to cover the rear end regions of the U-shaped arms on the two sides of the U-shaped table top and the region between the two U-shaped arms;
s 06: transferring the two-dimensional material to a U-shaped table board, carrying out U-shaped patterning treatment on the two-dimensional material to form a semiconductor/two-dimensional material plane heterojunction, and enabling the two-dimensional material to extend onto an insulating layer along a U-shaped arm;
s 07: depositing an inner wall electrode and an outer wall electrode on the insulating layer, enabling the inner wall electrode to press the two-dimensional material, enabling the outer wall electrode to be located on the insulating layer between the two U-shaped arms, and enabling the outer wall electrode not to be in contact with the two-dimensional material and the U-shaped table top;
s 08: etching the semiconductor compressive strain layer remained in the step s04 on the other side of the U-shaped table top opposite to the inner wall electrode and the outer wall electrode to form an etching window, and exposing the sacrificial layer in the etching window;
s 09: covering the inner wall electrode, the outer wall electrode, the insulating layer and part of the U-shaped table top by photoresist with rectangular patterns;
s 10: the sacrificial layer is laterally corroded by a wet method through a corrosion window, so that the semiconductor/two-dimensional material planar heterojunction which is not covered by the photoresist is separated from the substrate to release stress and generate directional curling, the constraint of the residual semiconductor compressive strain layer is torn, the microtube type semiconductor/two-dimensional material three-dimensional heterojunction is formed, and meanwhile, the U-shaped table surface part covered by the photoresist is not self-curled due to the pressing of the photoresist;
s 11: and removing the photoresist, exposing the inner wall electrode and the outer wall electrode, continuously curling the U-shaped table-board part pressed by the photoresist, continuously curling the two U-shaped arms to form a complete suspended microtube type three-dimensional heterojunction of the semiconductor/two-dimensional material, climbing to the top of the outer wall electrode, and rolling on the top of the outer wall electrode, so that the outer wall electrode is rolled up and wound on the outer wall of the three-dimensional heterojunction, and the outer wall of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction is in electrical contact with the outer wall electrode.
In some embodiments, the substrate includes, but is not limited to, ceramic, glass, polymer, Si, Ge, diamond, SOI, GeOI, GaN, AlN, InN, ZnO, MgO, SiC, LiAlO2、LiGaO2、MgAl2O4、Al2O3、Ga2O3、GaAs、InP、GaP、InAs、GaSb、Si3N4、SiO2And various dummy substrates, preferably GaAs, InP, Si, Al2O3Substrates for growing single crystal semiconductors such as GaN; and/or, the semiconductor strained bilayer includes but is not limited to a Si/Si bilayer, a SiGe/Si bilayer, an InGaAs/GaAs bilayer, an InP/InGaAsP bilayer, an InGaAsP/InGaAsP bilayer, an InGaN/GaN bilayer, wherein the former in each set of the semiconductor strained bilayer is a semiconductor compressively strained layer and the latter is a semiconductor top layer, the semiconductor top layer being unstrained; and/or, the material of the insulating layer includes but is not limited to SiO2、Al2O3、Ta2O5、HfO2、Si3N4Polydimethylsiloxane (PDMS), and the insulating layer has a resistivity of not less than 1 × 103Omega cm, the thickness is 5-300 nm; and/or, the sacrificial layer includes, but is not limited to, AlGaAs, AlAs, InGaP, AlInP, AlP, GaN, AlN, AlGaN, Ge, SiO2And photoresist (photoresist).
In some embodiments, after the outer wall electrode is contacted with the outer wall material of the microtube-type semiconductor/two-dimensional material three-dimensional heterojunction, the outer wall electrode is subjected to treatment for reducing contact resistance, wherein the treatment comprises one or more of dropping conductive adhesive, heat treatment, ultrasonic welding and chemical treatment.
In some embodiments, both step S04 and step S04 further include: carrying out hole digging operation on the U-shaped table top to expose the sacrificial layer from the hole; in the present invention, the shape of the hole includes, but is not limited to, circular, oval, square, rectangle, etc., preferably one or more of circular, oval, square and rectangle, the number of the hole is not required, and the depth of the hole ensures that the sacrificial layer is exposed from the hole; and/or, the two-dimensional material surface incorporates a surface nanoparticle layer or a surface passivation layer; and/or, a semiconductor quantum well or a semiconductor quantum dot gain medium is introduced into the semiconductor; and/or, the interface of the two-dimensional material and the semiconductor is introduced into an interface oxide layer or an interface nitride layer.
The embodiment of the invention also provides the application of the micro-tube type three-dimensional heterojunction device structure or the micro-tube type three-dimensional heterojunction device structure prepared by the method in photoelectric detection, photovoltaics, gas sensing and electronic components.
The inventor finds that the invention provides a micro-tube type three-dimensional heterojunction device structure, and effectively solves the problem that a micro-tube type three-dimensional heterojunction device in the prior art cannot be prepared. The invention also has the beneficial effects that: the invention discloses a micro-tube type three-dimensional heterojunction device structure and a preparation method thereof, the preparation method is simple and is completely compatible with the existing micro-electronic and photoelectron processes, the self-curling of the plane heterojunction is excited after the sacrificial layer at the bottom of the semiconductor/two-dimensional material plane heterojunction is removed, and the preparation of the micro-tube type three-dimensional heterojunction and the electric contact between the outer wall material of the micro-tube type three-dimensional heterojunction and the outer wall electrode can be simultaneously realized, so that the current can only pass through the micro-tube type three-dimensional heterojunction along the radial direction, and the current can not pass through the uncurled plane heterojunction.
In addition, the strain-driven self-curling technology is utilized to convert the planar two-dimensional heterojunction into the tubular three-dimensional heterojunction, the micro-tube three-dimensional heterojunction device is prepared, the advantages of the planar heterojunction device such as built-in electric field, rectification, high on-off ratio, low dark current and the like are completely inherited, the performance is improved, the heterojunction device is provided with a natural hollow pipeline, the occupied area of the heterojunction device in a plane is small, the ratio of the surface area to the volume of the heterojunction device is increased, and the light emitting direction or the light receiving direction of the heterojunction device is wide. In addition, compared with a planar two-dimensional heterojunction device, the two materials forming the heterojunction can be exposed as the inner wall and the outer wall of the tubular structure at the same time, and the self-curling behavior can be controlled to enable the materials of the inner wall and the outer wall to be flexibly exchanged, namely, a certain material forming the heterojunction can be used as the inner wall of the tubular structure and also can be used as the outer wall of the tubular structure, and the function of the heterojunction device can be provided in the tube and outside the tube. Therefore, after the planar two-dimensional heterojunction device is converted into the tubular three-dimensional heterojunction device, a plurality of performance advantages are additionally brought, and the planar two-dimensional heterojunction device can be widely applied to the field of devices such as self-driven (zero-bias) photoelectric detection, solar cell tubes and internal gas sensing, so that the device performance is greatly improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
Fig. 1 is a schematic diagram of a three-electrode microtube type three-dimensional heterojunction device structure according to an embodiment of the present invention;
fig. 2 is a schematic flow chart of a method for manufacturing a three-electrode microtube type three-dimensional heterojunction device structure according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a three-electrode micro-tube type three-dimensional heterojunction device structure for photoelectric detection according to an embodiment of the present invention;
fig. 4 is a schematic diagram of a three-electrode microtube type three-dimensional heterojunction device structure for photoelectric regulation and control according to an embodiment of the invention;
FIG. 5 is a schematic diagram of a two-electrode microtube type three-dimensional heterojunction device structure according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of a two-electrode microtube type three-dimensional heterojunction device structure for gas sensing according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a microtube type three-dimensional heterojunction device structure with an outer wall electrode wound on the outer wall of a tube according to an embodiment of the present invention;
fig. 8 is a schematic diagram of a micro-pipe type three-dimensional heterojunction device structure with holes on an outer wall of a pipe according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and the following embodiments are used for illustrating the present invention and are not intended to limit the scope of the present invention. The examples do not show the specific techniques or conditions, according to the technical or conditions described in the literature in the field, or according to the product specifications.
In the present invention, the instruments and the like used are conventional products which are purchased from regular vendors, not indicated by manufacturers. The process is conventional unless otherwise specified, and the starting materials are commercially available from the open literature. The examples do not show the specific techniques or conditions, according to the technical or conditions described in the literature in the field, or according to the product specifications. In the present invention, the two-dimensional and three-dimensional references mentioned in the plane two-dimensional heterojunction, tubular three-dimensional heterojunction, and the like refer to two-dimensional and three-dimensional in geometric structure, not two-dimensional and three-dimensional in electron band density.
Some preferred embodiments of the present invention provide a microtube-type three-dimensional heterojunction device structure, which is composed of a substrate, a buffer layer, a sacrificial layer, a semiconductor, a two-dimensional material, an insulating layer and an electrode. The semiconductor and the two-dimensional material are firstly formed into a semiconductor/two-dimensional material plane heterojunction on a substrate, the semiconductor/two-dimensional material plane heterojunction is preferably formed by stacking through Van der Waals force, and the semiconductor and the two-dimensional material are preferably stacked in the vertical direction in the sequence of the lower two-dimensional material and the upper two-dimensional material; the semiconductor/two-dimensional material plane heterojunction has strain, and a sacrificial layer is arranged at the bottom of the semiconductor/two-dimensional material plane heterojunction, and the strain of the plane heterojunction is preferably introduced by the semiconductor; after the sacrificial layer at the bottom of the planar heterojunction is removed, the planar heterojunction is separated from the substrate, stress is released, and the planar heterojunction is curled upwards or downwards to form a micron tube or a nanotube, preferably, the planar heterojunction is curled upwards to form the micron tube, namely, the planar heterojunction of the semiconductor/two-dimensional material is curled upwards to form a three-dimensional heterojunction of the micro-tube type semiconductor/two-dimensional material, wherein the number of curling turns of the three-dimensional heterojunction is more than or equal to 1 turn.
The substrate includes, but is not limited to, ceramic, glass, polymer, Si, Ge, diamond, SOI, GeOI, GaN, AlN, InN, ZnO, MgO, SiC, LiAlO2、LiGaO2、MgAl2O4、Al2O3、Ga2O3、GaAs、InP、GaP、InAs、GaSb、Si3N4、SiO2And various dummy substrates, preferably GaAs, InP, Si, Al2O3GaN, and the like can be used for a substrate for growing a single crystal semiconductor.
The semiconductor is one or more of group IV, group III-V, group II-VI, group IV-VI semiconductors, and the remaining other types of semiconductors, the semiconductor being a single layer or multiple layers, preferably a semiconductor strained single layer or a semiconductor strained double layer, wherein the semiconductor strained single layer is preferably a semiconductor compressively strained single layer, and for the semiconductor strained double layer is preferably composed of a pre-grown semiconductor compressively strained layer and a post-grown unstrained semiconductor top layer, the writing method of each group of semiconductor strained double layers being unified with the pre-grown semiconductor strained layer preceding the post-grown unstrained semiconductor top layer. Taking the InGaAs/GaAs strained double layer grown on the GaAs substrate as an example, the InGaAs is a semiconductor compressively strained layer grown first, and the GaAs is a non-strained semiconductor top layer grown later. Here, the compressive strain means that the lattice constant of the semiconductor is larger than that of the substrate, and the semiconductor itself is laterally contracted (distorted) in the horizontal direction in order to be horizontally aligned with the substrate, and can be regarded as being laterally compressed; unstrained means that the lattice constant of the semiconductor matches or substantially matches the lattice constant of the substrate, and the semiconductor itself is not distorted in the horizontal direction. The introduction of the compressive strain in the semiconductor includes, but is not limited to, means such as growth temperature regulation, growth rate regulation, composition regulation, substrate regulation and the like.
According to some preferred embodiments, the semiconductor constituting the heterojunction includes, but is not limited to, Si compressively strained monolayers, SnO2Compressive strain monolayer, GeO2Compressive strain monolayer, TiO2A compressive strain monolayer, a ZnO compressive strain monolayer, a ZnS compressive strain monolayer, a Si/Si strain bilayer, an InGaAs/GaAs strain bilayer, an InP/InGaAsP strain bilayer, an InGaAsP/InGaAsP strain bilayer, or an InGaN/GaN strain bilayer. In which the Si is a strained monolayer, SnO2Strained monolayer, GeO2Strained monolayer, TiO2Compressive strain monolayer, ZnO compressive strain monolayer, ZnS compressive strain monolayer, Si/Si strain bilayer, SiGe/Si strain double layer is grown on Si substrate, InGaAs/GaAs strain double layer is grown on GaAs substrate, InP/InGaAsP strain double layer, InGaAsP/InGaAsP strain double layer are grown on InP substrate, InGaN/GaN strain double layer is grown on Al2O3Or a GaN substrate.
The two-dimensional material is one or more of graphene, doped graphene, graphene derivatives, graphene alkyne, silicon alkene, germanium alkene, boron alkene, lead alkene, tin alkene, black phosphorus, hexagonal boron nitride, transition metal sulfides (TMDS), transition metal carbide, nitride or carbonitride (MXene), transition metal nitride, metal oxide, exol semimetal, layered hydroxide (LDH), two-dimensional superlattice, ternary and more than ternary multi-element two-dimensional materials; the two-dimensional material is a single-layer, double-layer, few-layer (3-10 layers) or multi-layer (more than 10 layers), and the single-layer, double-layer or few-layer two-dimensional material is preferred.
And preferably, removing the sacrificial layer at the bottom of the planar heterojunction by a lateral wet etching method, wherein the material of the sacrificial layer is selected to correspond to the semiconductor strain monolayer or the semiconductor strain bilayer and the two-dimensional material, so that when the lateral etching is carried out, the material of the sacrificial layer and the semiconductor strain monolayer or the semiconductor strain bilayer and the two-dimensional material have a sufficiently high etching selectivity ratio, namely, the lateral etching preferentially etches the sacrificial layer without basically etching the semiconductor strain monolayer or the semiconductor strain bilayer and the two-dimensional material. The sacrificial layer includes, but is not limited to, AlGaAs, AlAs, InGaP, AlInP, AlP, GaN, AlN, AlGaN, Ge, SiO2And photoresist (photoresist).
According to some preferred embodiments, the InGaAs/GaAs strained bilayer may be combined with graphene, Mxene, MoS2、WSe2The planar heterojunction is formed on a GaAs substrate by using semiconductor/two-dimensional materials such as InGaAs/GaAs/graphene, InGaAs/GaAs/reduced graphene oxide and the like, AlGaAs or AlAs with high aluminum components can be selected as a sacrificial layer at the bottom of the planar heterojunction, and the sacrificial layer can be selectively removed by using an HF acid solution; the Si strain single layer, the Si/Si strain double layer and the SiGe/Si strain double layer can be combined with graphene, Mxene and MoS2、WSe2Reduced graphene oxide, and the likeTwo-dimensional material, forming Si/graphene, Si/reduced graphene oxide and other semiconductor/two-dimensional material planar heterojunction on Si substrate, and selecting SiO2A sacrificial layer as the bottom of the planar heterojunction, which can be selectively removed by HF acid; SnO2Strained monolayer, GeO2Strained monolayer, TiO2The strained monolayer, the ZnO strained monolayer, the ZnS compressive strained monolayer may be combined with graphene, Mxene, MoS2、WSe2Reducing graphene oxide and other two-dimensional materials to form SnO on Si substrate2Graphene and GeO2Graphene and TiO2The planar heterojunction is made of semiconductors/two-dimensional materials such as graphene, ZnO/graphene, ZnS/graphene and the like, photoresist can be selected as a sacrificial layer at the bottom of the planar heterojunction, and the sacrificial layer can be selectively removed through an acetone solution.
According to some preferred embodiments, the finally formed microtubular semiconductor/two-dimensional material three-dimensional heterojunction, the semiconductor serves as an outer wall material and the two-dimensional material serves as an inner wall material. Further, if the planar heterojunction is a planar heterojunction formed by the semiconductor strain double layer and the two-dimensional material, the semiconductor strain layer serves as an outer wall material, and the two-dimensional material serves as an inner wall material; if the planar heterojunction is a planar heterojunction formed by the semiconductor compressive strain single layer and the two-dimensional material, the semiconductor compressive strain single layer serves as an outer wall material, and the two-dimensional material serves as an inner wall material.
In order to ensure that the microtubule type semiconductor/two-dimensional material three-dimensional heterojunction can realize normal device functions and be thoroughly distinguished from a semiconductor/two-dimensional material planar heterojunction device, current can only pass through the semiconductor/two-dimensional material three-dimensional heterojunction along the radial direction of the microtubule, but can not pass through the semiconductor/two-dimensional material planar heterojunction along the vertical direction. Therefore, the electrodes of the micro-tube three-dimensional heterojunction device at least comprise an inner wall electrode and an outer wall electrode, the inner wall electrode only forms electric contact with the inner wall material of the micro-tube two-dimensional material/semiconductor three-dimensional heterojunction, the outer wall electrode only forms electric contact with the outer wall material of the micro-tube two-dimensional material/semiconductor three-dimensional heterojunction, and the inner wall electrode and the outer wall electrode are insulated from the substrate. Therefore, the invention discloses a microtube type semiconductor/two-dimensional material three-dimensional heterojunction device, which at least comprises: the micro-tube type two-dimensional material/semiconductor three-dimensional heterojunction, an inner wall electrode and an outer wall electrode. The micro-tube type two-dimensional material/semiconductor three-dimensional heterojunction is a tubular three-dimensional heterojunction formed by self-coiling of a two-dimensional material/semiconductor planar heterojunction on a substrate.
However, the design concept and the electrode preparation process of the existing heterojunction device are only served for a planar heterojunction device (for the planar heterojunction device, the device electrode is completed by the steps of photoetching, metal deposition and the like after the planar heterojunction is realized, and the device electrode is directly pressed on the planar heterojunction), but the design concept and the electrode preparation process are obviously incompatible with the self-curling tube manufacturing process, and in other words, incompatible with the preparation process of the micro-tube type three-dimensional heterojunction. Specifically, as the microtube type semiconductor/two-dimensional material three-dimensional heterojunction is the same as the self-curling microtube and is provided with a natural hollow pipeline, if an outer wall electrode pressed on the outer wall of the three-dimensional heterojunction is directly prepared after the three-dimensional heterojunction is realized, thick photoresist spun in the electrode preparation process or deposited thick electrode metal is directly pressed on the outer wall of the microtube type three-dimensional heterojunction, which will inevitably cause the collapse or the breakage of the hollow microtube; the deposition of the thin-layer electrode metal is changed, so that the hollow micro-tube can be prevented from being crushed or collapsed, but the thin-layer electrode metal can be broken at the joint of the curved surface and the plane due to the influence of the curved surface outer wall of the micro-tube type three-dimensional heterojunction. The three-dimensional heterojunction device can be completely failed, so that the existing device design idea and electrode preparation process can not solve the problem of preparation of the electrode (especially the outer wall electrode) of the micro-tube type three-dimensional heterojunction device.
Example 1
The embodiment provides a schematic diagram of a three-electrode microtube type three-dimensional heterojunction device structure, as shown in fig. 1, the device comprises:
the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction field effect transistor comprises a substrate 101, a buffer layer 102, a sacrificial layer 103, a semiconductor 104, an insulating layer 105, a two-dimensional material 106, a first inner wall electrode 107, a second inner wall electrode 108, an outer wall electrode 109 and a micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction 110. Semiconductor 104 is situated on sacrificial layer 103, and semiconductor 104 has a strain, and may be embodied as a semiconductor strained monolayer or a semiconductor strained bilayer. The semiconductor 104 and the two-dimensional material 106 are firstly stacked on the sacrificial layer 103 by van der waals force to form a semiconductor/two-dimensional material planar heterojunction, and further, the sacrificial layer 103 at the bottom is selectively etched off, so that the planar heterojunction is self-curled upwards to form a micropipe type semiconductor/two-dimensional material three-dimensional heterojunction 110, wherein the semiconductor is the outer wall of the three-dimensional heterojunction 110, and the two-dimensional material is the inner wall of the three-dimensional heterojunction 110. Furthermore, before the curling, the U-shaped patterning treatment is carried out on the semiconductor/two-dimensional material planar heterojunction, the three-dimensional heterojunction 110 formed after the mesa of the U-shaped planar heterojunction is curled by self has two arms, the number of self-curling turns (namely, the self-curling length) of the two arms is more than that of the self-curling turns of the part between the two arms (namely, the self-curling length is longer), so that the three-dimensional heterojunction 110 between the two arms is suspended above the substrate 101, and a new approach is provided for preparing an outer wall electrode of the micro-tube type three-dimensional heterojunction device.
The device shown in fig. 1 is configured with three electrodes, namely a first inner wall electrode 107, a second inner wall electrode 108 and a second outer wall electrode 109, wherein the three electrodes are all positioned outside the microtubular semiconductor/two-dimensional material three-dimensional heterojunction 110 (i.e. none of the three electrodes are inside the microtubular semiconductor/two-dimensional material three-dimensional heterojunction, i.e. all of the three electrodes are planar electrodes and do not curl), all of the three electrodes are deposited on the insulating layer 105, so that the three electrodes are insulated from each other, and all of the electrodes are electrically isolated from the substrate 101 by the insulating layer. All electrodes were prepared before the planar heterojunction was self-curled. When the semiconductor/two-dimensional material planar heterojunction is subjected to U-shaped patterning, the two-dimensional material 106 extends from above the planar heterojunction to above the insulating layer 105, and the inner wall electrode presses the two-dimensional material 106 on the insulating layer 105, that is, the inner wall electrode makes electrical contact with the two-dimensional material 106. The outer wall electrode 109 is located between the inner wall electrodes and does not make any contact with the U-shaped planar heterojunction mesa (including the semiconductor) before the planar heterojunction is crimped; after the curling is started, the table top of the U-shaped plane heterojunction curls towards the direction of the outer wall electrode, the curled suspended three-dimensional heterojunction gradually advances and climbs to the top of the outer wall electrode 109 under the driving of the curling of the two arms, so that the compression contact between the outer wall semiconductor of the micro-tube type three-dimensional heterojunction 110 and the outer wall electrode 109 is realized, the compression contact between the outer wall semiconductor of the micro-tube type three-dimensional heterojunction 110 and the outer wall electrode is formed at the moment, the inherent mode of the attachment contact between the outer wall electrode and the outer wall semiconductor of the micro-tube type three-dimensional heterojunction 110 is broken, the micro-tube type three-dimensional heterojunction 110 cannot be collapsed or broken by the outer wall electrode while the good electric contact between the outer wall electrode and the outer wall semiconductor of the micro-tube type three-dimensional heterojunction 110 is guaranteed, and a feasible solution is provided for.
The inner wall electrode and the outer wall electrode comprise one or more of Au, Pt, Ti, Cr, Ni, Ge, Pd, Cu, Ag, Fe, Co and the like, and/or Indium Tin Oxide (ITO), and/or low-melting-point alloy consisting of low-melting-point metal elements such as Ga, In, Sn, Pb, Bi and the like; after the outer wall electrode is contacted with the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction outer wall semiconductor, the contact resistance can be further reduced by the methods of dropping conductive adhesive on the outer wall electrode, heat treatment, ultrasonic welding, chemical treatment and the like. For example, after the outer wall electrode is contacted with the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction outer wall semiconductor, a small amount of conductive adhesive is dripped on the top of the three-dimensional heterojunction outer wall contacted with the outer wall electrode, and the conductive adhesive automatically flows down along the outer wall under the action of self gravity to reach the contact part and fill and surround the contact part. And moreover, the low melting point cooperation is adopted as an outer wall electrode material, after the outer wall electrode is contacted with the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction outer wall semiconductor, heat treatment is carried out on the contact part, so that the electrode material is softened or even partially melted, the outer wall can automatically sink into the electrode material due to the compression type contact between the outer wall semiconductor and the outer wall electrode, after the electrode material is cooled and solidified again, the large-area surrounding of the electrode material on the contact part is realized, and the electric contact quality is further improved.
Example 2
The embodiment provides a method for preparing a three-electrode microtube type semiconductor/two-dimensional material three-dimensional heterojunction device structure, as shown in fig. 2, comprising the following steps:
(a) the method comprises the following steps A buffer layer 102, a sacrificial layer 103 and a semiconductor 104 are sequentially deposited on a substrate 101, so that a complete epitaxial structure is obtained. Wherein, optionally, the semiconductor 104 is a semiconductor strained bilayer consisting of a semiconductor compressively strained layer and an unstrained semiconductor top layer;
(b) the method comprises the following steps Photoetching and etching the epitaxial structure to form a U-shaped table top, and simultaneously exposing the sacrificial layer 103;
(c) the method comprises the following steps Depositing an insulating layer 105, and photoetching and etching a pattern on the insulating layer 105 to enable the insulating layer 105 to cover the rear end regions of the U-shaped arms on the two sides of the U-shaped table top and the region between the two U-shaped arms;
(d) the method comprises the following steps Transferring the two-dimensional material 106 onto a U-shaped table board, carrying out U-shaped patterning treatment on the two-dimensional material 106 to form a semiconductor/two-dimensional material planar heterojunction, and enabling the two-dimensional material 106 to extend onto the insulating layer 105 along the U-shaped arm;
(e) the method comprises the following steps Depositing an inner wall electrode 107, an inner wall electrode 108 and an outer wall electrode 109 on the insulating layer 105, so that the inner wall electrode 107 and the inner wall electrode 108 press the two-dimensional material 106, the outer wall electrode 109 is positioned on the insulating layer 105 between the two U-shaped arms, and the outer wall electrode 109 is not in contact with the two-dimensional material 106 and the U-shaped table;
(f) the method comprises the following steps Covering the inner wall electrode 107, the inner wall electrode 108, the outer wall electrode 109, the insulating layer 105 and part of the U-shaped mesa with photoresist in a rectangular pattern;
(g) the method comprises the following steps Adopting a wet method to laterally etch the sacrificial layer 103, so that the semiconductor/two-dimensional material planar heterojunction uncovered by the photoresist is separated from the substrate 101 to release stress and generate directional curling, thereby forming a microtube type semiconductor/two-dimensional material three-dimensional heterojunction 110, and meanwhile, the U-shaped mesa part pressed by the photoresist is not self-curled due to the pressing of the photoresist;
(f) the method comprises the following steps And removing the photoresist to expose the inner wall electrode 107, the inner wall electrode 108 and the outer wall electrode 109, continuously curling the U-shaped table surface part pressed by the photoresist, continuously curling the two U-shaped arms to form a complete suspended microtube type semiconductor/two-dimensional material three-dimensional heterojunction 110, climbing the top area of the outer wall electrode 109, realizing the electric contact between the microtube type semiconductor/two-dimensional material three-dimensional heterojunction outer wall semiconductor 104 and the outer wall electrode 109, and finally preparing the microtube type three-dimensional heterojunction device structure.
Example 3
As shown in fig. 3, the three-electrode microtube-type three-dimensional heterojunction device described in fig. 1 in example 1 of the present invention can operate with two electrodes (an outer wall electrode and either one of the inner wall electrodes). And welding an electrode lead for the device, optionally packaging the device, and connecting an outer wall electrode and any one inner wall electrode into a source meter, wherein the three-electrode micro-tube type three-dimensional heterojunction device is a heterojunction type photoelectric detector. The current is provided by a source meter (the source meter is also replaced by other current sources or voltage sources), the current finally returns to the source meter through the source meter, the inner wall electrode, the two-dimensional material, the semiconductor and the outer wall electrode to form a heterojunction loop, and the current can only pass through the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction along the radial direction; when the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction has photovoltaic effect, a closed current loop is only provided without a source meter (or an external current source or a voltage source), the device can also work normally, incident light irradiated to the outer wall of the micro-tube type three-dimensional heterojunction from multiple directions is absorbed by the semiconductor and then generates photo-generated electron-hole pairs in the semiconductor, the photo-generated electron-hole pairs are separated by a built-in electric field of the three-dimensional heterojunction, and the holes and the electrons are respectively collected by a positive electrode and a negative electrode and finally are compounded outside the device to form photocurrent. The photocurrent response (namely, the magnitude and the change of the photocurrent under external illumination) can be monitored in real time through the source meter, so that the function of the three-dimensional photoelectric detector is realized.
Example 4
As shown in fig. 4, the three-electrode microtube-type three-dimensional heterojunction device described in fig. 1 of example 1 can also work with three electrodes (one outer wall electrode and two inner wall electrodes). It should be noted that before all the three electrodes are selected to work, optionally, an insulating layer is deposited on the outer wall electrode when the microtube type three-dimensional heterojunction device is prepared, that is, the outer wall of the microtube type three-dimensional heterojunction device is pressed on the insulating layer on the outer wall electrode. The device is used for welding an electrode lead, optionally packaging the device, an outer wall electrode and two inner wall electrodes are connected to a source meter, a current loop is composed of the inner wall electrode, a two-dimensional material, a semiconductor and the other inner wall electrode, the photoelectric detection function can be realized, at the moment, the device works in a photoconductive mode, a built-in electric field formed by the semiconductor/two-dimensional material heterojunction enhances the photoconductive effect, and meanwhile, the outer wall electrode is used for regulating and controlling grid voltage of the micro-tube type three-dimensional heterojunction, so that the photoconductive effect can be further enhanced, and the photoelectric detection performance is improved.
Example 5
The embodiment provides a schematic structural diagram of a two-electrode microtube type three-dimensional heterojunction device, as shown in fig. 5, the device includes: the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction comprises a substrate 201, a buffer layer 202, a sacrificial layer 203, a semiconductor 204, an insulating layer 205, a two-dimensional material 206, an inner wall electrode 207, an outer wall electrode 208 and a micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction 209. Therefore, the device is only provided with one outer wall electrode and one inner wall electrode, compared with the three-electrode microtube type three-dimensional heterojunction device provided in the figure 1, only one inner wall electrode is arranged, and the structures of the other devices are completely the same as the corresponding preparation processes.
Example 6
The double-electrode microtube type three-dimensional heterojunction device provided by the embodiment of the invention can be used for photoelectric detection and gas sensing. As shown in fig. 6, one inner wall electrode and one outer wall electrode are both connected to a source meter (preferably a constant current meter), the current loop is also a source meter-inner wall electrode-two-dimensional material-semiconductor-outer wall electrode-source meter, and the current can only pass through the microtube type semiconductor/two-dimensional material three-dimensional heterojunction in the radial direction. After the gas to be detected is filled into the hollow cavity of the micro-tube type three-dimensional heterojunction device, the resistivity of the gas to be detected is changed due to the fact that the inner wall material (namely, the two-dimensional material) adsorbs the gas molecules to be detected, the resistivity change can be determined by monitoring the voltage change, and the resistivity change is related to the gas concentration in the hollow cavity, so that the gas sensing function is achieved.
Example 7
The embodiment provides a schematic diagram of a three-electrode microtube type three-dimensional heterojunction device structure, as shown in fig. 7. The only difference between the microtubular three-dimensional heterojunction device structure shown in fig. 7 and the device structure shown in fig. 1 is that: the contact mode of the outer wall electrode and the outer wall of the microtube type three-dimensional heterojunction is different, and the contact mode adopted in figure 7 is that the outer wall electrode is wound on the outer wall of the microtube type three-dimensional heterojunction.
The device structure shown in fig. 7 can be prepared by the following method, including the steps:
s 01: and sequentially depositing a buffer layer, a sacrificial layer and a semiconductor on the substrate to obtain a complete epitaxial structure. Wherein optionally the semiconductor is a semiconductor strained bilayer consisting of a semiconductor compressively strained layer and an unstrained semiconductor top layer;
s 02: photoetching and etching the epitaxial structure to form a U-shaped table top with two U-shaped arms, wherein after etching is finished, a part of semiconductor compressive strain layer is reserved below the U-shaped table top, so that the sacrificial layer is not exposed;
s 03: depositing an insulating layer, and photoetching and etching a pattern on the insulating layer to enable the insulating layer to cover the rear end regions of the U-shaped arms on the two sides of the U-shaped table top and the region between the two U-shaped arms;
s 04: transferring the two-dimensional material to a U-shaped table board, carrying out U-shaped patterning treatment on the two-dimensional material to form a semiconductor/two-dimensional material planar heterojunction, and enabling the two-dimensional material to extend onto the insulating layer along the U-shaped arm;
s 05: depositing two inner wall electrodes and an outer wall electrode on the insulating layer, enabling the inner wall electrode to press the two-dimensional material, enabling the outer wall electrode to be located on the insulating layer between the two U-shaped arms, and enabling the outer wall electrode not to be in contact with the two-dimensional material and the U-shaped table top;
s 06: etching the semiconductor compressive strain layer remained in the step s02 on the other side of the U-shaped table top opposite to the inner wall electrode and the outer wall electrode to form an etching window, and completely exposing the sacrificial layer in the etching window;
s 07: covering the inner wall electrode, the outer wall electrode, the insulating layer and part of the U-shaped table top by photoresist with rectangular patterns;
s 08: the sacrificial layer is laterally corroded by a wet method through a corrosion window, so that the semiconductor/two-dimensional material planar heterojunction uncovered by the photoresist is separated from the substrate to release stress and generate directional curling, the constraint of the residual semiconductor compressive strain layer is torn, a microtube type semiconductor/two-dimensional material three-dimensional heterojunction is formed, and meanwhile, the U-shaped table surface part covered by the photoresist is not self-curled due to the pressing of the photoresist;
s 09: and removing the photoresist, exposing the inner wall electrode and the outer wall electrode, continuously curling the U-shaped table surface part pressed by the photoresist, continuously curling the two U-shaped arms to form a complete suspended microtube type semiconductor/two-dimensional material three-dimensional heterojunction, climbing to the top of the outer wall electrode, rolling and advancing at the top of the outer wall electrode, rolling and winding the outer wall electrode on the outer wall of the three-dimensional heterojunction, and electrically contacting the outer wall of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction with the outer wall electrode to finally prepare the three-electrode microtube type three-dimensional heterojunction device structure.
Example 8
The embodiment provides a micro-tube type three-dimensional heterojunction device structure with holes on the outer wall of a tube, and the schematic diagram of the device structure is shown in fig. 8. The only difference between the microtubular three-dimensional heterojunction device structure shown in fig. 8 and the device structure shown in fig. 1 is that: the outer wall of the microtube type three-dimensional heterojunction device shown in fig. 8 is provided with a hole, the semiconductors at the hole are completely removed, the two-dimensional material is directly exposed in the hole, the bottom of the two-dimensional material in the hole is a circle of rolled semiconductors, the two-dimensional material is tightly attached to the semiconductors, and a two-dimensional material/semiconductor heterojunction is formed through van der waals force.
The invention also provides a preparation method of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction device structure with the holes on the outer wall of the tube, which is characterized in that on the basis of the device preparation step disclosed in the figure 2, a hole digging operation of the U-shaped table is additionally added after the preparation of the U-shaped table is finished, the hole digging operation of the table can be finished through dry etching and/or wet etching, the shapes of the holes dug on the U-shaped table include but are not limited to round, oval, square, rectangle and the like, the number of the holes is not required, the depth of the holes ensures that the bottom sacrificial layer is exposed from the holes (namely, the semiconductor is completely etched in the holes, the sacrificial layer can be directly seen), and thus when the two-dimensional material is transferred to the U-shaped table, the two-dimensional material covered on the holes is in a suspended state. On the premise of accurately controlling the covering position of the two-dimensional material on the U-shaped table board, when the semiconductor/two-dimensional material planar heterojunction falls off the bottom sacrificial layer through lateral erosion and is curled upwards, the lateral erosion distance is controlled to enable the hole to be just appeared on the outermost wall of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction, and meanwhile, the two-dimensional material suspended in the hole can be tightly attached to a circle of semiconductor (without the two-dimensional material) which is curled up before. Thus, when viewed from the outside of the microtube to the inside of the microtube, the two-dimensional material/semiconductor three-dimensional heterojunction is formed in the hole, the semiconductor/two-dimensional material three-dimensional heterojunction is formed in the area outside the hole, and the positions of the two-dimensional material and the semiconductor which form the heterojunction are exchanged. More generally, the three-dimensional heterojunction at the hole is exposed to the outside by the two-dimensional material, and the three-dimensional heterojunction outside the hole is exposed to the outside by the semiconductor.
Example 9
All the microtube type semiconductor/two-dimensional material three-dimensional heterojunction device structures provided by the embodiments 1 to 8 of the present invention can further improve the device performance by adopting the following means, wherein the adopted means includes that a surface nanoparticle layer or a surface passivation layer can be introduced into the surface of the two-dimensional material; and/or, a semiconductor quantum well or a semiconductor quantum dot gain medium can be introduced into the semiconductor; and/or an interfacial oxide layer, an interfacial nitride layer, or the like may be introduced at the interface of the two-dimensional material and the semiconductor.
Although the invention has been described in detail hereinabove with respect to a general description and specific embodiments thereof, it will be apparent to those skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.

Claims (10)

1. A microtube three-dimensional heterojunction device structure, comprising:
the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction, an inner wall electrode, an outer wall electrode and a substrate; wherein the inner wall electrode only forms an electric contact with the inner wall material of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction; the outer wall electrode only forms electrical contact with the outer wall material of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction; the inner wall electrode and the outer wall electrode are insulated from the substrate;
the microtube type semiconductor/two-dimensional material three-dimensional heterojunction is a tubular three-dimensional heterojunction formed by self-coiling of a semiconductor/two-dimensional material planar heterojunction on the substrate.
2. The microtube three-dimensional heterojunction device structure of claim 1, wherein the semiconductor/two-dimensional material planar heterojunction is a planar heterojunction formed by stacking a two-dimensional material and a semiconductor up and down by van der waals force.
3. The microtube three-dimensional heterojunction device structure of claim 2, wherein the semiconductor/two-dimensional material planar heterojunction has a strain; the bottom of the semiconductor/two-dimensional material plane heterojunction is provided with a sacrificial layer; and after the sacrificial layer is removed, the semiconductor/two-dimensional material planar heterojunction is separated from the substrate, stress is released, and the semiconductor/two-dimensional material planar heterojunction is self-curled into a micro tube or a nano tube to form the semiconductor/two-dimensional material micro tube type three-dimensional heterojunction, wherein the number of self-curling turns is more than or equal to 1 turn.
4. The microtube three-dimensional heterojunction device structure of claim 3, wherein the inner wall electrode and the outer wall electrode are flat plate electrodes of a coplanar structure; and/or
The inner wall electrode and the outer wall electrode are positioned on the same side of the semiconductor/two-dimensional material plane heterojunction, and part of the inner wall electrode is pressed on the semiconductor/two-dimensional material plane heterojunction; a space is reserved between the outer wall electrode and the semiconductor/two-dimensional material plane heterojunction; and/or
The curling direction of the semiconductor/two-dimensional material plane heterojunction faces to the inner wall electrode and the outer wall electrode; and/or
The semiconductor/two-dimensional material plane heterojunction is self-curled into a micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction, the distance between the three-dimensional heterojunction and the outer wall electrode is gradually reduced, the curling action is continued until the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction advances to the outer wall electrode area, and the outer wall electrode and the outer wall material of the micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction form electric contact.
5. The microtubular three-dimensional heterojunction device structure of claims 1-4 wherein said semiconductor is selected from one or more of group IV, III-V, II-VI, IV-VI semiconductors and the remaining other types of semiconductors; and/or
The two-dimensional material is selected from one or more of graphene, doped graphene, graphene derivatives, graphene alkyne, silicon alkene, germanium alkene, boron alkene, lead alkene, tin alkene, black phosphorus, hexagonal boron nitride, transition metal sulfide TMDS, transition metal carbide, nitride or carbon nitride MXene, transition metal nitride, metal oxide, exol semimetal, layered hydroxide LDH, two-dimensional superlattice, ternary and more than ternary multi-element two-dimensional materials; and/or
The inner wall electrode and the outer wall electrode are made of one or more of Au, Pt, Ti, Cr, Ni, Ge, Pd, Cu, Ag, Fe, Co and the like, and/or Indium Tin Oxide (ITO), and/or low-melting-point alloy consisting of low-melting-point metal elements such as Ga, In, Sn, Pb, Bi and the like.
6. A method for preparing a micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction device structure is characterized by comprising the following steps:
s01: depositing a buffer layer on a substrate;
s02: depositing a sacrificial layer on the buffer layer;
s03: depositing a semiconductor compressive strain layer and a semiconductor top layer on the sacrificial layer, thereby forming a semiconductor strain double layer and obtaining a complete epitaxial structure;
s04: photoetching and etching the epitaxial structure to form a U-shaped table top with two U-shaped arms, and exposing the sacrificial layer;
s05: depositing an insulating layer, and photoetching and etching a pattern on the insulating layer to enable the insulating layer to cover the rear end regions of the U-shaped arms on the two sides of the U-shaped table top and the region between the two U-shaped arms;
s06: transferring the two-dimensional material to a U-shaped table board, carrying out U-shaped patterning treatment on the two-dimensional material to form a semiconductor/two-dimensional material planar heterojunction, and extending the two-dimensional material to the insulating layer along a U-shaped arm;
s07: depositing an inner wall electrode and an outer wall electrode on the insulating layer, enabling the inner wall electrode to press the two-dimensional material, enabling the outer wall electrode to be located on the insulating layer between the two U-shaped arms, and enabling the outer wall electrode not to be in contact with the two-dimensional material and the U-shaped table top;
s08: covering the inner wall electrode, the outer wall electrode, the insulating layer and part of the U-shaped table top by photoresist with rectangular patterns;
s09: adopting a wet method to laterally corrode the sacrificial layer to enable the semiconductor/two-dimensional material planar heterojunction which is not covered by the photoresist to be separated from the substrate, releasing stress and generating directional curling to form a microtube type semiconductor/two-dimensional material three-dimensional heterojunction;
s10: and removing the photoresist to expose the inner wall electrode and the outer wall electrode, continuously curling the U-shaped table surface part pressed by the photoresist, continuously curling the two U-shaped arms to form a suspended microtubule type semiconductor/two-dimensional material three-dimensional heterojunction, and climbing to the top area of the outer wall electrode to form electric contact between the outer wall of the microtubule type semiconductor/two-dimensional material three-dimensional heterojunction and the outer wall electrode.
7. A method for preparing a micro-tube type semiconductor/two-dimensional material three-dimensional heterojunction device structure is characterized by comprising the following steps:
s 01: depositing a buffer layer on a substrate;
s 02: depositing a sacrificial layer on the buffer layer;
s 03: depositing a semiconductor compressive strain layer and a semiconductor top layer on the sacrificial layer, thereby forming a semiconductor strain double layer and obtaining a complete epitaxial structure;
s 04: photoetching and etching the epitaxial structure to form a U-shaped table top with two U-shaped arms, so that a part of semiconductor compressive strain layer is left below the U-shaped table top, and the sacrificial layer is not exposed;
s 05: depositing an insulating layer, and photoetching and etching a pattern on the insulating layer to enable the insulating layer to cover the rear end regions of the U-shaped arms on the two sides of the U-shaped table top and the region between the two U-shaped arms;
s 06: transferring the two-dimensional material to a U-shaped table board, carrying out U-shaped patterning treatment on the two-dimensional material to form a semiconductor/two-dimensional material plane heterojunction, and enabling the two-dimensional material to extend onto an insulating layer along a U-shaped arm;
s 07: depositing an inner wall electrode and an outer wall electrode on the insulating layer, enabling the inner wall electrode to press the two-dimensional material, enabling the outer wall electrode to be located on the insulating layer between the two U-shaped arms, and enabling the outer wall electrode not to be in contact with the two-dimensional material and the U-shaped table top;
s 08: etching the semiconductor compressive strain layer remained in the step s04 on the other side of the U-shaped table top opposite to the inner wall electrode and the outer wall electrode to form an etching window, and exposing the sacrificial layer in the etching window;
s 09: covering the inner wall electrode, the outer wall electrode, the insulating layer and part of the U-shaped table top by photoresist with rectangular patterns;
s 10: laterally corroding the sacrificial layer through a corrosion window by a wet method, so that the semiconductor/two-dimensional material planar heterojunction which is not covered by the photoresist is separated from the substrate to release stress to generate directional curling, and tearing the constraint of the residual semiconductor compressive strain layer to form a microtube type semiconductor/two-dimensional material three-dimensional heterojunction;
s 11: and removing the photoresist, exposing the inner wall electrode and the outer wall electrode, continuously curling the U-shaped table-board part pressed by the photoresist, continuously curling the two U-shaped arms to form a complete suspended microtube type three-dimensional heterojunction of the semiconductor/two-dimensional material, climbing to the top of the outer wall electrode, and rolling on the top of the outer wall electrode, so that the outer wall electrode is rolled up and wound on the outer wall of the three-dimensional heterojunction, and the outer wall of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction is in electrical contact with the outer wall electrode.
8. The method for preparing the microtube type semiconductor/two-dimensional material three-dimensional heterojunction device structure according to claim 6 or 7, wherein after the outer wall electrode is electrically contacted with the outer wall material of the microtube type semiconductor/two-dimensional material three-dimensional heterojunction, the outer wall electrode is subjected to treatment for reducing contact resistance, wherein the treatment comprises one or more of dropping conductive adhesive, heat treatment, ultrasonic welding and chemical treatment.
9. The method for preparing the microtube-type semiconductor/two-dimensional material three-dimensional heterojunction device structure of claim 6 or 7, wherein the steps S04 and S04 further comprise: carrying out hole digging operation on the U-shaped table top to expose the sacrificial layer from the hole; and/or, the two-dimensional material surface incorporates a surface nanoparticle layer or a surface passivation layer; and/or, a semiconductor quantum well or a semiconductor quantum dot gain medium is introduced into the semiconductor; and/or, the interface of the two-dimensional material and the semiconductor is introduced into an interface oxide layer or an interface nitride layer.
10. Use of the microtube three-dimensional heterojunction device structure according to any one of claims 1 to 5 or the microtube three-dimensional heterojunction device structure prepared by the method according to any one of claims 6 to 9 in applications including photodetection, photovoltaics, gas sensing, and electronic components.
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