CN107093599A - The encapsulating structure of multi-chip - Google Patents
The encapsulating structure of multi-chip Download PDFInfo
- Publication number
- CN107093599A CN107093599A CN201710398633.6A CN201710398633A CN107093599A CN 107093599 A CN107093599 A CN 107093599A CN 201710398633 A CN201710398633 A CN 201710398633A CN 107093599 A CN107093599 A CN 107093599A
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- Prior art keywords
- chip
- substrate
- window
- encapsulating structure
- gap
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- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention discloses a kind of encapsulating structure of multi-chip, including：Multiple chips；Substrate, window has been cut through for being provided for multiple chips on placement position, substrate；Multiple chip-stacked both sides in window；The weld pad of each chip is located in the drop shadow spread of window.By the invention it is possible to increase packaging density when carrying out three-dimensional stacked to each chip, improve chip-stacked stability.
Description
Technical field
The present invention relates to semiconductor applications, and in particular to a kind of encapsulating structure of multi-chip.
Background technology
Global terminal electronic product towards under compact, multi-functional, low-power consumption development trend, can constantly be integrated above-mentioned
System in package (System in Package, SiP) technology of characteristic is gradually taken seriously.SiP has become important advanced
Encapsulation and system integration technology, are the important technology routes of miniaturization of electronic products and multifunction, in microelectronics and electronics system
The field of making has wide application market and development prospect.
The three-dimensional stacked major part of traditional chip is that chip is stacked in substrate front side, completes corresponding bonding wire plastic packaging work
Skill, the weld pad (bonding wire pad) of chip is unilateral or polygon, it is however generally that, heap is not done in the weld pad region on chip
It is folded, to be damaged when avoiding and stacking to bonding wire or short circuit.In the prior art, to it is chip-stacked when, to avoid pad zone
Domain is stacked, and the chip area for being usually located at upper strata is less than lower layer chip area, and this can cause, when multilayer chiop is stacked, to be located at
There is the situation of I/O interface lazy weight because area is too small in the chip on upper strata, also, because each layer die size differs so that
In stacking process, unbalance stress between each layer chip is easily caused, causes the chip stacked unstable；In the prior art, it is
Ensure the area of each chip, also each chip is tiled, however, which increase the area of plane of substrate.In addition,
To each chip carry out it is three-dimensional stacked when can also produce bonding wire it is long, it is disorderly the problem of.
Therefore, packaging density how is increased, improving chip-stacked stability becomes urgent problem to be solved.
The content of the invention
Therefore, the technical problem to be solved in the present invention is how to increase packaging density, improves chip-stacked stability
Energy.
Therefore, according in a first aspect, the embodiments of the invention provide a kind of encapsulating structure of multi-chip, including：Multiple cores
Piece；Substrate, window has been cut through for being provided for multiple chips on placement position, substrate；Multiple chip-stacked both sides in window；Respectively
The weld pad of individual chip is located in the drop shadow spread of window.
Alternatively, multiple chips are located at the same side of substrate.
Alternatively, the number of multiple chips is even number, and multiple chips are symmetrically distributed in the both sides of window.
Alternatively, the number of multiple chips is 2N+1, wherein, N is positive integer, and the 1st in multiple chips is to 2N
Chip is symmetrically distributed in the both sides of window and forms the gap for being less than the window；The 2N+1 chip covers gap.
Alternatively, many root bead lines, each bonding wire is connected to each chip from substrate through window and each same layer chip gap
Weld pad, each chip is connected with substrate signal respectively.
Alternatively, plastic packaging material, coats multiple chips and many root bead lines.
Technical solution of the present invention, has the following advantages that：
The encapsulating structure for the multi-chip that the present invention is provided, due to having cut through window on substrate, the weld pad of each chip is located at
In the drop shadow spread of window so that the weld pad of each chip can carry out signal by the window and substrate and be connected；Due to multiple
The chip-stacked both sides in window, relative in the prior art, list piles up the structure of stacked chips, side provided in an embodiment of the present invention
Case adds chip package density, also, due to each chip-stacked both sides in window, uniform force when improving chip package
Property, then improve chip-stacked stability.
As optional technical scheme, during due to each chip being connected with substrate signal with many root bead lines respectively, each
Bonding wire is connected to the weld pad of each chip from substrate through window and each same layer chip gap, will be multiple using plastic packaging material during encapsulation
Chip and many root bead lines are enveloped so that when carrying out three-dimensional stacked to each chip bonding wire be difficult to be weighed wounded, short circuit.
Brief description of the drawings
, below will be to specific in order to illustrate more clearly of the specific embodiment of the invention or technical scheme of the prior art
The accompanying drawing used required in embodiment or description of the prior art is briefly described, it should be apparent that, in describing below
Accompanying drawing is some embodiments of the present invention, for those of ordinary skill in the art, before creative work is not paid
Put, other accompanying drawings can also be obtained according to these accompanying drawings.
Fig. 1 is a kind of encapsulating structure schematic diagram of multi-chip in the embodiment of the present invention；
Fig. 2 is the encapsulating structure schematic diagram of another multi-chip in the embodiment of the present invention.
Embodiment
Technical scheme is clearly and completely described below in conjunction with accompanying drawing, it is clear that described implementation
Example is a part of embodiment of the invention, rather than whole embodiments.Based on the embodiment in the present invention, ordinary skill
The every other embodiment that personnel are obtained under the premise of creative work is not made, belongs to the scope of protection of the invention.
In the description of the invention, it is necessary to explanation, term " " center ", " on ", " under ", "left", "right", " vertical ",
The orientation or position relationship of the instruction such as " level ", " interior ", " outer " be based on orientation shown in the drawings or position relationship, merely to
Be easy to the description present invention and simplify description, rather than indicate or imply signified device or element must have specific orientation,
With specific azimuth configuration and operation, therefore it is not considered as limiting the invention.In addition, term " first ", " second ",
" the 3rd " is only used for describing purpose, and it is not intended that indicating or implying relative importance.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected to by intermediary, can be with
It is the connection of two element internals, can is wireless connection or wired connection.For one of ordinary skill in the art
For, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
As long as in addition, technical characteristic involved in invention described below different embodiments non-structure each other
It can just be combined with each other into conflict.
In order to increase chip package density, improve chip-stacked stability, the present embodiment provides a kind of multi-chip
Encapsulating structure, refer to Fig. 1 and Fig. 2, for the encapsulating structure schematic diagram of the multi-chip, in the present embodiment, the encapsulation of the multi-chip
Structure includes：Multiple chips 102 and substrate 101, wherein：
Multiple chips 102 are used to realize various electrical functions, it is however generally that, it is disposed with respective electricity on each chip 102
Line structure.
Substrate 101 is used to provide to place for multiple chips 102 to have cut through window 106 on position, substrate 101；Multiple chips 102
It is stacked in the both sides of window 106；The weld pad 103 of each chip 102 is located in the drop shadow spread of window 106.In specific implementation,
Multiple chips 102 are stacked in the same side of substrate 101, specifically, can be symmetrically distributed in the both sides of window 106, each chip
102 weld pad 103 is respectively facing window 106, also, each weld pad 103 should avoid being blocked by other chips, so that, it is
Bonding wire is drawn from weld pad 103 to substrate 101 and provides passage.It refer to Fig. 2 in one embodiment, the number of multiple chips 102
Mesh can be even number, and the multiple chips 102 of the even number are symmetrically distributed in the both sides of window, during stacking, can be by position
Fitted in the side of a pair of chips 102 of the superiors, so that, cover the gap formed between each layer chip.Fig. 2 be refer to another
Plant in embodiment, the number of multiple chips 102 can also be odd number, i.e., the number of multiple chips is 2N+1, wherein, N is
The 1st in positive integer, multiple chips is symmetrically distributed in the both sides of window to 2N chip and forms gap less than window, the
2N+1 chip covers gap.
In specific implementation process, one layer of chip 102 first can be attached in the both sides of window 106 of substrate 101, then successively
The chip 102 of other layers of stacking., can be to the core on substrate 101 during chip 102 specifically is attached into substrate 101
Piece places position using glue or typography is drawn, and glue is drawn in substrate paster face.In the present embodiment, chip is placed and attached on position
The glue of chip can be such as B stage glue, and the chip on to substrate 101 is placed and drawn on position after glue, can be passed through
Precuring, it is in semi-cured state to make glue, then attaches chip on the substrate 101.In the process of specific stacked chips 102
In, to the upper surface of chip 102 of current layer can draw the processing of glue and precuring, then by positioned at the upper of current layer chip
One layer of chip 102 is attached on the chip of current layer.In an alternate embodiment of the invention, chip bonding mould (Die can also be passed through
Attach film, DAF) 105 come to being fixed between substrate and chip, the chip of different layers.It should be noted that working as core
When piece 102 carries paste functionality, for example chip 102 is attached with printing glue (such as resitol), then to substrate with
When being fixed between chip 102, the chip 102 of different layers, its own can be directly used without external attaching glue
Stacking is fixed in the printing glue of attachment, simplifies packaging technology.
In an alternate embodiment of the invention, the number of plies that multiple chips 102 are stacked is at least two layers, the shape between the chip of same layer
Into same layer chip gap；It is more than the same layer of the chip layer away from substrate 101 close to the same layer chip gap of the chip layer of substrate 101
Chip gap, so that the chip pad of the chip layer away from substrate 101 is located at the same layer chip chamber of the chip layer close to substrate 101
In the drop shadow spread of gap.Thus, it is possible to avoid the chip layer for being located at close substrate 101 from sheltering from the core for being located remotely from substrate 101
The chip pad 103 of lamella so that the passage that bonding wire is drawn from weld pad 103 to substrate 101 is more smoothly.
In an alternate embodiment of the invention, the encapsulating structure of the multi-chip also includes：Many root bead lines 104, each bonding wire 104 is from base
Plate 101 is connected to the weld pad of each chip through window and each same layer chip gap, and each chip is believed with substrate 101 respectively
Number connection.In the present embodiment, bonding wire 104 can be using techniques such as gold thread, copper cash or electrum lines.
In an alternate embodiment of the invention, the encapsulating structure of the multi-chip also includes：Plastic packaging material 107, plastic packaging material 107 coats multiple
Chip and many root bead lines.It should be noted that in a particular embodiment, after the completion of each chip-stacked, bonding wire connection, passing through
Plastic packaging material, which is encapsulated, should be noted weighing wounded for bonding wire during these components, plastic packaging, and short circuit etc. is bad.
The encapsulating structure for the multi-chip that the present embodiment is provided, due to having cut through window on substrate, the weld pad position of each chip
In in the drop shadow spread of window so that the weld pad of each chip can carry out signal by the window and substrate and be connected；Due to many
The individual chip-stacked both sides in window, relative in the prior art, the structure of single pile stacked chips is provided in an embodiment of the present invention
Scheme adds chip package density, also, due to each chip-stacked both sides in window, stress is equal when improving chip package
Even property, then improves chip-stacked stability.
When in an alternate embodiment of the invention, due to each chip being connected with substrate signal with many root bead lines respectively, each weldering
Line is connected to the weld pad of each chip from substrate through window and each same layer chip gap, and plastic packaging material is used during encapsulation by multiple cores
Piece and many root bead lines are enveloped so that when carrying out three-dimensional stacked to each chip bonding wire be difficult to be weighed wounded, short circuit.
Obviously, above-described embodiment is only intended to clearly illustrate example, and the not restriction to embodiment.It is right
For those of ordinary skill in the art, can also make on the basis of the above description it is other it is various forms of change or
Change.There is no necessity and possibility to exhaust all the enbodiments.And the obvious change thus extended out or
Among changing still in the protection domain of the invention.
Claims (7)
1. a kind of encapsulating structure of multi-chip, it is characterised in that including：
Multiple chips；
Substrate, window has been cut through for being provided for the multiple chip on placement position, the substrate；
The multiple chip-stacked both sides in the window；The weld pad of each chip is located in the drop shadow spread of the window.
2. the encapsulating structure of multi-chip as claimed in claim 1, it is characterised in that the multiple chip is located at the same of the substrate
Side.
3. the encapsulating structure of multi-chip as claimed in claim 1, it is characterised in that the number of the multiple chip is even number,
The multiple chip is symmetrically distributed in the both sides of the window.
4. the encapsulating structure of multi-chip as claimed in claim 1, it is characterised in that the number of the multiple chip is 2N+1
It is individual, wherein, N is positive integer, and the 1st in the multiple chip to 2N chip is symmetrically distributed in the both sides of the window and shape
Into the gap less than the window；The 2N+1 chip covers the gap.
5. the encapsulating structure of the multi-chip as described in claim 1-4 any one, it is characterised in that the multiple chip-stacked
The number of plies be at least two layers, same layer chip gap is formed between the chip of same layer；Close to the substrate chip layer it is same
Layer chip gap is more than the same layer chip gap of the chip layer away from the substrate, so that the core of the chip layer away from the substrate
Piece weld pad is located in the drop shadow spread in the same layer chip gap of the chip layer of the substrate.
6. the encapsulating structure of multi-chip as claimed in claim 5, it is characterised in that also include：
Many root bead lines, each bonding wire is connected to the weldering of each chip from the substrate through the window and each same layer chip gap
Pad, each chip is connected with the substrate signal respectively.
7. the encapsulating structure of multi-chip as claimed in claim 6, it is characterised in that also include：
Plastic packaging material, coats the multiple chip and many root bead lines.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710398633.6A CN107093599A (en) | 2017-05-31 | 2017-05-31 | The encapsulating structure of multi-chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710398633.6A CN107093599A (en) | 2017-05-31 | 2017-05-31 | The encapsulating structure of multi-chip |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN107093599A true CN107093599A (en) | 2017-08-25 |
Family
ID=59639975
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710398633.6A Withdrawn CN107093599A (en) | 2017-05-31 | 2017-05-31 | The encapsulating structure of multi-chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107093599A (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070088177A (en) * | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | Semiconductor package and method of manufacturing the same |
| US20090134504A1 (en) * | 2007-11-28 | 2009-05-28 | Walton Advanced Engineering, Inc. | Semiconductor package and packaging method for balancing top and bottom mold flows from window |
| US20100295166A1 (en) * | 2009-05-21 | 2010-11-25 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN103887274A (en) * | 2012-12-20 | 2014-06-25 | 三星电子株式会社 | Semiconductor package |
-
2017
- 2017-05-31 CN CN201710398633.6A patent/CN107093599A/en not_active Withdrawn
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20070088177A (en) * | 2006-02-24 | 2007-08-29 | 삼성테크윈 주식회사 | Semiconductor package and method of manufacturing the same |
| US20090134504A1 (en) * | 2007-11-28 | 2009-05-28 | Walton Advanced Engineering, Inc. | Semiconductor package and packaging method for balancing top and bottom mold flows from window |
| US20100295166A1 (en) * | 2009-05-21 | 2010-11-25 | Samsung Electronics Co., Ltd. | Semiconductor package |
| CN103887274A (en) * | 2012-12-20 | 2014-06-25 | 三星电子株式会社 | Semiconductor package |
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Application publication date: 20170825 |
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