CN107070937A - A kind of protocol conversion apparatus based on FPGA - Google Patents
A kind of protocol conversion apparatus based on FPGA Download PDFInfo
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- CN107070937A CN107070937A CN201710288811.XA CN201710288811A CN107070937A CN 107070937 A CN107070937 A CN 107070937A CN 201710288811 A CN201710288811 A CN 201710288811A CN 107070937 A CN107070937 A CN 107070937A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/08—Protocols for interworking; Protocol conversion
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Abstract
The present invention provides a kind of protocol conversion apparatus based on FPGA, including HUB modules, RMII modules, MPU_TO_IO modules, IO_TO_MPU modules and CRC module, the conversion for ethernet link layer protocol to CAN2.0B agreements.This conversion equipment is transmitted and protocol conversion function with realizing the fast and stable of Ethernet information towards the application of the industrial communication of high reliability.
Description
Technical field
The present invention relates to nuclear power station FPGA emulation testings field, a kind of protocol conversion apparatus based on FPGA is particularly related to.
This conversion equipment is transmitted and agreement with realizing the fast and stable of Ethernet information towards the application of the industrial communication of high reliability
Translation function.
Background technology
In Industry Control occasion, in order to the data between different communication bus transmission, it is necessary to carry out communication bus conversion, and
It is exactly a type therein that Ethernet, which transforms to CAN (controller local area network) 2.0B, as shown in Figure 1.Design at present such
During communication switching unit, mostly realized using single-chip microcomputer or microprocessor, such as paper《A kind of Ethernet-CAN circuit designs
With realization》Single channel Ethernet has been described with C8051F040 chip microcontrollers to single channel in Guo Jianzhou, scientific and technological group of China Electronics
CAN translation function, as shown in Figure 2.The conversion equipment that single-chip microcomputer or processor are realized, has that peripheral circuit is more, processing speed
Slow the problems such as, requirement can not be met in the industrial applications for requiring the fast and stable response time.
Also there is Ethernet to turn the product of CAN device in market, implementation have single channel Ethernet to single channel CAN and single channel with
Too net to multichannel CAN, these designs can not meet carry in commercial Application it is a large amount of (>100) high traffic (single device bandwidth>
CAN device 60KHz) is, it is necessary to a plurality of CAN links flexible configuration.Similar work(can be realized with the mode of converter plus interchanger
Can, as shown in Figure 3.But there are the problem of network cable is more, network response time is slow and unstable in this scheme, it is impossible to meet nuclear power
In DCS system of standing communications applications for communication high reliability and high stability requirement.
In collecting, problems with present in prior art：
1st, the converter peripheral circuit complexity realized based on MCU (single-chip microcomputer) or processor technology；
2nd, CAN quantity is fixed in existing converter, is difficult extension；
3rd, forward delay time is long between the Ethernet switch network interface realized based on store-and-forward mode, during the response of communication
Between it is longer, and the stability of time is bad.
The content of the invention
A kind of situation of the purpose of the present invention aiming at above-mentioned prior art, it is proposed that protocol conversion dress based on FPGA
Put, the problem of converter peripheral circuit for solve 1, realizing based on MCU (single-chip microcomputer) or processor technology is complicated；2. existing conversion
CAN quantity is fixed in device, the problem of being difficult extension；3. between the Ethernet switch network interface realized based on store-and-forward mode
Forward delay time is long, and the response time of communication is longer, and the time stability it is bad the problem of.
The purpose of the present invention is achieved through the following technical solutions：A kind of protocol conversion apparatus based on FPGA, even
Be connected between Ethernet and CAN controller, including HUB modules, RMII modules, MPU_TO_IO modules, IO_TO_MPU modules and
CRC module；
The HUB modules are used for the message forwarding for realizing host computer MPU；The HUB modules include physical interface and logic
Interface, the physical interface is connected with the PHY chip of Ethernet, and the logic interfacing carries out data interaction with RMII modules；
The RMII modules are used for the message data to the MPU_TO_IO modules and CRC module transmission host computer MPU,
The reply data of the IO_TO_MPU modules is received, 2B/8B serioparallel exchange is realized；
The MPU_TO_IO modules are used to carry out after CRC decodings, decoding error all messages from host computer MPU
Abandon, after successfully decoded issued in message for each I/O boards output data and other various instructions (version, calibration,
Resetting etc.) classification is put into corresponding groove position and cached, and the requirement according still further to IOBUS-1 and IOBUS-2 agreements will cache message
It is sent to I/O boards；
The IO_TO_MPU modules are used for the state for monitoring CAN controller, and are extracted in 1 communication cycle from I/O
The data of board, are parsed and caching of classifying, and response is carried out to the instruction of the message from host computer MPU after parsing caching；
The CRC module is used to verify the message data of the host computer MPU from the RMII module transfers, will
As a result MPU_TO_IO modules are fed back to；CRC check value calculating is carried out to host computer MPU data to response, result of calculation is anti-
Feed IO_TO_MPU modules.
Further, in addition to SJA_CTRL modules, the SJA_CTRL modules receive the slow of the MPU_TO_IO modules
Stored messages, and send responses to the IO_TO_MPU modules host computer MPU data.
Further, in addition to the TIME_ that is arranged between the MPU_TO_IO modules and the IO_TO_MPU modules
ID modules, time information renovation when extracting MPU_TO_IO modules pair in instruction is in local clock and timing；In IO_TO_MPU
The newest clock information time is extracted during module response host computer MPU.
Further, in addition to PHY_RST modules, it is controlled for the reset to Ethernet PHY chip.
Further, in addition to LIGHT_CT modules, it is controlled for the state to indicator lamp.
A kind of method for converting protocol based on FPGA, comprises the following steps：
1) HUB module forwards host computers MPU message is passed through；
2) the MPU_TO_IO modules carry out abandoning after CRC decodings, decoding error to host computer MPU message data, solution
The output data and other various instructions (version, calibration, reset etc.) issued in message for each I/O boards after code success
Classification is put into corresponding groove position and cached；
3) I/O boards are sent to by message is cached according to the requirement of IOBUS-1 and IOBUS-2 agreements；
4) by the state of the IO_TO_MPU module monitors CAN controller, extracted in 1 communication cycle and come from I/O
The data of board, are parsed and caching of classifying, and carry out response to the instruction of the message from host computer MPU of parsing caching；
5) message data from host computer MPU is verified by the CRC module, result is fed back into MPU_
TO_IO modules；Data to response to host computer MPU carry out CRC check value calculating, and result of calculation is fed back into IO_TO_MPU
Module.
Further, step 2) also include by the TIME_ID modules, when extracting MPU_TO_IO modules pair in instruction
Time information renovation in local clock and timing.
Further, step 4) also include by the TIME_ID modules, it is extracted in IO_TO_MPU module responses upper
Newest clock information time during machine MPU.
Conversion equipment of the present invention has following functions and performance：
1) the slave station data of this management domain are recognized, and CAN device is arrived in data partition；
2) slave station I/O boards are managed, integrates and data cached, host computer MPU is sent to by Ethernet；
3) ethernet communication protocol response time (from instruction is received to the time for replying completion), less than 500us；
4) single device realizes the communication function of 4 road 100MHz Ethernet interfaces, is easy to expanded application；
5) forward delay time between the Ethernet interface in single assembly is less than 100ns.
The beneficial effects of the invention are as follows：
1st, circuit design is simple, low in energy consumption, and reliability is high；
2nd, CAN link spreads are supported, networking mode is flexible；
3rd, realized based on FPGA, program parallelization is performed, it is ensured that within Ethernet transmission delay 100ns, device is to agreement
Maximum response time within 500us, and the response time have other schemes without high stability it is specific.
The present invention instead of the processor in conventional design with FPGA, and the work(of multiple MAC chips is realized in monolithic FPGA
Energy.Multichannel 100M Ethernet interfaces, it is possible to achieve the cascade of equipment room, and realize access of multiple ancillary equipment to Ethernet interface,
Multiple network topology can be supported.Realize the uplink and downlink communication and management function to slave station equipment in CAN.
Brief description of the drawings
Fig. 1 is the communication switching cell schematics of prior art
Fig. 2 realizes Ethernet and CAN transition diagram for the MCU of prior art
Fig. 3 realizes that CAN extends schematic diagram for the exchange manner of prior art
Fig. 4 is a kind of paralell composition of the protocol conversion apparatus based on FPGA of the present invention；
Fig. 5 realizes block diagram for a kind of function of the protocol conversion apparatus based on FPGA of the present invention
Fig. 6 is a kind of FPGA internal logic Organization Charts of the protocol conversion apparatus based on FPGA of the present invention
Fig. 7 receives timing diagram for a kind of RMII of the protocol conversion apparatus based on FPGA of the present invention
Fig. 8 reads timing diagram for a kind of CAN of the protocol conversion apparatus based on FPGA of the present invention
Fig. 9 is a kind of CAN write timing figure of the protocol conversion apparatus based on FPGA of the present invention
The schematic diagram that Figure 10 realizes for a kind of protocol conversion apparatus based on FPGA of the present invention in a control system
Embodiment
A kind of protocol conversion apparatus based on FPGA of the present invention is described further below in conjunction with the accompanying drawings：The embodiment is only
For illustrating the present invention rather than limitation the scope of the present invention, those skilled in the art are to the various equivalent form of values of the invention
Modification falls within the application appended claims limited range.
FPGA (Field-Programmable Gate Array), i.e. field programmable gate array, it be PAL, GAL,
The product further developed on the basis of the programming devices such as CPLD.It is as one in application specific integrated circuit (ASIC) field
Plant semi-custom circuit and occur, both solve the deficiency of custom circuit, original programming device gate circuit number is overcome again to be had
The shortcoming of limit.The circuit design completed with hardware description language (Verilog or VHDL), can pass through simple synthesis and cloth
Office, is quickly burned onto on FPGA and is tested, and is the technology main flow of modern IC designs checking.These editable elements can be by
For realizing the combination function of some basic logic gates (such as AND, OR, XOR, NOT) or more more complicated such as
Decoder or mathematical equation.Inside most FPGA, also for example touched comprising memory cell in these editable elements
Send out device (Flip-flop) or other more complete block of memory.
System designer can connect the logical block inside FPGA as desired by editable connection, all right
As a breadboard has been placed in a chip.One dispatch from the factory after finished product FPGA logical block and connection can be according to
Designer and change, so FPGA can complete required logic function.
Speed of the FPGA in general than ASIC (application specific integrated circuit) is slow, realizes same function than ASIC circuit face
Product is big.But they also have the advantages that it is many such as can quick finished product, the mistake that can be modified in correction program and
Less expensive cost.Manufacturer may also can provide the FPGA of cheap still edit capability difference.Because these chips have poor
Editable ability, so these design exploitations be to be completed on common FPGA, design is then transferred to a class
It is similar on ASIC chip.Another method is with CPLD (Complex Programmable Logic Device, complexity
PLD).
It can be said that fpga chip, which is small lot system, improves one of level of integrated system, the optimal selection of reliability.
FPGA is that its working condition is set by the program being stored in ram in slice, therefore, is needed during work in piece
RAM be programmed.User can be according to different configuration modes, using different programming modes.
During power-up, fpga chip reads in data in EPROM in piece in programming RAM, and after the completion of configuration, FPGA enters work
State.After power down, FPGA reverts to white tiles, and internal logic relation disappears, and therefore, FPGA being capable of Reusability.FPGA programming
Without special FPGA programmable devices, general EPROM, PROM programmable device need only be used.When needing modification FPGA functions, only
A piece of EPROM need to be changed.So, with a piece of FPGA, different programming datas can produce different circuit functions.Therefore,
FPGA use is very flexible.
The present invention instead of the processor in conventional design with FPGA, and the work(of multiple MAC chips is realized in monolithic FPGA
Energy.Multichannel 100M Ethernet interfaces, it is possible to achieve the cascade of equipment room, and realize access of multiple ancillary equipment to Ethernet interface,
Multiple network topology can be supported.
HUB is the forwarding capability that Multi-netmouth transponder realizes network interface data.
RMII is simplified media interface, is the control between FPGA and ethernet PHY and data-interface.
MPU is the abbreviation of main control board, and MainProcess Unit are algorithm computing and the control unit of control station.
I/O boards are a series of boards or module for realizing signal specific type, such as analog input 4-20mA, digital quantity
Output relay contact output etc..
CRC is CRC, is accomplished that CRC-32 is verified herein
SJA_CTRL is FPGA realizations and the interface of SJA1000CAN controller chips.
PHY chip refers to Ethernet PHY chip, realizes the PHY of Ethernet.
It is the paralell composition for the communication nonredundancy that the protocol conversion apparatus based on FPGA is realized as shown in Figure 4,2 upper
Connect several Ethernet/CAN devices of the invention under machine MPU, each Ethernet/CAN device again under connect several CAN devices (I/O plates
Card), each CAN device independent operating.Wherein Ethernet/CAN refers to the protocol conversion apparatus of the present invention, in single assembly with
Forward delay time too between network interface is less than 100ns.
The present apparatus has following functions and performance：
1) the slave station data of this management domain are recognized, and data partition is arrived CAN mouthfuls；
2) slave station I/O boards are managed, integrates and data cached, host computer MPU is sent to by Ethernet；
3) ethernet communication protocol response time (from instruction is received to the time for replying completion), less than 500us；
4) single device realizes the communication function of the 100MHz Ethernet interfaces that HUB is connected with PHY in 4 road FPGA, is easy to extension
Using；
Implementation functional block diagram of the present invention is as shown in figure 5, in figure, and 2 road Ethernets of back plane connector connection exist
2 host computer MPU are connected in, 2 road Ethernets of front panel are connected to the expansion of network.
FPGA conversion equipments internal logic is as shown in fig. 6, logical internal is divided into 10 previous modules, the function of realization
It is as shown in the table：
1 Ethernet of form/CAN device fpga logic decomposition module
As shown in fig. 6, the FPGA conversion equipments are connected between Ethernet and CAN controller, including HUB modules, RMII
Module, MPU_TO_IO modules, IO_TO_MPU modules and CRC module；
The HUB modules are used for the message forwarding for realizing host computer MPU；The HUB modules include physical interface and logic
Interface, the physical interface is connected with the PHY chip of Ethernet, and the logic interfacing carries out data interaction with RMII modules；Institute
Stating RMII modules is used for the message data to the MPU_TO_IO modules and CRC module transmission host computer MPU, receives the IO_
The reply data of TO_MPU modules, realizes 2B/8B serioparallel exchange；The MPU_TO_IO modules are used for from host computer MPU
All messages parsed, and will be after parsing after local effective message information classification caching and management, decoding error
Abandon, after successfully decoded issued in message for each I/O boards output data and other various instructions (version, calibration,
Resetting etc.) classification is put into corresponding groove position, and the requirement according still further to IOBUS-1 and IOBUS-2 agreements by message is cached is sent to I/O
Board；Other various instructions refer to that version, calibration, reset etc. are instructed.
The IO_TO_MPU modules are used for the state for monitoring CAN controller, are extracted within 1 I/O communication cycle and come from I/O
The data of board, are parsed and caching of classifying, and the message instruction to host computer MPU carries out response；The CRC module be used for from
The host computer MPU of RMII module transfers message data is verified, and result is fed back into MPU_TO_IO modules；Correspondence
Answer and carry out CRC check value calculating to host computer MPU data, result of calculation is fed back into IO_TO_MPU modules.
Further, in addition to SJA_CTRL modules, the SJA_CTRL modules receive the slow of the MPU_TO_IO modules
Stored messages, and send responses to the IO_TO_MPU modules host computer MPU data.
Further, in addition to the TIME_ that is arranged between the MPU_TO_IO modules and the IO_TO_MPU modules
ID modules, time information renovation when extracting MPU_TO_IO modules pair in instruction is in local clock and timing；In IO_TO_MPU
The newest clock information time is extracted during module response host computer MPU.
Further, in addition to PHY_RST modules, it is controlled for the reset to Ethernet PHY chip.
Further, in addition to LIGHT_CT modules, it is controlled for the state to indicator lamp.
RMII as shown in Figure 7 is received in timing diagram, the timing Design of 100M network interfaces, it is necessary to support 100Mbps full duplexs
RMII Ethernet interfaces, meet RMII interface sequences.I_clk_50m is the 50MHz global clocks that chip exterior is inputted, i_rxdv
It is effectively mark and the data of the data from HUB interface modules respectively with im_rxdata, the output to MPU_TO_IO modules is believed
Number have o_mac_start, o_d_flag, o_d_sync, om_data, represent respectively initial signal, data effectively identify, data
Valid synchronization signal and serioparallel exchange data.
CAN as shown in Figure 8, Figure 9 reads timing diagram and CAN write timing figure, during CAN chip SJA1000
Sequence (SJA1000 is to refer to CAN controller chip)：Need to support 1Mbps CAN2.0Intel mode interfaces.CAN protocol is using expansion
Exhibition pattern, i_clk_16m is the internal clocking after being divided through PLL phaselocked loops, o_sja_rd_val and o_sja_wr_val difference
It is read states and write state to make CAN controller, and o_sja_ale, o_sja_cs_n and o_sja_rden_n control for respectively CAN
Address latch, chip selection signal and read to enable signal, om_sja_bus_data is writes CAN controller data, iom_sja_data
The data returned for CAN controller.
The agreement that ECC (Ethernet to Can Card) communication card ECC communications A, B in Figure 10 are exactly the present invention turns
Changing device is realized in a control system.In upper figure master control MPU and communication be all Redundancy Design, the MPU interconnections of redundancy
The frame of cascade is formed in ECC communication modules ECC communication A, B of two-way redundancy, the ECC communication module string access systems of subsequent expansion
Structure, this framework can largely reduce the length of the communications cable, and the ECC of present invention design in the arrangement of discrete system
Ensure that multi-stage cascade (<7) the maximum communication time delay in the case of is within 400us.Due to the communication between different cabinets
The physical layer of Ethernet is employed so communication distance can reach the standard of common Ethernet.I/O boards are exactly to be mounted to CAN nets
On equipment.
ECC module ECC communications A, B receive the data from MPU, through internal HUB module forwards to other nodes and originally
RMII interface data is gone here and there and turned by ground logic, the RMII_INTF modules (submodule of RMII modules) of inside modules
Change, give MPU_TO_IO modules and parsed, MPU_TO_IO modules are by the data received according to ethernet communication protocol requirement
Parsing classification is carried out, the data by inspection are put into internal FIFO.The communication cycle of CAN_CTRL modules control CAN nets, often
25ms reads a FIFO, gives CAN_INTF by the data read-out that MPU is issued, is converted to CAN sequential and is sent to IO.
RMII_INTF modules：One submodule of RMII modules.
FIFO：First in first out is represented, is a kind of mode of data storage.
CAN_CTRL：A timing pip in SJA_CTRL.
CAN_INTF：CAN data processing modules, belong to a SAJ_CTRL part.
After data are sent to I/O boards, CAN_CTRL control CAN_INTF monitor I/O board reported datas, will reported
Data write-in IO_TO_MPU modules are cached.IO_TO_MPU modules will upload data and arranged according to CAN protocol, point
Class.When MPU master controls require to reply, RMII_INTF is sent to by IO_TO_MPU modules are data cached, switchs to RMII sequential hair
Give MPU.
Claims (8)
1. a kind of protocol conversion apparatus based on FPGA, is connected between Ethernet and CAN controller, it is characterised in that including
HUB modules, RMII modules, MPU_TO_IO modules, IO_TO_MPU modules and CRC module；
The HUB modules are used for the message forwarding for realizing host computer MPU；The HUB modules include physical interface and logic interfacing,
The physical interface is connected with the PHY chip of Ethernet, and the logic interfacing carries out data interaction with RMII modules；
The RMII modules are used for the message data to the MPU_TO_IO modules and CRC module transmission host computer MPU, receive
The reply data of the IO_TO_MPU modules, realizes 2B/8B serioparallel exchange；
The MPU_TO_IO modules are used to all messages from host computer MPU are carried out to abandon after CRC decodings, decoding error,
The output data and other various instruction classifications that are issued in message for each I/O boards are put into corresponding groove after successfully decoded
Position is cached, then caching message is sent into I/O boards；
The IO_TO_MPU modules are used for the state for monitoring CAN controller, are extracted in 1 communication cycle from I/O boards
Data, are parsed and caching of classifying；And direct response is carried out to host computer MPU message instruction；
The CRC module is used to verify the message data of the host computer MPU from the RMII module transfers, by result
Feed back to MPU_TO_IO modules；Data to response to host computer MPU carry out CRC check value calculating, and result of calculation is fed back to
IO_TO_MPU modules.
2. a kind of protocol conversion apparatus based on FPGA according to claim 1, it is characterised in that also including SJA_CTRL
Module, the SJA_CTRL modules receive the caching message of the MPU_TO_IO modules, and are sent out to the IO_TO_MPU modules
Send data of the response to host computer MPU.
3. a kind of protocol conversion apparatus based on FPGA according to claim 1, it is characterised in that also including being arranged on
The TIME_ID modules between MPU_TO_IO modules and the IO_TO_MPU modules are stated, are instructed when extracting MPU_TO_IO modules pair
In time information renovation in local clock and timing；Newest clock is extracted in IO_TO_MPU module response host computer MPU
Information time.
4. a kind of protocol conversion apparatus based on FPGA according to claim 1, it is characterised in that also including PHY_RST moulds
Block, is controlled for the reset to Ethernet PHY chip.
5. a kind of protocol conversion apparatus based on FPGA according to claim 1, it is characterised in that also including LIGHT_CT
Module, is controlled for the state to indicator lamp.
6. a kind of method for converting protocol based on FPGA, it is characterised in that comprise the following steps：
1) HUB module forwards host computers MPU message is passed through；
2) the MPU_TO_IO modules carry out abandoning after CRC decodings, decoding error to host computer MPU message data, are decoded into
The output data and other various instruction classifications that issue for each I/O boards in message corresponding groove position is put into after work(to carry out
Caching；
3) I/O boards are sent to by message is cached according to the requirement of IOBUS-1 and IOBUS-2 agreements；
4) by the state of the IO_TO_MPU module monitors CAN controller, extracted in 1 communication cycle and come from I/O boards
Data, parse and caching of classifying, and to parsing caching from host computer MPU message instruction carry out response；
5) message data from host computer MPU is verified by the CRC module, result is fed back into MPU_TO_IO
Module；Data to response to host computer MPU carry out CRC check value calculating, and result of calculation is fed back into IO_TO_MPU modules.
7. a kind of method for converting protocol based on FPGA according to claim 6, it is characterised in that step 2) also include leading to
The TIME_ID modules are crossed, time information renovation when extracting MPU_TO_IO modules pair in instruction is in local clock and timing.
8. a kind of method for converting protocol based on FPGA according to claim 6, it is characterised in that step 4) also include leading to
The TIME_ID modules are crossed, the clock information time newest during IO_TO_MPU module response host computer MPU is extracted in.
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| CN117336387A (en) * | 2023-10-31 | 2024-01-02 | 中科驭数（北京）科技有限公司 | Multi-protocol interconnection method, equipment and computer readable storage medium |
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