CN101702839B - Device and method for implementing inverting function of main link and standby link of Ir interface - Google Patents

Device and method for implementing inverting function of main link and standby link of Ir interface Download PDF

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CN101702839B
CN101702839B CN2009102724702A CN200910272470A CN101702839B CN 101702839 B CN101702839 B CN 101702839B CN 2009102724702 A CN2009102724702 A CN 2009102724702A CN 200910272470 A CN200910272470 A CN 200910272470A CN 101702839 B CN101702839 B CN 101702839B
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link
data
fpga
light mouth
processing unit
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CN101702839A (en
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邓标华
李玮
杜仲
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Wuhan Feng and Zhida information technology limited liability company
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Wuhan Hongxin Telecommunication Technologies Co Ltd
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    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D30/00Reducing energy consumption in communication networks
    • Y02D30/70Reducing energy consumption in communication networks in wireless communication networks

Abstract

The invention relates to a device and a method for implementing the inverting function of a main link and a standby link of an Ir interface between a baseband unit and a radio frequency far-end unit in a TD-SCDMA system. The device mainly comprises two lasers, an FPGA and a CPU, wherein the FPGA is respectively connected with the two lasers and the CPU, and every two lasers finish the data transmission of a link. The method realizes matrix switching by utilizing a field programmable gate array, wherein main and standby link information extracted by an optical interface main and standby link detecting module and an Ir interface working mode command sent by a central processing unit are used as references, the outputs of an upstream link and a downstream link are dynamically switched through a matrix switching technology so as to realize the inverting function of the main link and the standby link of the Ir interface, improve the real-time of processing, greatly save the internal resources of the FPGA and be helpful to the cost reduction and the miniaturization of an RRU. The invention has the characteristics of less resource, low cost, high efficiency and low power consumption and is favorable to the system miniaturization.

Description

Ir interface active/standby link switching function implement device and method
Technical field
The present invention relates to a kind of in TD-SCDMA RRU system employed realization Ir interface active/standby link switching function implement device and method.
Background technology
Remote radio unit (RRU) (RRU) is a part important in the 3G communication system, for being attached to a communication module of base station (NODE B).The remote radio unit (RRU) major function is to accomplish the blind area to cover, and reduces base station number, and this module can be delivered to data the Base Band Unit (BBU) of the upper-level BTS that is depended on through optical fiber.
Reliability and the validity of TD-SCDMA in order to guarantee to communicate by letter between RRU and the BBU, employing be Ir (Interface between RRU and BBU) interface protocol, the relation of this interface and base station is shown in accompanying drawing 1.That the Ir interface is supported is star-like, chain and ring-shaped network form, has four kinds of mode of operations such as common, cascade, active and standby, load sharing, and under active and standby pattern, the network construction form of RRU and BBU is a Star Network, and promptly RRU is connected with BBU through 2 optical interfaces.For the reliability that guarantees to communicate by letter; RRU uses key light mouth and BBU to carry out transfer of data under the normal condition; Automatically accomplish transfer of data by being equipped with the light mouth after the key light mouth fault, so the masterslave switchover function there is very important meaning to the reliability of communicating by letter between RRU and the BBU.Traditional method is that RRU inside is handled 2 reception data on the light mouth simultaneously; And will eat dishes without rice or wine to go up the data that receive returns to BBU through 2 light mouths simultaneously; And no matter key light mouth fault whether, than higher, therefore cost also can increase many this method as far as the RRU resource requirement; Nor be beneficial to system's miniaturization, and then add to the difficulties for the stability of a system.
Summary of the invention
The objective of the invention is in order to overcome the defective that conventional method exists, provide that a kind of resource is few, cost is low, efficient is high, low in energy consumption, the Ir interface active/standby link switching function implement device and the method that help system's miniaturization.The inventive method and device are to be core with field programmable gate array (FPGA), and with respect to central processor CPU and these software control means of digital signal processor DSP, FPGA is parallel fully hardware structure.We can receive the data on 2 light mouths of down direction (downlink) simultaneously based on this, and only the data on effective light mouth are exchanged to the downlink data processing unit through a switching matrix (XCSUM); Equally; At up direction (uplink), after RRU inside is will be from the data processing of eating dishes without rice or wine to receive good, also upstream data is sent to effective light mouth through a switch matrix; Another light mouth does not then send; So just can guarantee that up-downlink direction all respectively has and an intact link is only arranged, thereby save the FPGA internal resource greatly, therefore cost and power consumption also reduce.
Device of the present invention; As shown in Figure 2; Mainly constitute: two laser instruments, FPGA, CPU by following components; FPGA links to each other with two laser instruments, CPU respectively; Per two laser instruments are accomplished the transfer of data of a link; The function of this each module of device is following: CPU is responsible for providing Ir interface mode of operation, and through data/address bus notice FPGA, so that two switching matrixs (XCSUM) unit of FPGA can correctly be operated under the active and standby pattern; Two laser instruments are responsible for accomplishing the conversion of photosignal or electro-optical signal; FPGA is responsible for receiving in real time the signal of telecommunication of 2 laser instrument inputs, and converts serial data into parallel data, and the requirement based on the Ir interface protocol afterwards detects main/slave link to control an XCSUM1 unit completion active/standby link switching from 2 links; Based on Ir mode of operation and active/standby link switchover order, another XCSUM2 is switched to link 0 and link 1 with the output signal of uplink downlink processing unit again, outputs to light mouth 0 and light mouth 1 in completion and string conversion back respectively through two laser instruments.
Ir interface active/standby link switching function implementation method of the present invention may further comprise the steps:
(1) laser 0 is accomplished the reception and the transmission of light mouth 0 data; Another laser 1 is accomplished the reception and the transmission of light mouth 1 data;
(2) CPU is configured the register of FPGA, and notice FPGA is operated in active and standby pattern, and FPGA just thinks that 2 light mouths are down link like this, a primary link and a reserve link; If CPU is not provided with the mode of operation of FPGA, then FPGA acquiescence is operated in the cascade pattern of Ir interface, and light mouth 0 is down link, and light mouth 1 is a up link;
(3) two of FPGA serial/parallel unit high-speed-differential serial signal that laser is sent here converts the 10bit parallel data into, accomplishes 8B/10B decoding back output 8bit parallel data;
(4) the main/slave link detecting unit of FPGA is searched for primary link Information sign 0xE7 with definite active/standby link according to the requirement of Ir agreement at the 16th byte place of physical layer control word of 5ms radio frames, and controls the work of XCSUM1 and XCSUM2 with this;
(5) two of FPGA XCSUM unit are according to the configuration of CPU; Confirm the mode of operation of Ir interface; If active and standby pattern and light mouth 0 are primary link, then XCSUM1 to the down link processing unit, exchanges to uplink processing unit and the data of light mouth 1 all are reset to 0 with the exchanges data of light mouth 0 again; XCSUM2 gives BBU to link 0 with passback with the exchanges data of uplink processing unit; And the dateout of forward downlink processing unit not is reset to 0 with link 1 simultaneously, and notice CPU closes laser 1; In like manner; Be primary link if the Ir interface is active and standby pattern and a light mouth 1, then XCSUM1 to the down link processing unit, exchanges to uplink processing unit and the data of light mouth 0 all are reset to 0 with the exchanges data of light mouth 1 again; XCSUM2 gives BBU to link 1 with passback with the exchanges data of uplink processing unit; And the dateout of forward downlink processing unit not is reset to 0 with link 0 simultaneously, and notice CPU closes laser 0; If the Ir interface is operated in the cascade pattern; Then light mouth 0 is a down link, and light mouth 1 is a up link, and XCSUM1 arrives the down link processing unit with the exchanges data of light mouth 0; With the exchanges data of light mouth 1 to the uplink processing unit; Correspondingly, XCSUM2 arrives link 0 with the exchanges data of down link processing unit output, and uplink processing unit dateout is exchanged to link 1;
(6) the down link processing unit of FPGA is responsible for extracting the required carrier wave of RRU at the corresponding levels (AxC) data and control and management (C&M) data, and the light mouth data of down link are transmitted to next stage RRU after treatment;
(7) the uplink processing unit of FPGA is responsible for AxC data with RRU at the corresponding levels digital coding is become the Ir radio frames with C&M, under the cascade pattern, also need synthesize with the Ir radio frames of the RRU of subordinate, gives BBU with synthetic good transfer of data;
(8) the 8bit parallel data that will deliver on the light mouth of in addition two parallel/serial unit of FPGA is carried out the 8B/10B coding; Output 10bit parallel data; Convert it into the high-speed-differential serial signal more afterwards and give laser; By laser the signal of telecommunication is become light signal again, be transferred to next stage RRU or BBU respectively.
Above-mentioned steps (2) repeats to step (8), just can accomplish switching of Ir interface main/slave link in real time.
The present invention has that resource is few, cost is low, efficient is high, low in energy consumption, help system's miniaturization characteristics.
Description of drawings
Fig. 1 is the position view of Ir interface and base station in the 3G system.
Fig. 2 is the Ir interface active/standby changeover apparatus block diagram that the inventive method adopted.
Fig. 3 is the key step flow chart that the inventive method adopted.
5ms wireless frame structure sketch map when Fig. 4 is 2.4576Gbps for Ir interface rate in the 3G system.
Embodiment
Below in conjunction with accompanying drawing the present invention is described further.
As shown in Figure 2; Device of the present invention mainly is made up of following components: two lasers, FPGA, CPU, and FPGA links to each other with two lasers, CPU respectively; Per two lasers are accomplished the transfer of data of a link; The function of this each module of device is following: CPU is responsible for providing Ir interface mode of operation, and through data/address bus notice FPGA, so that two switching matrixs (XCSUM) unit of FPGA can correctly be operated under the active and standby pattern; Two lasers are responsible for accomplishing the conversion of photosignal or electro-optical signal; FPGA is responsible for receiving in real time the signal of telecommunication of 2 laser inputs, and converts serial data into parallel data, and the requirement according to the Ir interface protocol afterwards detects main/slave link to control an XCSUM1 unit completion active/standby link switching from 2 links; According to Ir mode of operation and active/standby link switchover order, another XCSUM2 is switched to link 0 and link 1 with the output signal of uplink downlink processing unit again, outputs to light mouth 0 and light mouth 1 in completion and string conversion back respectively through two lasers.
Because the Ir interface protocol requires RRU can support common, cascade, active and standby, four kinds of mode of operations of load sharing simultaneously, general mode only uses 1 light mouth, and another light mouth does not possess any function; The cascade pattern is used 2 light mouths simultaneously, and a light mouth connects one-level RRU or BBU, and another light mouth connects next stage RRU; Active and standby and load sharing pattern is all used in hub-and-spoke network topology; 2 light mouths all link to each other with BBU, and one is the key light mouth, and another is for being equipped with the light mouth; In order to make the resource utilization maximization of FPGA; The best way is only to use a bars processing unit at up-downlink direction, utilizes switching matrix to carry out link switchover respectively in its rear and front end, and link all can proper communication under different working modes to guarantee Ir; Device block diagram among Fig. 2 just is being based on above factor and is designing, and therefore has higher resource multiplex rate and practical value.
In device block diagram shown in Figure 2; When 2 optical interface links being carried out the main/slave link detection, at first need carry out synchronous detecting with the wireless frame head of search 5ms, in case find frame head to the data on 2 light mouths; Then link gets into synchronous regime, otherwise link is in desynchronizing state.According to the Ir interface protocol, under 2.4576Gbps light mouth speed, its 5ms wireless frame structure is as shown in Figure 4; The agreement regulation: if locate to send the 0xE7 sign in first ultra the 16th byte (Byte15) of organizing first group (Group0) of (Super-Group0), and send 8 5ms radio frames continuously, then this light mouth is the key light mouth; Otherwise be subsequent use light mouth, therefore, the main/slave link detecting unit can detect main/slave link according to this; Provide switching command; Switching command is 0, and expression light mouth 0 is a primary link, and switching command is that 1 expression light mouth 1 is primary link.
As shown in Figure 3; After the XCSUM1 of FPGA and XCSUM2 unit receive the Ir interface mode of operation configuration order from CPU, confirm the mode of operation of Ir interface, if active and standby pattern and light mouth 0 are primary link; Then XCSUM1 arrives the down link processing unit with the exchanges data of light mouth 0; Exchange to the uplink processing unit again and the data of light mouth 1 all are reset to 0, XCSUM2 gives BBU to link 0 with passback with the exchanges data of uplink processing unit, and the dateout of forward downlink processing unit not; Simultaneously link 1 is reset to 0, and notice CPU closes laser 1; In like manner; Be primary link if the Ir interface is active and standby pattern and a light mouth 1, then XCSUM1 to the down link processing unit, exchanges to uplink processing unit and the data of light mouth 0 all are reset to 0 with the exchanges data of light mouth 1 again; XCSUM2 gives BBU to link 1 with passback with the exchanges data of uplink processing unit; And the dateout of forward downlink processing unit not is reset to 0 with link 0 simultaneously, and notice CPU closes laser 0.
If the Ir interface is operated in general mode; Then RRU only uses a light mouth, and another light mouth does not use, and is the same with active and standby pattern principle; RRU only adopts the key light port communications; In case after confirming the key light mouth, FPGA notice CPU closes the laser of another one light mouth, no longer receives and send the data on this light mouth.
If the Ir interface is operated in the cascade pattern; Then give tacit consent to light mouth 0 and be down link, light mouth 1 is a up link, and XCSUM1 arrives the down link processing unit with the exchanges data of light mouth 0; With the exchanges data of light mouth 1 to the uplink processing unit; Correspondingly, XCSUM2 arrives link 0 with the exchanges data of down link processing unit output, and uplink processing unit dateout is exchanged to link 1.
If the Ir interface is operated in the load sharing pattern; Then transmit the AxC data simultaneously on 2 light mouths; And have only the key light oral instructions to fail the C&M data; XCSUM1 all exchanges to the down link processing unit with the data on 2 light mouths, and correspondingly, XCSUM2 exchanges to all AxC data separated into two parts of RRU at the corresponding levels respectively on 2 light mouths.
The down link processing unit of FPGA is responsible for extracting required AxC data of RRU at the corresponding levels and C&M data, and the light mouth data of down link are transmitted to next stage RRU after treatment.AxC data with RRU at the corresponding levels are responsible in the uplink processing unit of FPGA, and digital coding becomes the Ir radio frames with C&M, under the cascade pattern, also need synthesize with the Ir radio frames of the RRU of subordinate, gives BBU with synthetic good transfer of data.The parallel/serial unit of FPGA carries out the 8B/10B coding with the 8bit parallel data of uplink processing unit output; Be transformed to the 10bit parallel data; Convert it into the high-speed-differential serial signal more afterwards and give laser; By laser the signal of telecommunication is become light signal again, be transferred to next stage RRU or BBU respectively.
The above embodiment of the present invention only is explanation method of the present invention, and protection range of the present invention is limited claims.

Claims (2)

1.Ir interface active/standby link switching function implement device; Mainly constitute: two lasers, FPGA, CPU by following components; It is characterized in that: FPGA links to each other with two lasers, CPU respectively, and per two lasers are accomplished the transfer of data of a link, and CPU is responsible for providing Ir interface mode of operation; And through data/address bus notice FPGA, so that two switching matrixs (XCSUM) unit of FPGA can correctly be operated under the active and standby pattern; Two lasers are responsible for accomplishing the conversion of photosignal or electro-optical signal; FPGA is responsible for receiving in real time the signal of telecommunication of 2 laser inputs, and converts serial data into parallel data, and the requirement according to the Ir interface protocol afterwards detects main/slave link to control an XCSUM1 unit completion active/standby link switching from 2 links; According to Ir mode of operation and active/standby link switchover order; Another XCSUM2 is switched to link 0 or link 1 with the output signal of uplink downlink processing unit again; Output to light mouth 0 in completion and string conversion back through a laser 0, perhaps output to light mouth 1 through another laser 1.
2.Ir interface active/standby link switching function implementation method may further comprise the steps:
(1) laser 0 is accomplished the reception and the transmission of light mouth 0 data; Another laser 1 is accomplished the reception and the transmission of light mouth 1 data;
(2) CPU is configured the register of FPGA, and notice FPGA is operated in active and standby pattern, and FPGA just thinks that 2 light mouths are down link like this, a primary link and a reserve link; If CPU is not provided with the mode of operation of FPGA, then FPGA acquiescence is operated in the cascade pattern of Ir interface, and light mouth 0 is down link, and light mouth 1 is a up link;
(3) two of FPGA serial/parallel unit high-speed-differential serial signal that laser is sent here converts the 10bit parallel data into, accomplishes 8B/10B decoding back output 8bit parallel data;
(4) the main/slave link detecting unit of FPGA is searched for primary link Information sign 0xE7 with definite active/standby link according to the requirement of Ir agreement at the 16th byte place of physical layer control word of 5ms radio frames, and controls the work of XCSUM1 and XCSUM2 with this;
(5) two of FPGA XCSUM unit are according to the configuration of CPU; Confirm the mode of operation of Ir interface; If active and standby pattern and light mouth 0 are primary link, then XCSUM1 to the down link processing unit, exchanges to uplink processing unit and the data of light mouth 1 all are reset to 0 with the exchanges data of light mouth 0 again; XCSUM2 gives BBU to link 0 with passback with the exchanges data of uplink processing unit; And the dateout of forward downlink processing unit not is reset to 0 with link 1 simultaneously, and notice CPU closes laser 1; In like manner; Be primary link if the Ir interface is active and standby pattern and a light mouth 1, then XCSUM1 to the down link processing unit, exchanges to uplink processing unit and the data of light mouth 0 all are reset to 0 with the exchanges data of light mouth 1 again; XCSUM2 gives BBU to link 1 with passback with the exchanges data of uplink processing unit; And the dateout of forward downlink processing unit not is reset to 0 with link 0 simultaneously, and notice CPU closes laser 0; If the Ir interface is operated in the cascade pattern; Then light mouth 0 is a down link, and light mouth 1 is a up link, and XCSUM1 arrives the down link processing unit with the exchanges data of light mouth 0; With the exchanges data of light mouth 1 to the uplink processing unit; Correspondingly, XCSUM2 arrives link 0 with the exchanges data of down link processing unit output, and uplink processing unit dateout is exchanged to link 1;
(6) the down link processing unit of FPGA is responsible for extracting the required carrier wave of RRU at the corresponding levels (AxC) data and control and management (C&M) data, and the light mouth data of down link are transmitted to next stage RRU after treatment;
(7) the uplink processing unit of FPGA is responsible for AxC data with RRU at the corresponding levels digital coding is become the Ir radio frames with C&M, under the cascade pattern, also need synthesize with the Ir radio frames of the RRU of subordinate, gives BBU with synthetic good transfer of data;
(8) the 8bit parallel data that will deliver on the light mouth of in addition two parallel/serial unit of FPGA is carried out the 8B/10B coding; Output 10bit parallel data; Convert it into the high-speed-differential serial signal more afterwards and give laser; By laser the signal of telecommunication is become light signal again, be transferred to next stage RRU or BBU respectively;
Above-mentioned steps (2) repeats to step (8), just can accomplish switching of Ir interface main/slave link in real time.
CN2009102724702A 2009-10-20 2009-10-20 Device and method for implementing inverting function of main link and standby link of Ir interface Active CN101702839B (en)

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CN101931455B (en) * 2010-07-26 2013-04-10 武汉邮电科学研究院 Method for realizing base band and intermediate frequency data interface in radio-frequency remote-end unit (RRU) and method thereof
CN101998518B (en) * 2010-11-23 2013-04-24 北京北方烽火科技有限公司 Base station IR interface data transmission system and method
CN107492783A (en) * 2016-06-13 2017-12-19 常州星宇车灯股份有限公司 A kind of control system of laser
CN111181630B (en) * 2020-01-03 2023-09-29 云南电网有限责任公司电力科学研究院 Method for switching standby optical fiber optical port of transformer substation process layer network and electronic equipment

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CN101426216A (en) * 2008-12-09 2009-05-06 信息产业部电信传输研究所 Test method and device for wireless access system distributed base station
CN101447836A (en) * 2008-12-30 2009-06-03 芯通科技(成都)有限公司 Production testing method to TD-SCDMA radio remote unit

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Publication number Priority date Publication date Assignee Title
CN101426216A (en) * 2008-12-09 2009-05-06 信息产业部电信传输研究所 Test method and device for wireless access system distributed base station
CN101447836A (en) * 2008-12-30 2009-06-03 芯通科技(成都)有限公司 Production testing method to TD-SCDMA radio remote unit

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