CN107017304A - 半导体切换装置以及制造半导体切换装置的方法 - Google Patents

半导体切换装置以及制造半导体切换装置的方法 Download PDF

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CN107017304A
CN107017304A CN201710040199.4A CN201710040199A CN107017304A CN 107017304 A CN107017304 A CN 107017304A CN 201710040199 A CN201710040199 A CN 201710040199A CN 107017304 A CN107017304 A CN 107017304A
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semiconductor regions
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马哈茂德·谢哈布·穆罕默德·阿尔沙蒂
约翰内斯·J·T·M·唐克尔
帕图斯·胡贝图斯·柯奈利斯·马尼
伊戈尔·布鲁内斯
阿努拉格·沃赫拉
让·威廉·斯伦特伯
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NXP BV
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Abstract

本发明提供一种用于切换射频信号的半导体切换装置以及一种制造该半导体切换装置的方法。该装置包括具有第一导电性类型的第一半导体区域。该装置还包括位于第一半导体区域中的源极区域和漏极区域。源极区域和漏极区域具有第二导电性类型。第二导电性类型不同于第一导电性类型。该装置另外包括分离源极区域与漏极区域的栅极。该装置还包括具有第二导电性类型的至少一个沉降区域。每个沉降区域可连接到外部电势以用于吸引少数载流子远离源极区域和漏极区域以减少在源极区域和漏极区域与第一半导体区域之间的接合点处的泄漏电流。

Description

半导体切换装置以及制造半导体切换装置的方法
技术领域
本发明涉及用于切换射频信号的半导体切换装置以及制造用于切换射频信号的半导体切换装置的方法。
背景技术
例如功率MOSFET的半导体装置可以用作用于高频脉宽调制应用的电力开关并且作为功率应用中的负载开关。当用作负载开关时，其中切换时间通常较长，开关的成本、大小和导通电阻(R开)是主要设计考虑因素。当用于高频脉宽调制应用时，可能需要MOSFET在切换期间呈现较小功率损耗，这施加了较小内部电容的额外要求。评估功率MOSFET的性能的最受欢迎的方式中的一个是计算优值(figure of merit，FOM)，优值可被定义为装置的接通状态电阻(R开)和断开状态电容(C关)的乘积。装置内的泄漏电流对装置的总体性能而言也是重要的。
发明内容
在随附的独立权利要求和从属权利要求中陈述了本发明的各方面。从属权利要求的特征的组合可以按需要与独立权利要求的特征进行组合，并且不仅仅是按照权利要求书中所明确陈述的那样组合。
根据本发明的一个方面，提供一种用于切换射频信号的半导体切换装置，该半导体切换装置包括：
第一半导体区域，该第一半导体区域具有第一导电性类型；
位于第一半导体区域中的源极区域和漏极区域，其中源极区域和漏极区域具有第二导电性类型，其中第二导电性类型不同于第一导电性类型；
栅极，该栅极分离源极区域与漏极区域；以及
至少一个沉降区域，该至少一个沉降区域具有第二导电性类型，其中每个沉降区域可连接到外部电势以用于吸引少数载流子远离源极区域和漏极区域以减少在源极区域和漏极区域与第一半导体区域之间的接合点处的泄漏电流。
根据本发明的另一方面，提供一种制造用于切换射频信号的半导体切换装置的方法，该方法包括：
提供具有第一导电性类型的第一半导体区域；
形成栅极；
形成位于第一半导体区域中的源极区域和漏极区域，其中源极区域和漏极区域具有第二导电性类型，其中第二导电性类型不同于第一导电性类型，其中栅极分离源极区域与漏极区域；以及
形成具有第二导电性类型的至少一个沉降区域，其中每个沉降区域可连接到外部电势以用于吸引少数载流子远离源极区域和漏极区域以减少源极区域和漏极区域与第一半导体区域之间的接合点处的泄漏电流。
在用于切换射频信号的半导体切换装置中，该装置包括位于不同导电性类型的半导体区域中的源极区域和漏极区域，泄漏电流可以发生在通过源极区域/漏极区域和第一半导体区域形成的二极管中。举例来说，此泄漏电流可以由于在低温处的耗尽电流和在较高温度处的扩散电流。至少一个沉降区域的提供可以允许此泄漏电流通过吸引少数载流子(与上述扩散电流相关联)远离源极区域和漏极区域而减小。这可以在一些实施例中实现而无须必须降级装置的计算优值(R开×C关)和/或无须增大装置复杂性。
在一些例子中，至少一个沉降区域中的至少一个可以位于具有源极区域和漏极区域的第一半导体区域中。沉降区域邻近于源极区域和漏极区域可以增强沉降区域防止少数载流子到达源极区域和漏极区域与第一半导体区域之间的接合点的能力。
第一半导体区域中的至少一个沉降区域可以通过位于第一半导体区域中的例如虚拟栅极或隔离区域(例如，包含电介质的沟槽)的间隔物与源极区域或漏极区域分离。
在一些例子中，源极区域和/或漏极区域可以配备有它们自身的沉降区域。相应地，沉降区域中的一个可以是位于第一半导体区域中的源极区域附近的源极沉降区域并且沉降区域中的一个可以是位于第一半导体区域中的漏极区域附近的漏极沉降区域。针对源极区域和/或漏极区域的相应的沉降区域的分配可以增强沉降区域吸引少数载流子远离源极区域和漏极区域的能力。
至少一个沉降区域中的至少一个可以位于第一半导体区域外部。这些沉降区域可以电连接到装置的下层衬底区域。通过提供第一半导体区域外部的沉降区域，可以避免源极区域和漏极区域附近的装置复杂性的增大，这可以使得装置更容易制造。位于第一半导体区域外部的沉降区域可以位于通过隔离区域(例如，填充有电介质的沟槽)分离第一半导体区域的半导体区域中。
在一些例子中装置可以包括至少一个具有第一导电性类型的另外的半导体区域。这些另外的半导体区域可以连接到外部电势以用于将电势施加到第一半导体区域。这可以允许通过源极区域、漏极区域和栅极形成的晶体管的主体区域发生偏置。
至少一个另外的半导体区域中的至少一个可以位于具有源极区域和漏极区域的第一半导体区域中。至少一个另外的半导体区域中的至少一个可以位于第一半导体区域外部并且可以经由装置的下层衬底区域电连接到第一半导体区域。
在一些例子中，装置可以包括紧密地位于第一半导体区域下方的具有所述第一导电性类型的半导体层。另外区域的掺杂水平可以高于第一半导体区域的掺杂水平。具有所述第一导电性类型的半导体层可以另外减少装置内的泄漏电流。据设想，在一些例子中，装置可不包括在此类例子中上文所述种类的半导体层，第一半导体区域可以直接地位于装置的下层衬底区域上。以此方式将第一半导体区域直接提供在下层衬底区域上可以减少装置内的寄生接合点电容(由于高度掺杂的半导体层的缺乏可以允许第一半导体区域附近的掺杂的数量减小)，以减少装置的断开状态电容。在此类例子中，装置中的潜在地较高的泄漏电流可以通过至少一个沉降区域的提供而缓解。
第一导电性类型可以是p型，且第二导电性类型可以是n型。相应地，在一些实施例中，装置可以包括NMOS晶体管。然而，还设想出第一导电性类型可以是n型并且第二导电性类型可以是p型。相应地，在一些实施例中，装置可以包括PMOS晶体管。
外部电势可以接地。在第一导电性类型是p型的情况下，外部电势可以是正电势。相反地，在第一导电性类型是n型的情况下，外部电势可以是负电势。外部电势可以是装置的电源电势。
出于本发明的目的“射频(Radio Frequency，RF)”是指通常在0.5GHz≤f≤30GHz范围内的频率，但不限于此。应注意虽然根据本发明的实施例的半导体切换装置可用于通过或阻断射频信号，但是通常装置将实际上不会在射频频率本身下切换。
附图说明
在下文中将仅借助于例子参考附图来描述本发明的实施例，在附图中相同的附图标记指代相同的元件，并且在附图中：
图1示出根据本发明的实施例的半导体装置；以及
图2示出根据本发明的另一个实施例的半导体装置。
具体实施方式
在下文中参考附图描述本发明的实施例。
图1和2各自示出根据本发明的实施例的半导体装置10。装置10可以在包括例如硅的半导体衬底上实施。据设想衬底可以是包括在绝缘层上磊晶地生长的硅层的所谓的绝缘体上硅(Silicon on Insulator，SOI)衬底。在图1和2中所示的例子中，装置包括形成NMOS(N沟道金属氧化物半导体)晶体管的特征。然而，据设想本发明的实施例还可以包括形成PMOS(P沟道金属氧化物半导体)晶体管的特征。将了解图1和2中所示的实施例可以替代于NMOS装置被实施为PMOS装置，方法是简单地逆转掺杂物的极性(例如，使得n型区被p型区替代，且反之亦然)。
图1中的装置包括第一半导体区域40，该第一半导体区域40可以包括掺杂为具有p型导电性的硅。在此例子中第一半导体区域40(以及下文描述的半导体区域43和半导体区域41)由位于半导体衬底的主表面附近的硅的区域形成。在此例子中，第一半导体区域40位于埋入式半导体层38的顶部。层38是p型掺杂的，并且具有高于第一半导体区域40的掺杂水平。层38可以提供为减少下文描述的NMOS装置内的泄漏电流。
应注意埋入半导体层38可以跨越衬底延伸，由此半导体区域43和半导体区域41也可以位于埋入半导体层38的顶部上。在当前例子中，埋入半导体层38位于半导体衬底的下层部分36的顶部上。如同第一半导体区域40，半导体区域43也可以掺杂为具有p型导电性。半导体区域41可以是不掺杂或低掺杂的。
在一些实施例中，层38内的掺杂物水平可以降低，或者可以省略层38(在此情况下第一区域40、区域41和区域43可以直接位于半导体衬底的下层部分36上)。可以采用这些步骤以便减少用于装置中的掺杂物的总量，由此寻求减少装置10内的寄生接合点电容。虽然这还可以潜在地引起装置10内的泄漏电流的增大，但是据设想这可以通过提供下文将描述的沉降区域8来缓解。
第一半导体区域40、半导体区域43、半导体区域41和它们位于其上的埋入半导体层38的部分可以通过一个或多个隔离区域52彼此分离。隔离区域52可以例如包括填充有电介质或具有低导电性的例如无掺杂多晶硅的材料的沟槽。沟槽可以内衬有一个或多个电介质层54，例如，氧化硅。隔离区域52可以从衬底的主表面向下延伸到衬底中，并且可以完全通过形成第一半导体区域40、半导体区域43和半导体区域41的半导体区域，且完全通过埋入半导体层38。隔离区域52可以至少部分延伸到半导体衬底的下层部分36中。虽然未在图1中示出，但是半导体衬底的下层部分36的较低部分未通过隔离区域彼此隔离(其仅部分地延伸到半导体衬底的下层部分36中)，并且相应地第一半导体区域40可以经由下层部分36(并且还经由任选的埋入层38)电连接到半导体区域43和半导体区域41。
在一些例子中，另外的隔离区域30(例如，浅沟槽隔离(STI))可以位于半导体衬底的主表面处。这些隔离区域30可以允许位于半导体衬底的表面或半导体衬底的表面附近的装置10的特征彼此分离。举例来说，在此例子中，包括STI的隔离区域30用于分离形成于第一半导体区域40中的NMOS晶体管的特征与下文将描述的另外的半导体区域22。
一个或多个金属间电介质层24、26、28可以提供在主表面上(例如，氧化硅和氮化硅)。
在此例子中装置10还包括源极区域2和漏极区域6，源极区域2和漏极区域6都位于第一半导体区域40内。在此例子中源极区域2和漏极区域6掺杂以具有n型导电性。源极区域2和漏极区域6通过栅极4分离。栅极4可以包括位于栅极电介质上的栅极电极，栅极电介顾本身可以位于半导体衬底的主表面的部分上，该半导体衬底位于源极区域2与漏极区域6之间。将了解在此例子中通过源极区域2、漏极区域6和栅极4形成的晶体管是NMOS晶体管，然而如先前所提到，据设想本发明的实施例可以替代地使用PMOS晶体管来应用。
触点12、16可以相应地提供到源极区域2和漏极区域6的电连接。类似触点可用于为栅极4(在图1中未示出)提供电连接。每个触点可以包括部分42，部分42向下延伸穿过金属间电介质层24、26、28以与源极区域2、漏极区域6和栅极4连接。
为了将电势施加到第一半导体区域40(其中NMOS晶体管的通道区域将在装置10的操作期间形成)，在此例子中提供另一半导体区域22。另外的半导体区域22可以位于半导体区域43中。在此例子中另外的半导体区域22掺杂为具有p型导电性，并且通常可以具有高于半导体区域43的掺杂水平的掺杂水平。
如图1所示，另外的半导体区域22可以配备有类似于上文相对于源极区域2和漏极区域6所述的触点12、16的触点32。如先前所描述，半导体区域43经由半导体衬底的下层部分36电连接到第一半导体区域40，使得施加到触点32的电势可用于改变第一半导体区域40内的电势。
根据本发明的实施例，装置10配备有至少一个沉降区域8。在此例子中每个沉降区域8被掺杂为具有n型导电性。在形成PMOS晶体管的装置中，沉降区域可以替代地被掺杂为具有p型导电性。沉降区域8的掺杂水平(以及源极区域2和漏极区域6的掺杂水平)可以高于第一半导体区域40的掺杂水平(还应注意沉降区域8、源极区域2和漏极区域6各自具有不同于第一半导体区域40的导电性类型)。据设想沉降区域8可以使用用于形成源极区域2和漏极区域6的相同处理步骤(例如，通过离子植入)形成于第一半导体区域中。
每个沉降区域可以是可连接到外部电势的。举例来说，如图1所示，每个沉降区域8可以配备有触点18，触点18可以类似于上文关于源极区域2和漏极区域6所述的触点12、16。
在当前例子中，每个沉降区域8位于第一半导体区域40中。当前例子包括两个沉降区域8。据设想可以提供单个沉降区域8(或大于两个沉降区域8)。如图1所示，沉降区域中的一个(在本文中被称作源极沉降区域)位于源极区域8附近。同样如图1中所示，另一沉降区域8(在本文中被称作漏极沉降区域)位于漏极区域6附近。位于第一半导体区域40中的每个沉降区域8可以通过例如间隔物与源极区域或漏极区域分离。在当前例子中，每个间隔物包括虚拟栅极20，虚拟栅极20可以位于半导体衬底的主表面上，介于源极区域2或漏极区域6与沉降区域8之间。据设想，可以使用其它种类的间隔物，此类隔离区域(例如，包含电介质的沟槽)位于第一半导体区域40中在源极区域2或漏极区域6与沉降区域8之间。
NMOS或PMOS晶体管中的泄漏电流的潜在地相当大的份额源自穿过二极管的泄漏电流，该二极管由源极区域和漏极区域与它们所在的半导体区域(具有不同的)之间的接合点形成。此泄漏电流可以由于在低温下的耗尽电流和较高温度下的扩散电流。
根据本发明的实施例，施加到沉降区域8的电势可用于吸引少数载流子(与上述扩散电流相关联)远离源极区域和漏极区域。这可以减少在源极区域2和漏极区域6与第一半导体区域40之间的接合点处的泄漏电流。以此方式，装置10内的泄漏电流可以不需要一定使装置10的计算优值(R开×C关)降级和/或不需要显著增大装置10的复杂性的方式减小。
在图1的例子中，第一半导体区域40内的沉降区域8的位置可以增强它们吸引少数载流子远离源极区域2和漏极区域6的能力，这是由于沉降区域8邻近于源极区域2和漏极区域6。此外，据设想提供相应的源极沉降区域和漏极沉降区域用于源极区域2和漏极区域6可以另外增强沉降区域8吸引少数载流子远离源极区域2和漏极区域6的能力。
沉降区域8可以连接到的外部电势可以例如是接地电势。在装置包括例如图1中所示的NMOS晶体管的情况下，外部电势也可以是正电势，以用于吸引少数载流子(电子)。在替代地包括PMOS晶体管的例子中，外部电势可以是负电势，以用于吸引少数载流子(空穴)。在一些实施例中，沉降区域8可以连接到装置10的电源电压(在NMOS的情况下为正，在PMOS的情况下为负)。
在图1的例子中，沉降区域8位于第一半导体区域40连同源极区域2和漏极区域6中。然而，另外据设想沉降区域可以位于半导体区域40外部。其例子在图2中示出。
图2的实施例中所示的装置10在一些方面中类似于图1中所示的装置10，并且在下文中将仅详细描述差异。
图2中的装置包括第一半导体区域40，该第一半导体区域40可以包括掺杂为具有p型导电性的硅。在此例子中第一半导体区域40(以及下文描述的半导体区域60)由位于半导体衬底的主表面附近的硅的区域形成。每个半导体区域60可以掺杂为具有第二导电性类型，第二导电性类型在当前例子中是n型。应注意半导体区域60具有与第一半导体区域40相反的。在此例子中，第一半导体区域40位于埋入半导体层38的顶部上。层38是p型掺杂的，并且具有高于第一半导体区域40的掺杂水平。如已经相对于图1所描述，可以提供层38以减少NMOS装置内的泄漏电流。
在当前例子中，埋入半导体层38位于半导体衬底的下层部分36的顶部上。在此例子中形成埋入半导体层38的层还可以跨越衬底延伸。半导体区域60可以位于埋入半导体层58的顶部上，该埋入半导体层58可以掺杂为具有第二导电性类型(在当前例子中为n型)。据设想，可以省略层58。
如上文已经关于图1所描述，据设想在一些实施例中层38内的掺杂物水平可以降低，或者可以省略层38(在此情况下第一半导体区域40可以直接地位于半导体衬底的下层部分36上)。
第一半导体区域40可以通过类似于上文关于图1所述的隔离区域52的隔离区域52与半导体区域60分离。应注意，类似于图1的布置，半导体区域60电连接到半导体衬底的下层部分36。图2的例子还包括另外的隔离区域30(例如，浅沟槽隔离(shallow trenchisolation，STI))，在此例子中另外的隔离区域30分离形成于第一半导体区域40中的NMOS晶体管的特征与下文将描述的沉降区域8。同样，上文所述的种类的一个或多个金属间电介质层24、26、28可以提供在半导体衬底的主表面上。
在此例子中装置10包括源极区域2和漏极区域6，源极区域2和漏极区域6都位于第一半导体区域40内。在此例子中源极区域2和漏极区域6掺杂以具有n型导电性。源极区域2和漏极区域6通过栅极4分离。栅极4可以包括位于栅极电介质上的栅极电极，栅极电介质本身可以位于半导体衬底的主表面的部分上，该半导体衬底位于源极区域2与漏极区域6之间。将了解在此例子中通过源极区域2、漏极区域6和栅极4形成的晶体管是NMOS晶体管，然而如先前所提到，据设想本发明的实施例可以替代地包括PMOS晶体管。
触点12、16可以相应地提供到源极区域2和漏极区域6的电连接。类似触点可用于为栅极4(在图2中未示出)提供电连接。每个触点可以包括部分42，部分42向下延伸穿过金属间电介质层24、26、28以与源极区域2、漏极区域6和栅极4连接。
为了将电势施加到第一半导体区域40(其中NMOS晶体管的通道区域将在装置10的操作期间形成)，在此例子中可以提供一个或多个另外的半导体区域22。在此例子中另外的半导体区域22掺杂为具有p型导电性，并且通常可以具有高于半导体区域40的掺杂水平的掺杂水平。另外的半导体区域22可以配备有类似于上文相对于源极区域2和漏极区域6所述的触点12、16的触点32。与图1的例子一样，施加到触点32的电势可用于改变第一半导体区域40内的电势。然而，与图1的例子相反，在当前例子中，另外的半导体区域22位于第一半导体区域40中。在当前例子中，另外的半导体区域22的邻近可以增强施加到触点32的电势的能力以控制栅极4附近的第一半导体区域40内的电势。
位于第一半导体区域40中的每个另外的半导体区域22可以通过间隔物与源极区域或漏极区域分离。在当前例子中，另外的半导体区域22通过已经关于图1描述的种类的虚拟栅极20与源极区域2分离。如同图1中描述的间隔物，据设想其它种类的间隔物可以用于图2中，例如，位于第一半导体区域40中的隔离区域(例如，包含电介质的沟槽)。
在此实施例中装置10配备有至少一个沉降区域8。在此例子中每个沉降区域8掺杂为具有n型导电性。在形成PMOS晶体管的装置中，沉降区域可以替代地被掺杂为具有p型导电性。沉降区域8的掺杂水平(以及源极区域2和漏极区域6的掺杂水平)可以高于第一半导体区域40的掺杂水平(还应注意沉降区域8、源极区域2和漏极区域6各自具有不同于第一半导体区域40的导电性类型)。据设想沉降区域8可以使用与用于形成源极区域2和漏极区域6相同的处理步骤形成(例如，通过离子植入)。
每个沉降区域可以是可连接到外部电势的。举例来说，如图1所示，每个沉降区域8可以配备有触点18，触点18可以类似于上文关于图1所述的触点18。
当前例子包括两个沉降区域8。据设想可以提供单个沉降区域8(或大于两个沉降区域8)。在当前例子中，每个沉降区域8位于第一半导体区域40外部。如图2所示，每个沉降区域8可以位于半导体区域60中的一个中。如先前所提到，在此例子中，半导体区域60电连接到半导体衬底的下层部分36。相应地，施加到触点18的电势可用于吸引少数载流子远离位于如已经关于图1所描述的第一半导体区域40中的源极区域2和漏极区域4。同样，这可以允许在源极区域2和漏极区域6与第一半导体区域40之间的接合点处的泄漏电流减小。
如同同样关于图1所描述，沉降区域8可以连接到其上的外部电势可以例如是接地电势。在装置包括例如图2中所示的NMOS晶体管的情况下，外部电势也可以是正电势，以用于吸引少数载流子(电子)。在替代地包括PMOS晶体管的例子中，外部电势可以是负电势，以用于吸引少数载流子(空穴)。在一些实施例中，沉降区域8可以连接到装置10的电源电压(在NMOS的情况下为正，在PMOS的情况下为负)。
在图1的例子中，沉降区域8位于半导体区域40连同源极区域2和漏极区域6中，而在图2的例子中，沉降区域8位于第一半导体区域40外部。据设想混合方法可以用于一些实施例中，其中一个或多个沉降区域8位于第一半导体区域40中(例如，如图1所示)并且其中一个或多个沉降区域8位于第一半导体区域40外部(例如，如图2所示)。类似地，据设想在一些例子中例如图1和2中所示的另外的半导体区域22的另外的半导体区域可以提供在第一半导体区域40中(例如，如图1所示)和第一半导体区域40外部(例如，如图2所示)。
制造本文中描述的种类的半导体射频切换装置的方法可以包括提供具有第一的第一半导体区域。第一区域可以例如通过掺杂(例如，通过离子植入)位于半导体衬底的主表面处的半导体层的部分而形成。衬底可以例如是块状硅晶片，然而另外设想出可以使用如先前所提到的SOI晶片。
在图1和2中所示的种类的实施例中，可以选择用于形成第一半导体区域的掺杂物使得第一导电性类型通常是p型，但不限于，硼或铟(使得源极和漏极以及栅极在第一半导体区域中形成NMOS晶体管)。在其它例子中，可以选择用于形成第一半导体区域的掺杂物使得第一导电性类型通常是n型，但不限于，砷或磷(使得源极和漏极以及栅极在第一半导体区域中形成PMOS晶体管)。
该方法还包括形成栅极。栅极可以包括位于栅极电介质上的栅极电极，该栅极电介质位于衬底的主表面上。可以使用标准光刻技术将电介质和栅极电极图案化成所选择的尺寸。该方法另外包括形成位于第一半导体区域中的源极区域和漏极区域。源极区域和漏极区域可以通过使用离子植入形成。在成品装置中，栅极位于源极区域与漏极区域之间。据设想栅极可以在源极区域和漏极区域已经形成之前或之后形成。源极区域和漏极区域具有不同于第一导电性类型的第二导电性类型(可以相应地选择用于形成这些区域的掺杂物(例如，砷和/或磷用于n型掺杂并且例如，硼用于p型掺杂))。因此，源极区域和漏极区域各自具有与第一半导体区域不同的导电性类型。
该方法还包括形成具有第二导电性类型的至少一个沉降区域。同样，这些沉降区域可以使用例如离子植入形成，并且可以根据第一导电性类型是否是n型或p型(例如，砷和/或磷或锑用于n型掺杂并且例如，硼或铟用于p型掺杂)来选择掺杂物。沉降区域可以形成在第一半导体区域内部(例如，按照图1)或第一半导体区域外部(例如，按照图2)。如已经描述的，在成品装置中，每个沉降区域可以连接到外部电势以用于吸引少数载流子远离源极区域和漏极区域以减少源极区域和漏极区域与第一半导体区域之间的接合点处的泄漏电流。
在一些例子中，关于图1和2描述的种类的另外的半导体区域可以形成为(同样使用例如离子植入)为施加电势到第一半导体区域。
在上述特征形成之后，一个或多个保护层(例如，关于图1和2描述的金属间电介质层24、26、28)可以沉积在半导体衬底的主表面上。
装置的特征，例如，源极区域、漏极区域、栅极、沉降区域以及另外的半导体区域可以配备有触点，例如上文关于图1和2所述的那些触点。触点可以例如是金属的。触点可以使用标准沉积和图案化步骤形成。
如已经关于图1和2所描述，存在用于沉降区域以及另外的半导体区域的放置的多个选项。在上文提到的种类的一个或多个沉降区域和/或另外的半导体区域位于第一半导体区域外部的情况下，该方法包括形成隔离区域，例如，上文所述的沟槽。标准制造技术可用于形成这些隔离区域。
相应地，已经描述了用于切换射频信号的半导体切换装置以及用于制造该半导体切换装置的方法。该装置包括具有第一导电性类型的第一半导体区域。该装置还包括位于第一半导体区域中的源极区域和漏极区域。源极区域和漏极区域具有第二导电性类型。第二导电性类型不同于第一导电性类型。该装置另外包括分离源极区域与漏极区域的栅极。该装置还包括具有第二导电性类型的至少一个沉降区域。每个沉降区域可连接到外部电势以用于吸引少数载流子远离源极区域和漏极区域以减少在源极区域和漏极区域与第一半导体区域之间的接合点处的泄漏电流。
尽管已经描述了本发明的特定实施例，但是应了解，可以在权利要求书的范围内作出许多修改/添加和/或替代。

Claims (10)

1.一种用于切换射频信号的半导体切换装置，其特征在于，所述装置包括：
第一半导体区域，所述第一半导体区域具有第一导电性类型；
位于所述第一半导体区域中的源极区域和漏极区域，其中所述源极区域和所述漏极区域具有第二导电性类型，其中所述第二导电性类型不同于所述第一导电性类型；
栅极，所述栅极分离所述源极区域与所述漏极区域；以及
至少一个沉降区域，所述至少一个沉降区域具有所述第二导电性类型，其中每个沉降区域可连接到外部电势以用于吸引少数载流子远离所述源极区域和漏极区域以减少在所述源极区域和漏极区域与所述第一半导体区域之间的接合点处的泄漏电流。
2.根据权利要求1所述的装置，其特征在于，所述至少一个沉降区域中的至少一个位于具有所述源极区域和漏极区域的所述第一半导体区域中。
3.根据权利要求2所述的装置，其特征在于，所述第一半导体区域中的至少一个沉降区域通过间隔物与所述源极区域或所述漏极区域分离。
4.根据权利要求3所述的装置，其特征在于，所述间隔物包括位于所述第一半导体区域中的隔离区域。
5.根据权利要求3所述的装置，其特征在于，所述间隔物包括虚拟栅极。
6.根据权利要求2到5中任一权利要求所述的装置，其特征在于，所述沉降区域中的一个是位于所述第一半导体区域中的所述源极区域附近的源极沉降区域并且其中所述沉降区域中的一个是位于所述第一半导体区域中的所述漏极区域附近的漏极沉降区域。
7.根据在前的任一项权利要求所述的装置，其特征在于，所述至少一个沉降区域中的至少一个位于所述第一半导体区域外部并且电连接到所述装置的下层衬底区域。
8.根据权利要求7所述的装置，其特征在于，位于所述第一半导体区域外部的至少一个沉降区域位于通过隔离区域与所述第一半导体区域分离的半导体区域中。
9.根据在前的任一项权利要求所述的装置，其特征在于，包括具有所述第一导电性类型的至少一个另外的半导体区域，其中所述至少一个另外的半导体区域可连接到外部电势以用于将所述电势施加到所述第一半导体区域。
10.一种制造用于切换射频信号的半导体切换装置的方法，其特征在于，所述方法包括：
提供具有第一导电性类型的第一半导体区域；
形成栅极；
形成位于所述第一半导体区域中的源极区域和漏极区域，其中所述源极区域和所述漏极区域具有第二导电性类型，其中所述第二导电性类型不同于所述第一导电性类型，其中所述栅极分离所述源极区域与所述漏极区域；以及
形成具有所述第二导电性类型的至少一个沉降区域，其中每个沉降区域可连接到外部电势以用于吸引少数载流子远离所述源极区域和漏极区域以减少所述源极区域和漏极区域与所述第一半导体区域之间的接合点处的泄漏电流。
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