CN107015891B - Information processing method and test chip - Google Patents
Information processing method and test chip Download PDFInfo
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- CN107015891B CN107015891B CN201710121712.2A CN201710121712A CN107015891B CN 107015891 B CN107015891 B CN 107015891B CN 201710121712 A CN201710121712 A CN 201710121712A CN 107015891 B CN107015891 B CN 107015891B
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2205—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested
- G06F11/2236—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing using arrangements specific to the hardware being tested to test CPU or processors
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]
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Abstract
The embodiment of the invention discloses an information processing method and a test chip, wherein the method comprises the following steps: determining the current working frequency and the current working voltage of a single chip to be tested; performing a pressure test on the chip to be tested which works by using the current working frequency and the current working voltage; when the tested chip passes the pressure test, increasing the current working frequency and returning to the pressure test of the tested chip; when the tested chip fails the pressure test, increasing the current working voltage; and returning to the pressure test of the tested chip when the increased current working voltage is not more than the maximum working voltage supported by the tested chip, otherwise determining the maximum working frequency supported by the tested chip according to the working frequency corresponding to the pressure test passed by the tested chip.
Description
Technical Field
The present invention relates to the field of electronic technologies, and in particular, to an information processing method and a test chip.
Background
The operating frequency of a chip, such as a Central Processing Unit (CPU), determines the response rate of the chip. Typically, the chip has a nominal frequency at which it is most suitable to operate, and in some cases the chip may operate in an over-frequency condition. When the chip works in an overclocking state, the working frequency of the chip is higher than the rated frequency, and at the moment, the response speed of the chip is further improved. But the maximum working frequency that the chip can support is the highest working frequency of the over-frequency state. In the prior art, the highest supportable operating frequency of a chip is determined based on an Over Clock (OC) test. In the prior art, the OC test is to perform batch test on a plurality of devices, and a tester inputs a working frequency for testing the plurality of devices, and when one of the devices does not support the working frequency, the tester correspondingly adjusts the input working frequency, and repeatedly tests to obtain a working frequency supported by the group of devices, which is used as the highest working frequency supported by all the devices in the group of devices. However, in practice, the performance of chips of different devices is different, and the highest operation frequency that can be supported by the device obtained by the OC test method often cannot reflect the performance of the device itself, and further, the device cannot exhibit the performance of the device itself to the maximum extent once it is put into use. Therefore, how to improve the accuracy of the OC test and how to determine the highest operating frequency supported by a single device in the over-frequency state through the OC test is a problem to be solved urgently in the prior art.
Disclosure of Invention
In view of the above, it is desirable to provide an information processing method and a test chip, which at least partially solve the above problems.
In order to achieve the purpose, the technical scheme of the invention is realized as follows:
a first aspect of an embodiment of the present invention provides an information processing method, including:
determining the current working frequency and the current working voltage of a single chip to be tested;
performing a pressure test on the chip to be tested which works by using the current working frequency and the current working voltage;
when the tested chip passes the pressure test, increasing the current working frequency and returning to the pressure test of the tested chip;
when the tested chip fails the pressure test, increasing the current working voltage;
and returning to the pressure test of the tested chip when the increased current working voltage is not more than the maximum working voltage supported by the tested chip, otherwise determining the maximum working frequency supported by the tested chip according to the working frequency corresponding to the pressure test passed by the tested chip.
Based on the above scheme, the increasing the current operating frequency further includes:
increasing the frequency multiplication parameter according to a first preset step length;
inputting the increased frequency multiplication parameters into the chip to be tested; and the frequency multiplication parameter is used for carrying out frequency multiplication processing on the chip to be tested on the basis of the frequency basic value.
Based on the above scheme, the method further comprises:
reading a first register representing whether the tested chip is normal in the pressure test by a test chip;
and when the value read from the first register by the test chip is the first value, the test chip determines that the chip to be tested passes the pressure test.
Based on the above scheme, the increasing the current operating frequency includes:
when the number of the pressure tests applied to the tested chip is less than a preset number, increasing the current working frequency by a first amplitude;
when the number of the pressure tests applied to the tested chip is not less than the preset number, increasing the current working frequency by a second amplitude; wherein the first amplitude is greater than the second amplitude.
Based on the above scheme, the method further comprises:
when the current working voltage of the tested chip reaches the maximum working voltage and does not pass the pressure test, reducing the current working frequency and returning to the pressure test of the tested chip, wherein the reduced current working voltage is greater than the working frequency corresponding to the pressure test which is passed by the tested chip for the previous time and is less than the working frequency corresponding to the pressure test.
A second aspect of the embodiments of the present invention provides a test chip, including a test chip, where the test chip includes:
the first determining unit is used for determining the current working frequency and the current working voltage of the single chip to be tested;
the test unit is used for carrying out pressure test on the chip to be tested which works by using the current working frequency and the current working voltage;
the adjusting unit is used for increasing the current working frequency and returning to the pressure test of the tested chip when the tested chip passes the pressure test; when the tested chip fails the pressure test, increasing the current working voltage;
and the second determining unit is used for returning to the pressure test of the tested chip when the increased current working voltage is not more than the maximum working voltage supported by the tested chip, otherwise, determining the maximum working frequency supported by the tested chip according to the working frequency corresponding to the pressure test passed by the tested chip.
Based on the above scheme, the adjusting unit is specifically configured to increase the frequency multiplication parameter according to a first preset step length; inputting the increased frequency multiplication parameters into the chip to be tested; and the frequency multiplication parameter is used for carrying out frequency multiplication processing on the chip to be tested on the basis of the frequency basic value.
Based on the above scheme, the test chip further comprises:
the reading unit is specifically used for reading a first register which represents whether the pressure test of the tested chip is normal or not;
and the third determining unit is used for determining that the chip to be tested passes the pressure test when the value read from the first register by the test chip is the first value.
Based on the above scheme, the adjusting unit is specifically configured to increase the current operating frequency by a first amplitude when the number of times of the pressure test applied to the chip under test is less than a preset number of times; when the number of the pressure tests applied to the tested chip is not less than the preset number, increasing the current working frequency by a second amplitude; wherein the first amplitude is greater than the second amplitude.
Based on the above scheme, the adjustment unit is further configured to reduce the current operating frequency and return to the pressure test of the chip to be tested when the current operating voltage of the chip to be tested has reached the maximum operating voltage and does not pass the pressure test of this time, wherein the reduced current operating voltage is greater than the operating frequency corresponding to the pressure test and less than the operating frequency corresponding to the pressure test of this time, which is passed by the chip before.
According to the information processing method and the test chip provided by the embodiment of the invention, when the maximum working frequency supported by the tested chip is positioned, the determined current working frequency and the determined current working voltage are both specific to the single tested chip, and whether the single tested chip passes the pressure test result is detected, so that the test chip is utilized to perform single test on the tested chip in the embodiment, obviously, the maximum working frequency of the tested chip can be accurately positioned based on the self performance of the tested chip, the determination accuracy of the ultra-frequency screen frequency of the chip is improved, and meanwhile, the performance of the chip is utilized with the maximum efficiency.
Drawings
Fig. 1 is a schematic flowchart of a first information processing method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating a second information processing method according to an embodiment of the present invention;
FIG. 3 is a schematic structural diagram of a test chip according to an embodiment of the present invention;
FIG. 4 is a flowchart illustrating a third information processing method according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a device under test according to an embodiment of the present invention.
Detailed Description
The technical solution of the present invention is further described in detail with reference to the drawings and the specific embodiments of the specification.
As shown in fig. 1, the present embodiment provides an information processing method including:
step S110: determining the current working frequency and the current working voltage of a single chip to be tested;
step S120: performing a pressure test on the chip to be tested which works by using the current working frequency and the current working voltage;
step S130: when the tested chip passes the pressure test, increasing the current working frequency, and returning to the step S120;
step S140: when the tested chip fails the pressure test, increasing the current working voltage;
step S151: returning to the step S120 when the increased current operating voltage is not greater than the maximum operating voltage supported by the chip under test,
step S152: and when the increased current working voltage is greater than the maximum working voltage supported by the tested chip, determining the maximum working frequency supported by the tested chip according to the working frequency corresponding to the pressure test passed by the tested chip.
The information processing method described in this embodiment may be a method applied to a test chip. The test chip herein includes a test chip. The test chip here may be an over-frequency test chip, which may also be referred to as an OC integrated circuit IC. Of course, in a specific implementation, the test chip may be other processing chips capable of performing a stress test, besides the OC IC dedicated to performing the turbo test. For example, when the chip under test is a north bridge chip of the device under test, the test chip may be a south bridge chip within the device under test. Therefore, the test chip can be a test chip dedicated to the OC test or a non-dedicated test chip integrated with other functions.
The chip under test may be a CPU chip, an image processor GPU chip, a DSP chip or an AP chip, and in short, the chip under test may be various types of chips.
In step S110, the test chip determines the current operating frequency and the current operating voltage of the single chip under test. In this embodiment, the test chip determines the current operating frequency and the current operating voltage, which are only for one chip under test, not for a plurality of chips under test.
The current operating frequency is a clock frequency of the chip under test, and the current operating voltage may be a voltage value input to the chip under test.
In the initial stage of testing, the current operating frequency is usually the nominal frequency of the chip under test plus a frequency offset value. And the current working voltage is the rated voltage of the tested chip. In this way, the information processing method provided by this embodiment directly measures the maximum work that can be made by the chip under test
Once the current operating frequency and the current operating voltage of the chip under test are determined, the test chip sends test instructions to the chip under test, where the test instructions can be used to initiate a stress test. The test command may carry command parameters that may be used to indicate the current operating frequency and current operating voltage.
And after receiving the test instruction, the tested chip enters a pressure test. The pressure test may be a test item pre-designed in the chip under test, in which the chip under test operates at the current operating frequency and the current operating voltage during the test process, and then performs functions or operations in the test item. And if the phenomena of error reporting, downtime and the like do not occur in the process of executing the test items by the tested chip, the pressure test can be considered to be passed, otherwise, the pressure test can be considered not to be passed.
Typically, the stress test also includes a test time, which may be a longer time period. For example, the pressure test time is 24 hours or 48 hours. The test items can be continuously executed for various functions in the tested equipment, and whether various abnormal phenomena such as error reporting, overload or overhigh temperature and the like which should not occur exist when the tested chip executes the functions is detected. Detecting whether a preset abnormal phenomenon occurs to the chip to be tested in the pressure testing process, if the preset abnormal phenomenon does not occur to the chip to be tested in the testing time, passing the pressure testing, once the abnormal phenomenon is detected, determining that the pressure testing does not pass, finishing the pressure testing, and entering the next step to reduce the unnecessary pressure testing process.
In the process of performing the pressure test, the test chip may monitor a state parameter of the chip under test in the pressure test process, for example, detect a temperature of the chip under test, and determine whether there is a problem of an excessively high temperature according to the detected temperature, for example, it may be determined that the pressure test is failed when the detected temperature is higher than a temperature threshold.
In step S130, when the chip under test passes the pressure test, it indicates that the chip under test supports the current operating frequency, and the chip under test may support an operating frequency higher than the current operating frequency, so the current operating frequency is increased. Equivalently, the working frequency of the chip to be tested is adjusted again, after the working frequency of the chip to be tested is adjusted, the step S120 is returned again, and the chip to be tested is subjected to the pressure test to determine whether the chip to be tested is abnormal when working at the adjusted working frequency, and the process is repeated until the maximum working frequency which can be made by the chip to be tested is found.
In this embodiment, if the chip under test fails the pressure test, the reasons for the chip under test failing the pressure test can be divided into two categories, the first category is that the operating frequency of the chip under test is actually too high, and the second category is that the operating voltage of the chip under test does not support such a high operating frequency. To exclude the second type of causes. In this embodiment, the current operating voltage of the chip under test is increased. However, in order to prevent the damage problem that the working voltage applied to the chip to be tested is too high, which may cause the chip to be tested to be broken down, in this embodiment, the increased current working voltage is compared with the maximum working voltage supported by the chip to be tested, and if the increased current working voltage is greater than the maximum working voltage, the increased current working voltage may not be applied to the chip to be tested to operate, otherwise, the chip to be tested may be damaged. Meanwhile, because the corresponding current working voltage is close to the maximum working voltage or equal to the maximum working voltage during the previous pressure test, the tested chip still does not pass the pressure test, the reason that the working voltage causes the tested chip to fail the pressure test can be eliminated, and the fact that the tested chip fails the pressure test due to the fact that the working frequency of the tested chip is too high can be determined. Therefore, at this time, the maximum working frequency supported by the chip to be tested can be determined according to the working frequency corresponding to the pressure test passed by the chip to be tested in the test process, and the maximum working frequency can be the over-frequency of the chip to be tested.
In a specific implementation process, in the step S150, if the increased current working voltage is greater than the maximum working voltage and the current working voltage before the increase is less than the maximum working voltage, the current working voltage is adjusted again to make the adjusted current working voltage equal to the maximum working voltage of the chip to be tested, and the pressure test on the chip to be tested is returned.
In step S150, if the current operating frequency is adjusted in a gradually increasing manner, when the maximum operating frequency is determined, it is determined that the operating frequency corresponding to the last time pressure test of the chip under test is the maximum operating frequency supported by the chip under test.
Therefore, in this embodiment, a method for non-batch testing of chips under test is provided, and the maximum operating frequency supported by each chip under test can be accurately determined by repeatedly adjusting the current operating frequency and the current operating voltage during the testing process. Therefore, the overclocking frequency of different tested chips can be recorded according to different performances of the different tested chips, so that the overclocking frequency recorded by the different tested chips is different, and the subsequent tested chips can work at different maximum working frequencies after being put into use, thereby fully playing the performance of each chip.
In some embodiments, the step S130 may further include:
increasing the frequency multiplication parameter according to a first preset step length;
inputting the increased frequency multiplication parameters into the chip to be tested; and the frequency multiplication parameter is used for carrying out frequency multiplication processing on the chip to be tested on the basis of the frequency basic value.
And increasing the current working frequency to directly output a frequency value corresponding to the current working frequency to the tested chip. In this embodiment, the frequency multiplication parameter is substantially adjusted. For example, if the frequency multiplication parameter is Rn and the frequency base value of the chip under test is F, the chip under test will operate at Rn × F after receiving the frequency multiplication parameter. In this way, obviously, the effect of increasing the current working frequency of the chip to be tested is achieved simply and conveniently by increasing the frequency doubling parameter. Therefore, if the test chip sends the test instruction to the tested chip, the parameter related to the current working frequency carried by the test instruction may be the frequency multiplication parameter, or may be a frequency value of the current working frequency or other indication information indirectly indicating the current working frequency.
In some embodiments, the method further comprises:
reading a first register representing whether the tested chip is normal in the pressure test by a test chip;
and when the value read from the first register by the test chip is the first value, the test chip determines that the chip to be tested passes the pressure test.
In this embodiment, the first register may be a component of the tested chip, the first register may also be a component of the testing chip, and of course, the first register may also be a register which is independent of the tested chip and the testing chip at the same time, but is connected to the tested chip and the testing chip respectively. The first register may be used to store values that characterize the results of the stress test. The first register comprises one or more bit identification bits, when the tested chip passes the pressure test, the identification bits are a first value, otherwise, the identification bits are a second value.
For example, when the tested chip is not abnormal during the pressure test, a first value is written into the first register when the pressure test is finished. In this way, the chip under test is monitored by time, and the first register is read when the chip under test is found to be finished with the pressure test. If the test chip reads the first value, the tested chip can be directly considered to pass the pressure test. If the tested chip is abnormal in the pressure testing process, the tested chip has no ability to set the value of the first accumulator as the first value, or the value of the first register is not set as the first value.
In this embodiment, there are various ways for the chip under test to set the first register to the first value, including writing the first value into the first register. When the first value is 0, the chip to be tested can also set the first register to be the first value by emptying the first register.
In this embodiment, if the test chip is a Platform Controller Hub (PCH), the first register may be a component of the test chip, and the first register may specifically be a PCH-OC-WDT register. The PCH-OC-WDT register is a register of a stress test-watchdog timer of the PCH. The PCH-OC-WDT is an abbreviation of Platform Controller Hub-Over Clock-Watch Dog Timer. In this embodiment, the first register directly multiplexes the existing register of the test chip, and a special register is not required, thereby reducing the test cost. In this embodiment, the PCH will be set to 1 in the PCH-OC-WDT register before the pressure test, so that the value of the PCH-OC-WDT register can be adjusted by the chip under test according to the result of the pressure test. Certainly, the PCH may periodically adjust a value in the CH-OC-WDT register according to its own state, and in order to avoid that the PCH needs to specially adjust the value of the CH-OC-WDT register before the pressure test time of the chip to be tested, in this embodiment, the test time of the pressure test may be set to be N times the period in which the PCH updates the CH-OC-WDT register. And the CH-OC-WDT register is set as a second value under the normal condition of the PCH, and the second value is different from the first value. Further, the starting time of the pressure test and the starting time of the period of the PCH-OC-WDT register update do not coincide, and the starting time of the pressure test is slightly later than the starting time of one period of the PCH-OC-WDT register update, but the later time does not exceed one period of the PCH-OC-WDT register update.
In some embodiments said increasing said current operating frequency comprises:
when the number of the pressure tests applied to the tested chip is less than a preset number, increasing the current working frequency by a first amplitude;
when the number of the pressure tests applied to the tested chip is not less than the preset number, increasing the current working frequency by a second amplitude; wherein the first amplitude is greater than the second amplitude.
When the pressure test is carried out, the current working frequency of the tested chip is gradually increased. Obviously, when the test is started, the current working frequency of the tested chip is far away from the maximum working frequency supported by the tested chip, in order to reduce the times of the pressure test, the current working frequency can be increased by an increased amplitude in the starting stage, after the test is carried out by a plurality of times of pressure tests, the current working frequency of the tested chip is increased for a plurality of times relative to the rated frequency, the current working frequency is close to the maximum working frequency supported by the tested chip, if the current working frequency is increased by a large amplitude, the phenomenon that the pressure test cannot pass can occur after the current working frequency is increased once, and therefore, after the test is carried out by the pressure test, the current working frequency is increased by a small amplitude. On one hand, the frequency of pressure test or whole OC test is reduced, and on the other hand, the maximum working frequency supported by the tested chip can be accurately positioned. The whole flow from step S110 to step S150 in this embodiment may be referred to as OC test.
In this embodiment, the first amplitude may include one or more first adjustment step values, and the second amplitude may also include one or more second adjustment step values. All first adjustment step values are greater than the second adjustment step value. Of course, two different calculation methods may be used when increasing the current operating frequency. And when the first amplitude is adopted, calculating by adopting a first calculation mode to obtain the increased current working frequency, and when the second amplitude is adopted, calculating by adopting a second calculation mode to obtain the increased current working frequency. And calculating by adopting two calculation modes, so that the adjustment amplitude of the increased current working frequency is different from that of the current working frequency before the increase.
In some embodiments, as shown in fig. 2, the method further comprises:
step S153: and when the current working voltage of the tested chip reaches the maximum working voltage and does not pass the current pressure test, reducing the current working frequency and returning to the step S120, wherein the reduced current working voltage is greater than the working frequency corresponding to the previous pressure test of the tested chip and is less than the working frequency corresponding to the current pressure test.
If the current working frequency is gradually increased from the rated frequency of the tested chip, when the current working frequency is increased to a certain working frequency, the tested chip does not support the working frequency, so that the maximum working frequency which can be supported by the tested chip can be determined to be located between the working frequency and the working frequency corresponding to the pressure test which is passed by the tested chip in the previous time. In this embodiment, in order to accurately locate the maximum operating frequency supported by the chip under test, in this embodiment, the current operating frequency is reduced, and the chip under test is subjected to the stress test at the reduced current operating frequency again.
In this embodiment, the reduced current operating frequency may be a median or a mean of the increased current operating frequency and an operating frequency corresponding to a pressure test of a previous pass.
Of course, scaling down the current operating frequency may include in some embodiments: reducing the current operating frequency by a preset magnitude. The preset amplitude here corresponds directly to an adjustment step value, which is smaller than the difference between the current operating frequency before the reduction and the operating frequency corresponding to the previously passed pressure test.
For example, assume that increasing the current operating frequency by a first magnitude is a first adjustment phase and increasing the current operating frequency by a second magnitude is a second adjustment phase. When the failure of the pressure test occurs in the first adjustment phase, the step 151 may include:
reducing the current working frequency by a third amplitude and returning to the pressure test of the tested chip; wherein the third amplitude is equal to or greater than the second amplitude.
In this embodiment, an approximate range of the maximum operating voltage supported by the chip to be tested is first located in a stepwise increasing manner, and then the maximum operating frequency supported by the chip to be tested can be accurately located by readjusting (e.g., fine tuning) within the approximate range, so that the over-frequency of the chip to be tested is accurately located.
In a specific implementation process, the test chip or the tested chip further forms an OC test record according to the test parameters and the test result. The test parameters include the current operating frequency and the current operating voltage of each, and the test result may be the final result of the stress test and/or the test result of each item in the stress test process.
Further, the method may further include:
outputting the OC test record. Through the output of OC test record, make things convenient for fault analysis chip or tester to fix a position the trouble or know the maximum operating frequency of the chip that is surveyed.
In some embodiments, the method further comprises:
once the maximum working frequency of the tested chip is determined, the indication parameter of the maximum working frequency is written in a preset memory of the tested chip, so that the over-frequency in the over-frequency state can be determined according to the indication parameter after the tested chip is put into use. Therefore, manual writing by testers is not needed, and full automation of OC test and maximum working frequency writing is realized.
As shown in fig. 3, the present embodiment provides a test chip, which includes a test chip, where the test chip includes:
a first determining unit 110 for determining a current operating frequency and a current operating voltage of a single chip under test;
the test unit 120 is configured to perform a pressure test on the chip under test that operates with the current operating frequency and the current operating voltage;
the adjusting unit 130 is used for increasing the current working frequency and returning to the pressure test of the tested chip when the tested chip passes the pressure test; when the tested chip fails the pressure test, increasing the current working voltage;
a second determining unit 140, configured to return to the pressure test on the chip to be tested when the increased current working voltage is not greater than the maximum working voltage supported by the chip to be tested, and otherwise determine the maximum working frequency supported by the chip to be tested according to a working frequency corresponding to the pressure test that the chip to be tested passes through.
The embodiment provides a test chip, which can be a special OC test chip. In this embodiment, the test chip may also be a different processing chip of the device under test than the chip under test. For example, a tested chip in a device under test is a CPU, and a PCH in the device under test can be used as the test chip.
In this embodiment, the first determining unit 110, the testing unit 120, the adjusting unit 130, and the second determining unit 140 may all correspond to an integrated circuit in a test chip, and the like, which may implement the operation of the above functional units through execution of predetermined codes.
In this embodiment, a test apparatus is further provided, and the test apparatus includes the test chip and a support structure of the test chip. The support structure may comprise a housing or a support plate; the test chip may be mounted on the support structure. The support plate may be a printed circuit board or the like.
The test chip is arranged in the shell and is connected with the test chip through an opening on the shell or connected with the test chip through a connecting path on the printed circuit board.
In the embodiment, the current working frequency and the current working voltage determined by the test chip are specific to a single chip to be tested, and the current working frequency is only performed according to the self pressure test result of the single chip to be tested in the whole OC test process, so that the maximum working frequency of the chip to be tested can be accurately obtained, and the accurate determination of the maximum working frequency of the single chip to be tested is realized.
In some embodiments, the adjusting unit 130 is specifically configured to increase the frequency multiplication parameter according to a first preset step length; inputting the increased frequency multiplication parameters into the chip to be tested; and the frequency multiplication parameter is used for carrying out frequency multiplication processing on the chip to be tested on the basis of the frequency basic value.
In some embodiments, the test chip further comprises:
the reading unit is specifically used for reading a first register which represents whether the pressure test of the tested chip is normal or not;
and the third determining unit is used for determining that the chip to be tested passes the pressure test when the value read from the first register by the test chip is the first value.
The test chip in this embodiment further includes a reading unit and a third determining unit, where the reading unit and the third determining unit may also correspond to the integrated circuit in the test chip. The test chip may read the first register through the reading unit, and the third determining unit determines whether the chip under test passes the stress test according to a value read from the first register. In this embodiment, the first register may be a register carried by the chip under test itself and having other functions. For example, when the test chip is a PCH, the first register may be a PCH-OC-WDT register.
In some embodiments, the adjusting unit 130 is specifically configured to increase the current operating frequency by a first amplitude when the number of the pressure tests applied to the chip under test is less than a preset number; when the number of the pressure tests applied to the tested chip is not less than the preset number, increasing the current working frequency by a second amplitude; wherein the first amplitude is greater than the second amplitude.
In this embodiment, the adjusting unit 130 may include a counter, where the counter may record the number of times that the tested chip has undergone the pressure test in the OC test process, and if the number of times is smaller, the current operating frequency may be increased by a larger amplitude, otherwise, the current operating frequency may be increased by a smaller amplitude, so that the number of times of the pressure test in the OC test process may be reduced, and the OC test efficiency may be improved.
In some embodiments, the adjusting unit 130 is further configured to reduce the current operating frequency and return to the pressure test on the chip to be tested when the current operating voltage of the chip to be tested has reached the maximum operating voltage and fails the pressure test of this time, where the reduced current operating voltage is greater than the operating frequency corresponding to the pressure test that the chip to be tested has passed last time and is less than the operating frequency corresponding to the pressure test of this time.
In this embodiment, the adjusting unit 130 can not only increase the current working voltage in the forward direction, but also decrease the current working voltage in the reverse direction when appropriate, so as to accurately locate the maximum working frequency supported by the current chip to be tested, and increase the over-frequency of the maximum working frequency of the single chip to be tested.
One specific example is provided below in connection with any of the embodiments described above:
as shown in fig. 4, this example takes a CPU as an example, and provides an over-frequency positioning method based on any of the above embodiments, including:
step 1: entering an OC test mode of the CPU;
step 2: the OC IC sets the current working voltage Vp of the CPU; when the OC IC sets the Vp for the first time, the current working voltage of the CPU can be set by using a formula Vp + Voffset, wherein Vp is the current working voltage, and Vcpu is the rated voltage of the CPU; the Voffset is a voltage offset value;
and step 3: the OC IC sets the current frequency multiplication parameter Rn;
and 4, step 4: the CPU performs a stress test, which may specifically include: and the CPU determines the current working frequency and the current working voltage to enter a working state based on the frequency multiplication parameters and performs pressure test.
And 5: and (3) judging the value of the PCH-OC-WDT identification bit, entering the step 6 when the value is 1, obtaining the current frequency multiplication parameter by using a formula Rn ═ Rn + b when the value is 0, and returning to the step 3. And b is the frequency multiplication parameter increasing step length, and the value can be 0.5, 1 or 2 and the like. The PCH-OC-WDT flag is used to indicate whether the CPU passes the stress test at the current operating frequency and the current operating voltage.
Step 6: the OC IC triggers the global reset of the CPU; the global recovery here includes: the current operating voltage of the chip under test (referred to as CPU in this example) is restored to the initial operating voltage of the OC test, e.g., the rated voltage. The current operating frequency is restored to the original operating frequency, e.g., the nominal frequency.
And 7: determining the current working voltage of the CPU by using the formula Vp + Vstep, wherein the Vstep is the increasing step of the current working voltage;
and 8: judging whether VP is smaller than Vcpumax, wherein Vcpumax is the maximum working voltage supported by the CPU; if yes, returning to the step 2, and if not, entering the step 9;
and step 9: and exiting the OC test and generating an OC test file of the CPU, wherein various OC test records generated by the OC test are included in the OC test file.
Step 10: applying the OC test file.
FIG. 5 shows a device under test including a CPU and a PCH; wherein the PCH comprises an integrated circuit and a PCH-OC-WDT register. The CPU is a tested chip, the PCH is a testing chip, and the PCH-OC-WDT register is a register for storing a PCH-OC-WDT identification bit. The tested equipment can adopt the steps 1 to 10 to carry out OC test, so that the tested equipment can utilize the structure of the tested equipment to realize the accurate positioning of the over-frequency of the CPU, and simultaneously has the characteristic of simplicity in realization.
After the above example is performed, the following technical effects can be obtained:
1) the OC IC automatically carries out OC test and corrects parameters;
2) customizing the frequency and voltage of CPU overclocking;
3) the CPU over-frequency capability is explored to the maximum extent;
4) the CPU overclocking performance is maximized, and the user experience is improved.
In the several embodiments provided in the present application, it should be understood that the disclosed apparatus and method may be implemented in other ways. The above-described device embodiments are merely illustrative, for example, the division of the unit is only a logical functional division, and there may be other division ways in actual implementation, such as: multiple units or components may be combined, or may be integrated into another system, or some features may be omitted, or not implemented. In addition, the coupling, direct coupling or communication connection between the components shown or discussed may be through some interfaces, and the indirect coupling or communication connection between the devices or units may be electrical, mechanical or other forms.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, that is, may be located in one place, or may be distributed on a plurality of network units; some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, all the functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may be separately used as one unit, or two or more units may be integrated into one unit; the integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
Those of ordinary skill in the art will understand that: all or part of the steps for implementing the method embodiments may be implemented by hardware related to program instructions, and the program may be stored in a computer readable storage medium, and when executed, the program performs the steps including the method embodiments; and the aforementioned storage medium includes: a mobile storage device, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the appended claims.
Claims (10)
1. An information processing method characterized by comprising:
determining the current working frequency and the current working voltage of a single chip to be tested;
performing a pressure test on the chip to be tested which works by using the current working frequency and the current working voltage;
when the tested chip passes the pressure test, increasing the current working frequency and returning to the pressure test of the tested chip;
when the tested chip fails the pressure test, increasing the current working voltage;
and returning to the pressure test of the tested chip when the increased current working voltage is not more than the maximum working voltage supported by the tested chip, otherwise determining the maximum working frequency supported by the tested chip according to the working frequency corresponding to the pressure test passed by the tested chip.
2. The method of claim 1,
the increasing the current operating frequency further comprises:
increasing the frequency multiplication parameter according to a first preset step length;
inputting the increased frequency multiplication parameters into the chip to be tested; and the frequency multiplication parameter is used for carrying out frequency multiplication processing on the chip to be tested on the basis of the frequency basic value.
3. The method of claim 1,
the method further comprises the following steps:
reading a first register representing whether the tested chip is normal in the pressure test by a test chip;
and when the value read by the test chip from the first register is a first value, the test chip determines that the tested chip passes the pressure test.
4. The method of claim 1, 2 or 3,
the increasing the current operating frequency includes:
when the number of the pressure tests applied to the tested chip is less than a preset number, increasing the current working frequency by a first amplitude;
when the number of the pressure tests applied to the tested chip is not less than the preset number, increasing the current working frequency by a second amplitude; wherein the first amplitude is greater than the second amplitude.
5. The method of claim 1, 2 or 3,
the method further comprises the following steps:
when the current working voltage of the tested chip reaches the maximum working voltage and does not pass the pressure test, reducing the current working frequency and returning to the pressure test of the tested chip, wherein the reduced current working frequency is greater than the working frequency corresponding to the pressure test which is passed by the tested chip for the previous time and is less than the working frequency corresponding to the pressure test.
6. A test chip, comprising:
the first determining unit is used for determining the current working frequency and the current working voltage of the single chip to be tested;
the test unit is used for carrying out pressure test on the chip to be tested which works by using the current working frequency and the current working voltage;
the adjusting unit is used for increasing the current working frequency and returning to the pressure test of the tested chip when the tested chip passes the pressure test; when the tested chip fails the pressure test, increasing the current working voltage;
and the second determining unit is used for returning to the pressure test of the tested chip when the increased current working voltage is not more than the maximum working voltage supported by the tested chip, otherwise, determining the maximum working frequency supported by the tested chip according to the working frequency corresponding to the pressure test passed by the tested chip.
7. The test chip of claim 6,
the adjusting unit is specifically configured to increase the frequency multiplication parameter according to a first preset step length; inputting the increased frequency multiplication parameters into the chip to be tested; and the frequency multiplication parameter is used for carrying out frequency multiplication processing on the chip to be tested on the basis of the frequency basic value.
8. The test chip of claim 6,
the test chip further comprises:
the reading unit is specifically used for reading a first register which represents whether the pressure test of the tested chip is normal or not;
and the third determining unit is used for determining that the tested chip passes the pressure test when the value read from the first register by the test chip is the first value.
9. The test chip of claim 6, 7 or 8,
the adjusting unit is specifically configured to increase the current operating frequency by a first amplitude when the number of times of the pressure test applied to the chip under test is less than a preset number of times; when the number of the pressure tests applied to the tested chip is not less than the preset number, increasing the current working frequency by a second amplitude; wherein the first amplitude is greater than the second amplitude.
10. The test chip of claim 6, 7 or 8,
the adjustment unit is further used for reducing the current working frequency and returning to the pressure test of the tested chip when the current working voltage of the tested chip reaches the maximum working voltage and does not pass the pressure test, wherein the reduced current working frequency is greater than the working frequency corresponding to the pressure test which is passed by the tested chip before and is less than the working frequency corresponding to the pressure test.
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| CN107908509A (en) * | 2017-11-07 | 2018-04-13 | 晶晨半导体(上海)股份有限公司 | A kind of automated testing method for processor |
| CN108459934B (en) * | 2017-12-22 | 2021-01-29 | 深圳比特微电子科技有限公司 | Method for searching optimum frequency |
| CN109065094B (en) * | 2018-08-09 | 2021-04-27 | 晶晨半导体（深圳）有限公司 | Method and system for obtaining mass production frequency of double-rate synchronous dynamic random access memory |
| CN111290890B (en) * | 2019-01-28 | 2023-02-24 | 紫光展讯通信(惠州)有限公司 | Chip screening method and device |
| CN111289873B (en) * | 2019-05-10 | 2022-10-25 | 展讯通信（上海）有限公司 | Chip testing method, chip parameter setting method and chip |
| CN112526319B (en) * | 2020-11-25 | 2022-11-22 | 海光信息技术股份有限公司 | Chip testing method and device, processor chip and server |
| CN114236363A (en) * | 2022-01-04 | 2022-03-25 | 深圳凯瑞通电子有限公司 | Stability testing method and system based on integrated circuit chip |
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| CN101908012A (en) * | 2009-06-05 | 2010-12-08 | 鸿富锦精密工业（深圳）有限公司 | Clock signal testing device and testing method thereof |
| CN104597393B (en) * | 2015-01-29 | 2017-09-12 | 华为技术有限公司 | A kind of determination method and device of chip maximum operating frequency |
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