CN117149691A - PCIe reference clock switching method, device, equipment and storage medium - Google Patents

PCIe reference clock switching method, device, equipment and storage medium Download PDF

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Publication number
CN117149691A
CN117149691A CN202311108575.0A CN202311108575A CN117149691A CN 117149691 A CN117149691 A CN 117149691A CN 202311108575 A CN202311108575 A CN 202311108575A CN 117149691 A CN117149691 A CN 117149691A
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China
Prior art keywords
reference clock
clock
signal
pcie
switching
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CN202311108575.0A
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Chinese (zh)
Inventor
王瑞
刘奇浩
孟凡兴
刘洋
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
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Priority to CN202311108575.0A priority Critical patent/CN117149691A/en
Publication of CN117149691A publication Critical patent/CN117149691A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/40—Bus structure
    • G06F13/4004—Coupling between buses
    • G06F13/4022—Coupling between buses using switching circuits, e.g. switching matrix, connection or expansion network
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0026—PCI express
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The embodiment of the application provides a PCIe reference clock switching method, device, equipment and storage medium, which are used for solving the technical problem that the existing PCIe reference clock cannot realize automatic switching. The method comprises the following steps: step S1: the counter is controlled to start counting at a stable clock frequency. Step S2: and outputting a marking signal when the counter count value reaches a set value. Step S3: and judging the level of the marking signal, and judging whether the external input clock is disconnected or not based on the level of the marking signal. Step S4: and switching the clock to an internal reference clock of the SSD solid state disk main control chip. The fault of the PCIe external reference clock of the main control chip can be detected rapidly, the PCIe external reference clock can be automatically switched to the PCIe reference clock in the main control chip, the normal operation of the SSD solid state disk is ensured, the hardware is adopted, the operation is simpler and more convenient, the stability is improved, and the stability of the SSD solid state disk main control chip and the accuracy of data transmission can be improved by switching the PCIe reference clock.

Description

PCIe reference clock switching method, device, equipment and storage medium
Technical Field
The present application relates to the field of clock switching technologies, and in particular, to a PCIe reference clock switching method, device, equipment, and storage medium.
Background
With the continuous popularization of solid state disks in storage markets, the requirements on the performance and stability of a main control chip of the SSD solid state disk are also higher. PCIe, as a high-speed serial interface, is widely used in data transmission between the SSD solid state disk main control chip and the host, so as to ensure the performance of high-speed data transmission. In PCIe systems, the reference clock is particularly important, and when the reference clock is lost or unstable, data transmission errors, performance degradation, equipment failure to identify, and even system errors and crashes are caused, so a method is needed to detect whether the PCIe reference clock is in place, so as to ensure accuracy and stability of data transmission between the SSD main control chip and the host.
At present, two main sources of PCIe reference clocks of the SSD solid state disk main control chip are available, one is that the SSD solid state disk and a host use the same homologous reference clock source, the other is that the SSD solid state disk and the host use independent reference clock sources, and in most cases, the first mode homologous reference clock source is used for data transmission. However, in this manner, a PCIe clock switching method for the mode is lacking, so as to determine whether the PCIe external reference clock input by the current master control chip is in place, and determine whether internal reference clock switching is required according to a monitoring result.
Disclosure of Invention
The embodiment of the application provides a PCIe reference clock switching method, device, equipment and storage medium, which are used for solving the technical problem that the existing PCIe reference clock cannot realize automatic switching.
According to the embodiment of the application, two groups of reference clock inputs (a chip external reference clock and a chip internal reference clock) are provided for design according to PCIe IP, and the embodiment of the application is characterized in that a reference clock detection unit is arranged in a SSD solid state disk main control chip and is provided with an enabling signal of the detection unit, when the enabling signal is started, whether the PCIe external reference clock input by the current main control chip is in place or not can be monitored, and whether internal reference clock switching is needed or not is judged according to a monitoring result. The following specifically explains the summary of the embodiments of the present application.
In one aspect, an embodiment of the present application provides a PCIe reference clock switching method, where the method includes the following steps:
step S1: the counter is controlled to start counting at a stable clock frequency.
Step S2: and outputting a marking signal when the counter count value reaches a set value.
Step S3: and judging the level of the marking signal, and judging whether the external input clock is disconnected or not based on the level of the marking signal.
Step S4: and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
In one possible implementation manner of the present application, a PCIe reference clock switching method as described above, before the step S1, the method further includes:
the clk_sel_en signal is enabled and the reference clock auto-switching function is turned on.
In one possible implementation manner of the present application, a PCIe reference clock switching method as described above, the step S2 specifically includes:
and outputting a first marking signal when the count value of the counter reaches a first set value.
In one possible implementation manner of the present application, a PCIe reference clock switching method as described above, the method further includes:
and outputting a second marking signal when the count value of the counter reaches a second set value.
In one possible implementation manner of the present application, a PCIe reference clock switching method as described above, the step S3 specifically includes:
step S31: and controlling the heartbeat detection module to receive the first marking signal, and judging whether the external input clock is normal or not based on the first marking signal.
Step S32: and if the external input clock is normal, generating a high-level signal.
Step S33: and controlling the heartbeat detection module to receive a second marking signal, and judging whether an external input clock is normal or not based on the second marking signal.
Step S34: and if the external input clock is normal, generating a low-level signal.
Step S35: and the control selector judges the first mark signal and the second mark signal, and if the first mark signal is effective and is a low-level signal, the external input clock is determined to be disconnected.
In one possible implementation manner of the present application, a PCIe reference clock switching method as described above, the method further includes:
if the second flag signal is valid and is a high level signal, it is determined that the external input clock is off.
In a possible implementation manner of the present application, a PCIe reference clock switching method as described in the foregoing, after the step S4, the method further includes:
the clock is determined to be switched.
The control firmware initiates a system reset.
The embodiment of the application further provides a PCIe reference clock switching device, which comprises:
and the counter module is used for controlling the counter to start counting at a stable clock frequency.
And the marking module is used for outputting a marking signal when the count value of the counter reaches a set value.
And the level judging module is used for judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal.
And the clock switching module is used for switching the clock to an internal reference clock of the SSD solid state disk main control chip.
Still further, an embodiment of the present application further provides a PCIe reference clock switching device, where the device includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to: controlling the counter to start counting at a stable clock frequency; outputting a marking signal when the counter count value reaches a set value; judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal; and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
Finally, an embodiment of the present application further provides a non-volatile computer storage medium for PCIe reference clock switching, storing computer executable instructions, where the computer executable instructions are configured to: controlling the counter to start counting at a stable clock frequency; outputting a marking signal when the counter count value reaches a set value; judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal; and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
The PCIe reference clock switching method, the device, the equipment and the storage medium provided by the embodiment of the application can quickly detect the faults of the PCIe external reference clock of the main control chip and realize automatic switching to the PCIe reference clock in the main control chip, thereby ensuring the normal operation of the SSD solid state disk; the automatic switching method provided by the application is realized by adopting hardware, can quickly respond without manual intervention, and is simpler and more convenient to operate; stability is improved, and stability of the SSD solid state disk main control chip and accuracy of data transmission can be improved by switching PCIe reference clocks. Through counting in the stable clock domain, when counting to a certain set value, polling is carried out to detect whether the PCIe external reference clock is in place, and when detecting that the PCIe external reference clock cannot work normally, the clock is automatically switched to the internal reference clock of the SSD main control chip, so that the phenomenon that the SSD main control chip cannot work normally due to the fact that the PCIe reference clock is lost is avoided.
Drawings
The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:
FIG. 1 is a diagram of an off-chip reference clock architecture used in an embodiment of the present application;
FIG. 2 is a diagram of an on-chip reference clock used in an embodiment of the present application;
FIG. 3 is a flowchart of a switching method of PCIe reference clocks according to an embodiment of the present application;
FIG. 4 is a diagram of a heartbeat detection device according to an embodiment of the present application;
FIG. 5 is a block diagram of a PCIe reference clock switching system according to an embodiment of the present application;
fig. 6 is a schematic diagram of a PCIe reference clock switching device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the technical solutions of the present application will be clearly and completely described below with reference to specific embodiments of the present application and corresponding drawings. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
With the continuous popularization of solid state disks in storage markets, the requirements on the performance and stability of a main control chip of the SSD solid state disk are also higher. PCIe, as a high-speed serial interface, is widely used in data transmission between the SSD solid state disk main control chip and the host, so as to ensure the performance of high-speed data transmission. In PCIe systems, the reference clock is particularly important, and when the reference clock is lost or unstable, data transmission errors, performance degradation, equipment failure to identify, and even system errors and crashes are caused, so a method is needed to detect whether the PCIe reference clock is in place, so as to ensure accuracy and stability of data transmission between the SSD main control chip and the host.
At present, two main sources of PCIe reference clocks of the SSD solid state disk main control chip are available, one is that the SSD solid state disk and a host use the same homologous reference clock source, the other is that the SSD solid state disk and the host use independent reference clock sources, and in most cases, the first mode homologous reference clock source is used for data transmission. However, in this manner, a PCIe clock switching method for the mode is lacking, so as to determine whether the PCIe external reference clock input by the current master control chip is in place, and determine whether internal reference clock switching is required according to a monitoring result.
The embodiment of the application provides a PCIe reference clock switching method, device, equipment and storage medium, which are used for solving the technical problem that the existing PCIe reference clock cannot realize automatic switching.
According to the embodiment of the application, two groups of reference clock inputs (a chip external reference clock and a chip internal reference clock) are provided for design according to PCIe IP, and the embodiment of the application is characterized in that a reference clock detection unit is arranged in a SSD solid state disk main control chip and is provided with an enabling signal of the detection unit, when the enabling signal is started, whether the PCIe external reference clock input by the current main control chip is in place or not can be monitored, and whether internal reference clock switching is needed or not is judged according to a monitoring result. The following describes the technical scheme provided by the embodiment of the application in detail through the attached drawings.
Fig. 1 is a schematic diagram of a PCIe physical electronic air layer using an off-chip reference clock, and an external input clock is generally the same reference clock as a host, where a wafer refers to the final product of an integrated circuit in a manufacturing process, and is manufactured by performing steps such as multiple processing and photolithography on a silicon wafer or other semiconductor material, and is a generally square or rectangular sheet, on which a large number of transistors, resistors, capacitors, and other elements are included to implement specific functions and circuits, which can be simply understood as the structure inside the chip. The off-chip reference clock is directly connected to the PHY interface ref_pad_clk_p/m signal through the PCB and the ref_use_pad signal of the following figure needs to be pulled high before the PHY perceives that the reference clock is accessed off-chip.
Fig. 2 is a block diagram of an on-chip reference clock, which is also from the outside of the chip by comparison with the clock source in fig. 1, but is not a homologous clock to the clock used by the host, and is mainly from a crystal oscillator on the PCB board. The external reference clock is converted into the reference clock in the chip through the buffer in the chip and is connected to the ref_alt_clk_p/m signal, and the ref_use_pad signal in the following diagram needs to be pulled low, so that the physical electron gas layer can sense that the reference clock is connected to the ref_alt_clk_p/m signal.
Fig. 3 is a flowchart of a PCIe reference clock switching method according to an embodiment of the present application. As shown in fig. 3, the method mainly comprises the following steps:
step S1: the counter is controlled to start counting at a stable clock frequency.
Step S2: and outputting a marking signal when the counter count value reaches a set value.
Step S3: and judging the level of the marking signal, and judging whether the external input clock is disconnected or not based on the level of the marking signal.
Step S4: and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
Further, before the step S1, the method further includes: the clk_sel_en signal is enabled and the reference clock auto-switching function is turned on.
Further, the step S2 specifically includes: and outputting a first marking signal when the count value of the counter reaches a first set value.
Further, the method further comprises: and outputting a second marking signal when the count value of the counter reaches a second set value.
Further, the step S3 specifically includes:
step S31: and controlling the heartbeat detection module to receive the first marking signal, and judging whether the external input clock is normal or not based on the first marking signal.
Step S32: and if the external input clock is normal, generating a high-level signal.
Step S33: and controlling the heartbeat detection module to receive a second marking signal, and judging whether an external input clock is normal or not based on the second marking signal.
Step S34: and if the external input clock is normal, generating a low-level signal.
Step S35: and the control selector judges the first mark signal and the second mark signal, and if the first mark signal is effective and is a low-level signal, the external input clock is determined to be disconnected.
Further, the method further comprises: if the second flag signal is valid and is a high level signal, it is determined that the external input clock is off.
After the step S4, the method further includes: the clock is determined to be switched. The control firmware initiates a system reset.
Specific embodiments of the present application are described below:
the application adopts a clock heartbeat detection method, and a specific structure diagram is shown in fig. 4, wherein an external input clock ref_pad_clk_100MHz and ref_pad_clk_p/m in fig. 2 are homologous clocks, ref_alt_clk_100MHz and ref_alt_clk_p/m in fig. 2 are homologous clocks, and clk_25MHz is a stable system clock in a main control chip.
In the present application, the clk_sel_en signal is first enabled for the purpose of: the Refclk automatic switching detection function is turned on. Then the counter counts at a stable clock frequency of 25MHz, when the counter reaches a first set value, a cnt_flg0 signal, that is, a first flag signal in the present application, is output, after the heartbeat detection module bat receives the cnt_flg0 signal, if the external input clock ref_pad_clk_100MHz normally outputs a level signal pad_clk_bat, and the signal is at a high level. cnt_flg0 is a flag signal when the counter counts to the first set value. Specifically, if the external input clock ref_pad_clk_100MHz is normal, the pad_clk_bat signal is controlled to output a high level.
Further, when the counter reaches the second set value, a cnt_flg1 signal, that is, the second flag signal in the present application, is output, after the heartbeat detection module bat receives the cnt_flg1 signal, if ref_pad_clk_100MHz normally outputs a level signal pad_clk_bat, and at this time, the signal is at a low level. cnt_flg1 is a flag signal when the counter counts to the second set value. Specifically, if the external input clock ref_pad_clk_100MHz is normal, the pad_clk_bat signal is controlled to output a low level.
Regarding the pad_clk_bat signal, it is controlled by cnt_flg0 and cnt_flg1 signals, respectively, if the external input clock ref_pad_clk_100MHz is normal, the pad_clk_bat signal is effectively controlled to output a high level when cnt_flg0, and the pad_clk_bat signal is effectively controlled to output a low level when cnt_flg1, and vice versa.
The selector sel module uses stable clock clk_25MHz to judge the signals input from the counter and the bat module, when cnt_flg0 is effective and pad_clk_bat is low, or cnt_flg1 is effective and pad_clk_bat is high, the externally input reference clock ref_pad_clk_100MHz is disconnected, and the clock ref_alt_clk_100MHz in the chip is automatically switched.
After the clock switching is completed, interrupt is sent to the firmware, and the firmware initiates system reset according to specific conditions in order to ensure high-speed stable performance of data transmission between the subsequent SSD main control chip and the host computer due to clock switching. The interrupt of transmission occurs because it is judged that the clock used before the clock switching instruction is abnormal, and if there is data transmission in an abnormal period, the data is possibly problematic, so that the interrupt is sent to the firmware, and the firmware makes a judgment after receiving the interrupt, and resets the system. The system reset firmware can control, and the firmware judges whether to reset according to specific conditions. Where firmware may be understood as a controller or other device having control functions.
The application realizes automatic detection of whether the PCIe external reference clock is in place or not through the clock heartbeat detection method, and realizes rapid automatic switching into an internal reference clock function when the external reference clock is out of place, thereby ensuring the stability of data transmission between the SSD main control chip and the host. The method is realized by hardware, has the advantages of reducing the use of PCB materials, saving the cost, having quick response, needing no manual intervention, enhancing the robustness, ensuring the stability and the reliability of data transmission between the SSD main control chip and the host, and the like, and has practicability and popularization value.
The PCIe reference clock switching method provided by the embodiment of the application can quickly detect the faults of the PCIe external reference clock of the main control chip and realize automatic switching to the PCIe reference clock in the main control chip, thereby ensuring the normal operation of the SSD solid state disk; the automatic switching method provided by the application is realized by adopting hardware, can quickly respond without manual intervention, and is simpler and more convenient to operate; stability is improved, and stability of the SSD solid state disk main control chip and accuracy of data transmission can be improved by switching PCIe reference clocks. Through counting in the stable clock domain, when counting to a certain set value, polling is carried out to detect whether the PCIe external reference clock is in place, and when detecting that the PCIe external reference clock cannot work normally, the clock is automatically switched to the internal reference clock of the SSD main control chip, so that the phenomenon that the SSD main control chip cannot work normally due to the fact that the PCIe reference clock is lost is avoided.
The above is a PCIe reference clock switching method provided by the embodiment of the present application, based on the same inventive concept, and the embodiment of the present application further provides a PCIe reference clock switching device, and fig. 5 is a composition diagram of a PCIe reference clock switching device provided by the embodiment of the present application, as shown in fig. 5, where the device mainly includes: a counter module 501 for controlling the counter to start counting at a stable clock frequency.
A marking module 502, configured to output a marking signal when the counter count value reaches a set value.
A level judging module 503, configured to judge the level of the flag signal, and judge whether the external input clock is disconnected based on the level of the flag signal.
The clock switching module 504 is configured to switch the clock to an internal reference clock of the SSD solid state disk master control chip.
In the embodiment of the present application, the level determination module 503 specifically performs: the counter counts at a stable clock frequency of 25MHz, and outputs a cnt_flg0 signal when the counter reaches a first set value, namely a first flag signal in the present application, and after the heartbeat detection module bat receives the cnt_flg0 signal, if the external input clock ref_pad_clk_100MHz normally outputs a level signal pad_clk_bat, the signal is at a high level. cnt_flg0 is a flag signal when the counter counts to the first set value. Specifically, if the external input clock ref_pad_clk_100MHz is normal, the pad_clk_bat signal is controlled to output a high level. When the counter reaches the second set value, a cnt_flg1 signal, that is, a second flag signal in the present application, is output, after the heartbeat detection module bat receives the cnt_flg1 signal, if ref_pad_clk_100MHz normally, a level signal pad_clk_bat is output, and at this time, the signal is at a low level. cnt_flg1 is a flag signal when the counter counts to the second set value. Specifically, if the external input clock ref_pad_clk_100MHz is normal, the pad_clk_bat signal is controlled to output a low level.
In the embodiment of the application, the power consumption modes of the SSD main control chip comprise a normal power consumption mode and a low power consumption mode. Generally, when a chip is switched from a normal power consumption mode to a low power consumption mode, the corresponding clock is also switched. In the process, to realize automatic clock switching, an external input reference clock is switched to an internal reference clock, and the key link is to identify the power consumption mode of the chip system.
Specifically, firstly, the chip state of the SSD main control chip and the task currently processed by the main control chip are collected, if complex tasks and processes such as data calculation and control are processed, the SSD main control chip is considered to be in a normal power consumption state at present, and if the corresponding process is not processed by the main control chip at present, the SSD main control chip is considered to be in a low power consumption mode at present. After the acquired chip state data of the SSD main control chip are processed, the chip state data are transmitted to a pre-trained BP neural network model for identification, the power consumption state predicted by the current SSD main control chip is output, and then whether the external input reference is needed to be switched into an internal reference clock is judged.
Further, for the predicted neural network model of the state data of the SSD main control chip, pre-training is needed, and the training process is as follows: and collecting relevant logs and data about chip processing tasks and processes in an SSD main control chip database, cleaning and processing the data to form a corresponding data set, wherein the data set comprises a training set test set, the SSD main control chip power consumption mode prediction model is trained through the training set, and the SSD main control chip power consumption mode prediction model is optimized and tested through the test set. The trained neural network model can complete data acquisition of the main control chip, and the power consumption mode of the current chip is predicted through the data. Further, the clock switching condition corresponding to the SSD main control chip under various power consumption modes can be obtained through massive historical data in the database, the clock switching condition is applied to what kind of clock is needed under the power consumption mode of the current SSD main control chip, and finally the SSD main control chip under the current power consumption is selected to be automatically switched.
The PCIe reference clock switching device provided by the embodiment of the application can quickly detect the faults of the PCIe external reference clock of the main control chip and realize automatic switching to the PCIe reference clock in the main control chip, thereby ensuring the normal operation of the SSD solid state disk; the automatic switching method provided by the application is realized by adopting hardware, can quickly respond without manual intervention, and is simpler and more convenient to operate; stability is improved, and stability of the SSD solid state disk main control chip and accuracy of data transmission can be improved by switching PCIe reference clocks. Through counting in the stable clock domain, when counting to a certain set value, polling is carried out to detect whether the PCIe external reference clock is in place, and when detecting that the PCIe external reference clock cannot work normally, the clock is automatically switched to the internal reference clock of the SSD main control chip, so that the phenomenon that the SSD main control chip cannot work normally due to the fact that the PCIe reference clock is lost is avoided.
The above is a PCIe reference clock switching device provided by the embodiment of the present application, based on the same inventive concept, the embodiment of the present application further provides a PCIe reference clock switching device, and fig. 6 is a schematic diagram of a PCIe reference clock switching device provided by the embodiment of the present application, where, as shown in fig. 6, the device mainly includes: at least one processor 601; and a memory 602 communicatively coupled to the at least one processor; wherein the memory 602 stores instructions executable by the at least one processor 601, the instructions being executable by the at least one processor 601 to enable the at least one processor 601 to: controlling the counter to start counting at a stable clock frequency; outputting a marking signal when the counter count value reaches a set value; judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal; and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
In addition, the embodiment of the application also provides a nonvolatile computer storage medium for switching PCIe reference clocks, which stores computer executable instructions, wherein the computer executable instructions are configured to: controlling the counter to start counting at a stable clock frequency; outputting a marking signal when the counter count value reaches a set value; judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal; and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
The PCIe reference clock switching method, the device, the equipment and the storage medium provided by the embodiment of the application can quickly detect the faults of the PCIe external reference clock of the main control chip and realize automatic switching to the PCIe reference clock in the main control chip, thereby ensuring the normal operation of the SSD solid state disk; the automatic switching method provided by the application is realized by adopting hardware, can quickly respond without manual intervention, and is simpler and more convenient to operate; stability is improved, and stability of the SSD solid state disk main control chip and accuracy of data transmission can be improved by switching PCIe reference clocks. Through counting in the stable clock domain, when counting to a certain set value, polling is carried out to detect whether the PCIe external reference clock is in place, and when detecting that the PCIe external reference clock cannot work normally, the clock is automatically switched to the internal reference clock of the SSD main control chip, so that the phenomenon that the SSD main control chip cannot work normally due to the fact that the PCIe reference clock is lost is avoided.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
In one typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.
The embodiments of the present application are described in a progressive manner, and the same and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in the differences from the other embodiments. In particular, for the device embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and reference is made to the description of the method embodiments in part.
It should also be noted that the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article or apparatus that comprises the element.
The foregoing is merely exemplary of the present application and is not intended to limit the present application. Various modifications and variations of the present application will be apparent to those skilled in the art. Any modification, equivalent replacement, improvement, etc. which come within the spirit and principles of the application are to be included in the scope of the claims of the present application.

Claims (10)

1. A PCIe reference clock switching method, the method comprising:
step S1: controlling the counter to start counting at a stable clock frequency;
step S2: outputting a marking signal when the counter count value reaches a set value;
step S3: judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal;
step S4: and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
2. The PCIe reference clock switching method according to claim 1 wherein prior to said step S1, said method further comprises:
the clk_sel_en signal is enabled and the reference clock auto-switching function is turned on.
3. The PCIe reference clock switching method according to claim 1 wherein step S2 specifically comprises:
and outputting a first marking signal when the count value of the counter reaches a first set value.
4. The PCIe reference clock switching method of claim 3 further comprising:
and outputting a second marking signal when the count value of the counter reaches a second set value.
5. The PCIe reference clock switching method according to claim 1 wherein step S3 specifically comprises:
step S31: the method comprises the steps that a heartbeat detection module is controlled to receive a first marking signal, and whether an external input clock is normal or not is judged based on the first marking signal;
step S32: if the external input clock is normal, generating a high-level signal;
step S33: the heartbeat detection module is controlled to receive a second marking signal, and whether an external input clock is normal or not is judged based on the second marking signal;
step S34: if the external input clock is normal, generating a low-level signal;
step S35: and the control selector judges the first mark signal and the second mark signal, and if the first mark signal is effective and is a low-level signal, the external input clock is determined to be disconnected.
6. The PCIe reference clock switching method of claim 5 wherein the method further comprises:
if the second flag signal is valid and is a high level signal, it is determined that the external input clock is off.
7. The PCIe reference clock switching method according to claim 1 wherein after said step S4, said method further comprises:
determining that the clock is switched;
the control firmware initiates a system reset.
8. A PCIe reference clock switching device, said device comprising:
a counter module for controlling the counter to start counting at a stable clock frequency;
the marking module is used for outputting a marking signal when the count value of the counter reaches a set value;
the level judging module is used for judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal;
and the clock switching module is used for switching the clock to an internal reference clock of the SSD solid state disk main control chip.
9. A PCIe reference clock switching device, the device comprising:
at least one processor; the method comprises the steps of,
a memory communicatively coupled to the at least one processor; wherein,
the memory stores instructions executable by the at least one processor to enable the at least one processor to:
controlling the counter to start counting at a stable clock frequency;
outputting a marking signal when the counter count value reaches a set value;
judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal;
and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
10. A non-volatile computer storage medium storing computer-executable instructions for PCIe reference clock switching, the computer-executable instructions configured to:
controlling the counter to start counting at a stable clock frequency;
outputting a marking signal when the counter count value reaches a set value;
judging the level of the marking signal and judging whether the external input clock is disconnected or not based on the level of the marking signal;
and switching the clock to an internal reference clock of the SSD solid state disk main control chip.
CN202311108575.0A 2023-08-30 2023-08-30 PCIe reference clock switching method, device, equipment and storage medium Pending CN117149691A (en)

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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117472837A (en) * 2023-12-27 2024-01-30 苏州元脑智能科技有限公司 Mode switching circuit and method, external expansion connector and PCIe board card

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN117472837A (en) * 2023-12-27 2024-01-30 苏州元脑智能科技有限公司 Mode switching circuit and method, external expansion connector and PCIe board card
CN117472837B (en) * 2023-12-27 2024-03-01 苏州元脑智能科技有限公司 Mode switching circuit and method, external expansion connector and PCIe board card

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