CN106971753B - A kind of latch structure that anti-SEU is reinforced - Google Patents
A kind of latch structure that anti-SEU is reinforced Download PDFInfo
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- CN106971753B CN106971753B CN201610878141.2A CN201610878141A CN106971753B CN 106971753 B CN106971753 B CN 106971753B CN 201610878141 A CN201610878141 A CN 201610878141A CN 106971753 B CN106971753 B CN 106971753B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
Abstract
The present invention discloses a kind of latch structure that anti-SEU is reinforced, including storage unit, prefix logic circuit, the storage unit includes the first branch, second branch, third branch, 4th branch, 5th branch, 6th branch, the storage unit further includes node A, node B1, node B2, node C1, node C2, node D, the node A is set in the first branch, the node B1 is set in the second branch, the node B2 is set to the third branch road, the node C1 is set to the 4th road, the node C2 is set to the 5th road, the node D is set to the 6th road, the output end of the prefix logic circuit respectively with the node B1, the node B2, the node C1, the node C2 is connected.The present invention increases the performance of anti-SEU, when 0 → 1 and 1 → 0 overturning occurs for any memory node, the present invention has correct logic to export by increasing redundant storage node.
Description
Technical field
The present invention relates to a kind of latch structures that anti-SEU is reinforced, and belong to latch anti-single particle overturning (SEU) reinforcing and set
Count technical field.
Background technique
The locating outer space of spacecraft operation, there is extremely severe radiation environments.Chip is by radiating ring in space
The influence in border, easily generation single particle effect cause the data of chip memory (such as latch) to be flipped, this mistake
Referred to as single-particle inversion (SEU).Continue forward development with modern production process, radiation environment for deep-submicron,
The influence of the storage unit circuit of nanometer technology size is increasing, causes circuit more and more sensitive to single particle effect.
The basic structure of conventional memory cell is a pair of back-to-back phase inverter, is connected with each other by positive feedback, Fig. 1 is
The basic structure schematic illustration of conventional memory cell, there are two complementary memory node A and A ' for shown structure tool.Assuming that node
A logic level is 0, then A ' logic level is 1.If node A ', which catches a packet, is turned into 0, node A is possible to therefore overturn
At 1, so that mistake occurs for the logic level values of two nodes of A and A '.
With the fast development of China's aerospace, urgent skill is proposed to high stability, the chip for capableing of Flouride-resistani acid phesphatase
Art demand.Moreover, commercial product also proposed higher finger to the performance of anti-single particle effect in the application of ground key
Mark requires.
Summary of the invention
It is an object of the present invention to overcome defect of the existing technology, the anti-SEU performance of traditional standard storage organization is made up
Low technical problem proposes a kind of latch structure that anti-SEU is reinforced.
The present invention adopts the following technical scheme: a kind of latch structure that anti-SEU is reinforced, which is characterized in that including storage
Unit, for the prefix logic circuit of data write-in, the storage unit includes the first branch, second branch, third branch, the
Four branches, the 5th branch, the 6th branch, the storage unit further include node A, node B1, node B2, node C1, node C2,
Node D, the node A are set in the first branch, and the node B1 is set in the second branch, the node B2
It is set to the third branch road, the node C1 is set to the 4th road, and the node C2 is set to the described 5th
Branch road, the node D are set to the 6th road, the first branch by the node A and the second branch,
The third branch, the 6th branch are connected, the second branch by the node B1 respectively with the first branch,
4th branch is connected, the third branch by the node B2 respectively with the first branch, the 5th branch
It is connected, the 4th branch is connected with the second branch, the 6th branch respectively by the node C1, and described
Five branches are connected with the third branch, the 6th branch respectively by the node C2, and the 6th branch passes through institute
Node D is stated to be connected with the 4th branch, the 5th branch, the first branch respectively, the prefix logic circuit
Output end is connected with the node B1, the node B2, the node C1, the node C2 respectively.
Preferably, the first branch includes first branch power supply, PMOS tube P1, NMOS tube N1A, NMOS tube N1B, described
First branch power supply is connected with the source electrode of the PMOS tube P1, and the drain electrode of the PMOS tube P1 is sequentially connected the node A, institute
The drain electrode of NMOS tube N1A is stated, the source electrode of the NMOS tube N1A is connected with the drain electrode of the NMOS tube N1B, the NMOS tube
The source electrode of N1B is grounded, and the grid of the PMOS tube P1 is connected with the node D, the grid and the section of the NMOS tube N1A
Point B1 is connected, and the grid of the NMOS tube N1B is connected with the node B2.
Preferably, the second branch includes second branch power supply, PMOS tube P2A, NMOS tube N2A, the second branch
Power supply is connected with the source electrode of the PMOS tube P2A, and the drain electrode of the PMOS tube P2A is sequentially connected the node B1, described
The drain electrode of NMOS tube N2A, the source electrode ground connection of the NMOS tube N2A, the grid of the PMOS tube P2A are connected with the node A,
The grid of the NMOS tube N2A is connected with the node C1.
Preferably, the third branch includes third branch power supply, PMOS tube P2B, NMOS tube N2B, the third branch
Power supply is connected with the source electrode of the PMOS tube P2B, and the drain electrode of the PMOS tube P2B is sequentially connected the node B2, described
The drain electrode of NMOS tube N2B, the source electrode ground connection of the NMOS tube N2B, the grid of the PMOS tube P2B are connected with the node A,
The grid of the NMOS tube N2B is connected with the node C2.
Preferably, the 4th branch includes the 4th branch power supply, PMOS tube P3A, NMOS tube N3A, the 4th branch
Power supply is connected with the source electrode of the PMOS tube P3A, and the drain electrode of the PMOS tube P3A is sequentially connected the node C1, described
The drain electrode of NMOS tube N3A, the source electrode ground connection of the NMOS tube N3A, the grid of the PMOS tube P3A are connected with the node D,
The grid of the NMOS tube N3A is connected with the node B1.
Preferably, the 5th branch includes the 5th branch power supply, PMOS tube P3B, NMOS tube N3B, the 5th branch
Power supply is connected with the source electrode of the PMOS tube P3B, and the drain electrode of the PMOS tube P3B is sequentially connected the node C2, described
The drain electrode of NMOS tube N3B, the source electrode ground connection of the NMOS tube N3B, the grid of the PMOS tube P3B are connected with the node D,
The grid of the NMOS tube N3B is connected with the node B2.
Preferably, the 6th branch includes the 6th branch power supply, PMOS tube P4, NMOS tube N4A, NMOS tube N4B, described
6th branch power supply is connected with the source electrode of the PMOS tube P4, and the drain electrode of the PMOS tube P4 is sequentially connected the node D, institute
The drain electrode of NMOS tube N4A is stated, the source electrode of the NMOS tube N4A is connected with the drain electrode of the NMOS tube N4B, the NMOS tube
The source electrode of N4B is grounded, and the grid of the PMOS tube P4 is connected with the node A, the grid and the section of the NMOS tube N4A
Point C1 is connected, and the grid of the NMOS tube N4B is connected with the node C2.
Preferably, the prefix logic circuit includes the first logic circuit, the second logic circuit, third logic circuit, the
Four logic circuits, first logic circuit, second logic circuit, the third logic circuit, the 4th logic electricity
Road is connected with each other by 2 PMOS tube, 2 NMOS tubes respectively, the input terminating data input of first logic circuit
In, clock input clock and clock ', and the output of first logic circuit terminates the node B1；The second logic electricity
Input terminating data input in, the clock on road input clock and clock ', and the output of second logic circuit terminates the section
Point B2；Input terminating data input in ', the clock of the third logic circuit input clock and clock ', the third logic
The output of circuit terminates the node C1；Input terminating data input in ', the clock of 4th logic circuit input clock
And clock ', the output of the 4th logic circuit terminate the node C2.
Advantageous effects of the invention: the present invention increases the performance of anti-SEU by increase redundant storage node, when
0 → 1 and 1 → 0 overturning occurs for any memory node, and the present invention can have correct logic to export.
Detailed description of the invention
Fig. 1 is the basic structure schematic diagram of conventional memory cell.
Fig. 2 is the circuit theory schematic diagram for the latch structure that a kind of anti-SEU of the invention is reinforced.
Fig. 3 is the circuit theory schematic diagram of logic read/write circuit of the invention.
Fig. 4 is circuit theory schematic diagram when node B1 of the invention is flipped.
Fig. 5 is circuit theory schematic diagram when node B2 of the invention is flipped.
Fig. 6 is circuit theory schematic diagram when node C1 of the invention is flipped.
Fig. 7 is circuit theory schematic diagram when node C2 of the invention is flipped.
Fig. 8 is circuit theory schematic diagram when node A of the invention is flipped.
Fig. 9 is circuit theory schematic diagram when node D of the invention is flipped.
Specific embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following embodiment is only used for clearly illustrating the present invention
Technical solution, and not intended to limit the protection scope of the present invention.
Fig. 2 is the circuit theory schematic diagram for the latch structure that a kind of anti-SEU of the invention is reinforced.The present invention proposes one kind
The latch structure that anti-SEU is reinforced, which is characterized in that including storage unit, prefix logic circuit, the storage unit includes the
One branch, second branch, third branch, the 4th branch, the 5th branch, the 6th branch, the storage unit further include node A,
Totally six redundant storage nodes, the node A are set to described first by node B1, node B2, node C1, node C2, node D
On the road, the node B1 is set in the second branch, and the node B2 is set to the third branch road, the node C1
It is set to the 4th road, the node C2 is set to the 5th road, and the node D is set to described 6th
On the road, the first branch is connected by the node A with the second branch, the third branch, the 6th branch,
The second branch is connected with the first branch, the 4th branch respectively by the node B1, the third branch
It is connected respectively with the first branch, the 5th branch by the node B2, the 4th branch passes through the node
C1 is connected with the second branch, the 6th branch respectively, the 5th branch by the node C2 respectively with it is described
Third branch, the 6th branch are connected, the 6th branch by the node D respectively with the 4th branch, described
5th branch, the first branch are connected, the output end of the prefix logic circuit respectively with the node B1, the node
B2, the node C1, the node C2 are connected.
As a kind of preferred embodiment, the first branch include first branch power supply, PMOS tube P1, NMOS tube N1A,
NMOS tube N1B, the first branch power supply are connected with the source electrode of the PMOS tube P1, and the drain electrode of the PMOS tube P1 successively connects
The drain electrode of the node A, the NMOS tube N1A are connect, the source electrode of the NMOS tube N1A is connected with the drain electrode of the NMOS tube N1B
It connects, the source electrode ground connection of the NMOS tube N1B, the grid of the PMOS tube P1 is connected with the node D, the NMOS tube N1A
Grid be connected with the node B1, the grid of the NMOS tube N1B is connected with the node B2.
As a kind of preferred embodiment, the second branch includes second branch power supply, PMOS tube P2A, NMOS tube
N2A, the second branch power supply are connected with the source electrode of the PMOS tube P2A, and the drain electrode of the PMOS tube P2A is sequentially connected institute
State the drain electrode of node B1, the NMOS tube N2A, the source electrode ground connection of the NMOS tube N2A, the grid of the PMOS tube P2A and institute
It states node A to be connected, the grid of the NMOS tube N2A is connected with the node C1.
As a kind of preferred embodiment, the third branch includes third branch power supply, PMOS tube P2B, NMOS tube
N2B, the third branch power supply are connected with the source electrode of the PMOS tube P2B, and the drain electrode of the PMOS tube P2B is sequentially connected institute
State the drain electrode of node B2, the NMOS tube N2B, the source electrode ground connection of the NMOS tube N2B, the grid of the PMOS tube P2B and institute
It states node A to be connected, the grid of the NMOS tube N2B is connected with the node C2.
As a kind of preferred embodiment, the 4th branch includes the 4th branch power supply, PMOS tube P3A, NMOS tube
N3A, the 4th branch power supply are connected with the source electrode of the PMOS tube P3A, and the drain electrode of the PMOS tube P3A is sequentially connected institute
State the drain electrode of node C1, the NMOS tube N3A, the source electrode ground connection of the NMOS tube N3A, the grid of the PMOS tube P3A and institute
It states node D to be connected, the grid of the NMOS tube N3A is connected with the node B1.
As a kind of preferred embodiment, the 5th branch includes the 5th branch power supply, PMOS tube P3B, NMOS tube
N3B, the 5th branch power supply are connected with the source electrode of the PMOS tube P3B, and the drain electrode of the PMOS tube P3B is sequentially connected institute
State the drain electrode of node C2, the NMOS tube N3B, the source electrode ground connection of the NMOS tube N3B, the grid of the PMOS tube P3B and institute
It states node D to be connected, the grid of the NMOS tube N3B is connected with the node B2.
As a kind of preferred embodiment, the 6th branch include the 6th branch power supply, PMOS tube P4, NMOS tube N4A,
NMOS tube N4B, the 6th branch power supply are connected with the source electrode of the PMOS tube P4, and the drain electrode of the PMOS tube P4 successively connects
The drain electrode of the node D, the NMOS tube N4A are connect, the source electrode of the NMOS tube N4A is connected with the drain electrode of the NMOS tube N4B
It connects, the source electrode ground connection of the NMOS tube N4B, the grid of the PMOS tube P4 is connected with the node A, the NMOS tube N4A
Grid be connected with the node C1, the grid of the NMOS tube N4B is connected with the node C2.
Fig. 3 is the circuit theory schematic diagram of prefix logic circuit of the invention.The prefix logic circuit is patrolled including first
Collect circuit, the second logic circuit, third logic circuit, the 4th logic circuit, first logic circuit, second logic electricity
Road, the third logic circuit, the 4th logic circuit are connected with each other by 2 PMOS tube, 2 NMOS tubes respectively,
Input terminating data input in, the clock of first logic circuit input clock and clock ', first logic circuit
Output terminates the node B1；Second logic circuit input terminating data input in, clock input clock and
The output of clock ', second logic circuit terminate the node B2；The input terminating data of the third logic circuit is defeated
Enter in ', clock input clock and clock ', the output of the third logic circuit terminates the node C1；4th logic
Input terminating data input in ', the clock of circuit input clock and clock ', and the output of the 4th logic circuit terminates institute
State node C2.
The working principle of the invention: the latch structure that a kind of anti-SEU of the invention is reinforced includes data write operation and guarantor
Hold operation.Data write operation are as follows: (1) as clock and clock ' when being respectively high level and low level, if in is high level,
Then in ' is low level, and B1 and B2 are respectively low level, and C1 and C2 are respectively high level；(2) as clock and clock ' respectively
When for high level and low level, if in is low level, in ' is high level, then B1 and B2 is high level, and C1 and C2 is low electricity
It is flat.Keep operation for as clock and clock ' it is respectively circuit conditions under low level and high level.
The present invention has the anti-SEU immunity of single node, because the present invention has symmetry, only analysis is when with lower node
A, anti-SEU characteristic when B1, B2, C1, C2, D are respectively logic 1,0,0,1,1,0 is made a concrete analysis of as follows.
The first situation: 0 → 1 transient pulse is occurred by high energy particle strike for node B1.NMOS tube N1A is become by cut-off
To be connected, but since NMOS tube N1B still ends, so node A will not be flipped.On the other hand, even if the negative transient state of B1
Pulse enables to N3A conducting and the therefore logic level of pulling down node C1, but this can only allow NMOS tube N4A cut-off that can't change
The level of traitorous point D, so node D floating is in high-impedance state, Fig. 4 is circuit theory when node B1 of the invention is flipped
Schematic diagram.
Second situation: 0 → 1 transient pulse is occurred by high energy particle strike for node B2.NMOS tube N1B is become by cut-off
To be connected, but since NMOS tube N1A still ends, so node A will not be flipped.On the other hand, even if the negative wink of B2
State pulse enables to N3B conducting and the therefore logic level of pulling down node C2, but this can only allow NMOS tube N4B cut-off can't
The level of concept transfer D, so node D floating is in high-impedance state, Fig. 5 is that circuit when node B2 of the invention is flipped is former
Manage schematic diagram.
The third situation: 1 → 0 transient pulse is occurred by high energy particle strike for node C1.When node C1 is from 1 overturning
When 0, NMOS tube N2A becomes ending from being connected, so node B1 floating but can't overturn.Likewise, NMOS tube N4A is by being connected
Become ending, also only make node D floating, Fig. 6 is circuit theory schematic diagram when node C1 of the invention is flipped.
4th kind of situation: 1 → 0 transient pulse is occurred by high energy particle strike for node C2.When node C2 is by 1 overturning
When 0, NMOS tube N2B becomes ending from being connected, so node B2 floating but can't overturn.Likewise, NMOS tube N4B is by being connected
Become ending, also make node D floating, Fig. 7 is circuit theory schematic diagram when node C2 of the invention is flipped.
5th kind of situation: 1 → 0 transient pulse is occurred by high energy particle strike for node A.If node A is by high energy
The strike of particle, occurs 1 → 0 transient pulse, and may cause PMOS tube P2A conducting, but since node C1 makes for high level
NMOS tube N2A conducting is obtained, and NMOS tube N2A has driving capability more higher than PMOS tube P2A, node B1 can't be overturn.Together
Sample, node B2 and node D will not be flipped, and finish node A level restores, and Fig. 8 is that node A of the invention is flipped
When circuit theory schematic diagram.
6th kind of situation: 0 → 1 transient pulse is occurred by high energy particle strike for node D.If node D is by high energy grain
The strike of son, the transient pulse of node D are 1 by 0 overturning, only end PMOS tube P3A, P3B, and lead to node C1, node C2
Floating can't generate level overturning, and Fig. 9 is circuit theory schematic diagram when node D of the invention is flipped.
In conclusion the overturning of each redundant storage node will not cause the overturning of other any nodes, so that
Entire latch structure will not be overturn, and the present invention is the latch structure being immunized with single node SEU, and the present invention solves
The problem of anti-SEU.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (8)
1. a kind of latch structure that anti-SEU is reinforced, which is characterized in that including storage unit, prefix logic circuit, the storage
Unit includes the first branch, second branch, third branch, the 4th branch, the 5th branch, the 6th branch, and the storage unit is also
Including node A, node B1, node B2, node C1, node C2, node D, the node A is set in the first branch, institute
It states node B1 to be set in the second branch, the node B2 is set to the third branch road, and the node C1 is set to
4th road, the node C2 are set to the 5th road, and the node D is set to the 6th road,
The first branch is connected by the node A with the second branch, the third branch, the 6th branch, described
Second branch is connected with the first branch, the 4th branch respectively by the node B1, and the third branch passes through
The node B2 is connected with the first branch, the 5th branch respectively, and the 4th branch passes through the node C1 points
Be not connected with the second branch, the 6th branch, the 5th branch by the node C2 respectively with the third
Branch, the 6th branch are connected, the 6th branch by the node D respectively with the 4th branch, the described 5th
Branch, the first branch are connected, the output end of the prefix logic circuit respectively with the node B1, the node B2,
The node C1, the node C2 are connected；
The first branch includes PMOS tube P1, NMOS tube N1A, NMOS tube N1B, and the drain electrode of the PMOS tube P1 is sequentially connected institute
The drain electrode of node A, the NMOS tube N1A are stated, the source electrode of the NMOS tube N1A is connected with the drain electrode of the NMOS tube N1B, institute
The source electrode ground connection of NMOS tube N1B is stated, the grid of the PMOS tube P1 is connected with the node D, the grid of the NMOS tube N1A
It is connected with the node B1, the grid of the NMOS tube N1B is connected with the node B2；
The second branch includes PMOS tube P2A, NMOS tube N2A, and the drain electrode of the PMOS tube P2A is sequentially connected the node
The drain electrode of B1, the NMOS tube N2A, the source electrode ground connection of the NMOS tube N2A, the grid of the PMOS tube P2A and the node A
It is connected, the grid of the NMOS tube N2A is connected with the node C1；
The third branch includes PMOS tube P2B, NMOS tube N2B, and the drain electrode of the PMOS tube P2B is sequentially connected the node
The drain electrode of B2, the NMOS tube N2B, the source electrode ground connection of the NMOS tube N2B, the grid of the PMOS tube P2B and the node A
It is connected, the grid of the NMOS tube N2B is connected with the node C2.
2. the latch structure that a kind of anti-SEU according to claim 1 is reinforced, which is characterized in that the first branch is also
Including first branch power supply, the first branch power supply is connected with the source electrode of the PMOS tube P1.
3. according to claim 1 or a kind of latch structure reinforced of 2 any anti-SEU, which is characterized in that described second
Branch further includes second branch power supply, and the second branch power supply is connected with the source electrode of the PMOS tube P2A.
4. the latch structure that a kind of anti-SEU according to claim 1 is reinforced, which is characterized in that the third branch is also
Including third branch power supply, the third branch power supply is connected with the source electrode of the PMOS tube P2B.
5. the latch structure that a kind of anti-SEU according to claim 1 is reinforced, which is characterized in that the 4th branch packet
The 4th branch power supply, PMOS tube P3A, NMOS tube N3A are included, the 4th branch power supply is connected with the source electrode of the PMOS tube P3A
It connects, the drain electrode of the PMOS tube P3A is sequentially connected the drain electrode of the node C1, the NMOS tube N3A, the NMOS tube N3A's
Source electrode ground connection, the grid of the PMOS tube P3A are connected with the node D, the grid of the NMOS tube N3A and the node B1
It is connected.
6. the latch structure that a kind of anti-SEU according to claim 1 is reinforced, which is characterized in that the 5th branch packet
The 5th branch power supply, PMOS tube P3B, NMOS tube N3B are included, the 5th branch power supply is connected with the source electrode of the PMOS tube P3B
It connects, the drain electrode of the PMOS tube P3B is sequentially connected the drain electrode of the node C2, the NMOS tube N3B, the NMOS tube N3B's
Source electrode ground connection, the grid of the PMOS tube P3B are connected with the node D, the grid of the NMOS tube N3B and the node B2
It is connected.
7. the latch structure that a kind of anti-SEU according to claim 1 is reinforced, which is characterized in that the 6th branch packet
The 6th branch power supply, PMOS tube P4, NMOS tube N4A, NMOS tube N4B are included, the 6th branch power supply is with the PMOS tube P4's
Source electrode is connected, and the drain electrode of the PMOS tube P4 is sequentially connected the drain electrode of the node D, the NMOS tube N4A, the NMOS tube
The source electrode of N4A is connected with the drain electrode of the NMOS tube N4B, the source electrode ground connection of the NMOS tube N4B, the grid of the PMOS tube P4
Pole is connected with the node A, and the grid of the NMOS tube N4A is connected with the node C1, the grid of the NMOS tube N4B
It is connected with the node C2.
8. the latch structure that a kind of anti-SEU according to claim 1 is reinforced, which is characterized in that the prefix logic electricity
Road includes the first logic circuit, the second logic circuit, third logic circuit, the 4th logic circuit, first logic circuit, institute
The second logic circuit, the third logic circuit, the 4th logic circuit are stated respectively by 2 PMOS tube, 2 NMOS tube phases
It connecting, the input terminating data of first logic circuit input in, clock input clock and clock ', and described the
The output of one logic circuit terminates the node B1；The input terminating data input in of second logic circuit, clock input
The output of clock and clock ', second logic circuit terminate the node B2；The input of the third logic circuit terminates
Data input in ', clock inputs clock and clock ', and the output of the third logic circuit terminates the node C1；Described
Input terminating data input in ', the clock of four logic circuits input clock and clock ', the output of the 4th logic circuit
Terminate the node C2.
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| CN111969998B (en) * | 2020-08-03 | 2022-10-04 | 河海大学常州校区 | Latch structure capable of resisting single event upset |
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| CN102122950A (en) * | 2011-01-10 | 2011-07-13 | 深圳市国微电子股份有限公司 | High-speed low-power consumption latch device capable of resisting SEU (single event upset) |
| US9281807B1 (en) * | 2014-06-09 | 2016-03-08 | Xilinx, Inc. | Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit |
| CN104022773A (en) * | 2014-06-24 | 2014-09-03 | 河海大学常州校区 | DICE (dual interlocked storage cell)-based novel SEU (single event upset)-resistant reinforced SR latch |
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| CN106971753A (en) | 2017-07-21 |
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