CN106971753A - The latch structure that a kind of anti-SEU is reinforced - Google Patents
The latch structure that a kind of anti-SEU is reinforced Download PDFInfo
- Publication number
- CN106971753A CN106971753A CN201610878141.2A CN201610878141A CN106971753A CN 106971753 A CN106971753 A CN 106971753A CN 201610878141 A CN201610878141 A CN 201610878141A CN 106971753 A CN106971753 A CN 106971753A
- Authority
- CN
- China
- Prior art keywords
- node
- branch road
- nmos tube
- pmos
- logic circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
Abstract
The present invention discloses the latch structure that a kind of anti-SEU is reinforced, including memory cell, prefix logic circuit, the memory cell includes tie point, second branch road, 3rd branch road, 4th branch road, 5th branch road, 6th branch road, the memory cell also includes node A, node B1, node B2, node C1, node C2, node D, the node A is arranged in the tie point, the node B1 is arranged on second branch road, the node B2 is arranged on the 3rd branch road, the node C1 is arranged on the 4th branch road, the node C2 is arranged on the 5th branch road, the node D is arranged on the 6th branch road, the output end of the prefix logic circuit respectively with the node B1, the node B2, the node C1, the node C2 is connected.The present invention increases anti-SEU performance by increasing redundant storage node, and when 0 → 1 and 1 → 0 upset occurs for any of which memory node, the present invention has correct logic to export.
Description
Technical field
The present invention relates to the latch structure that a kind of anti-SEU is reinforced, belong to latch anti-single particle upset (SEU) reinforcing and set
Count technical field.
Background technology
The residing outer space of spacecraft operation, has extremely severe radiation environment.Chip in space by radiating ring
The influence in border, easily produces single particle effect and causes the data of chip memory (such as latch) to overturn, this mistake
It is referred to as single-particle inversion (SEU).With the development continued forward of modern production process, radiation environment for deep-submicron,
The influence of the storage unit circuit of nanometer technology size is increasing, causes circuit more and more sensitive to single particle effect.
The basic structure of conventional memory cell is a pair of back-to-back phase inverters, is connected with each other by positive feedback, Fig. 1 is
The basic structure principle schematic of conventional memory cell, shown structure has two complementary memory node A and A '.Assuming that node
A logic levels are 0, then A ' logic levels are 1.If node A ', which catches a packet, is turned into 0, node A is possible to therefore overturn
Into 1, so that the logic level values of two nodes of A and A ' make a mistake.
With the fast development of China's Aero-Space, urgent skill is proposed to high stability, the chip for being capable of Flouride-resistani acid phesphatase
Art demand.Moreover, performance of the commercial product to anti-single particle effect in the key application of ground it is also proposed higher finger
Mark is required.
The content of the invention
It is an object of the present invention to which the defect for overcoming prior art to exist, makes up the anti-SEU performances of traditional standard storage organization
Low technical problem, proposes the latch structure that a kind of anti-SEU is reinforced.
The present invention is adopted the following technical scheme that：The latch structure that a kind of anti-SEU is reinforced, it is characterised in that including storage
Unit, the prefix logic circuit write for data, the memory cell include tie point, the second branch road, the 3rd branch road, the
Four branch roads, the 5th branch road, the 6th branch road, the memory cell also include node A, node B1, node B2, node C1, node C2,
Node D, the node A are arranged in the tie point, and the node B1 is arranged on second branch road, the node B2
It is arranged on the 3rd branch road, the node C1 is arranged on the 4th branch road, the node C2 is arranged at the described 5th
On branch road, the node D is arranged on the 6th branch road, the tie point by the node A and second branch road,
3rd branch road, the 6th branch road are connected, second branch road by the node B1 respectively with the tie point,
4th branch road is connected, the 3rd branch road by the node B2 respectively with the tie point, the 5th branch road
It is connected, the 4th branch road is connected with second branch road, the 6th branch road respectively by the node C1, described
Five branch roads are connected with the 3rd branch road, the 6th branch road respectively by the node C2, and the 6th branch road passes through institute
Node D is stated respectively with the 4th branch road, the 5th branch road, the tie point to be connected, the prefix logic circuit
Output end is connected with the node B1, the node B2, the node C1, the node C2 respectively.
Preferably, the tie point includes tie point power supply, PMOS P1, NMOS tube N1A, NMOS tube N1B, described
Tie point power supply is connected with the source electrode of the PMOS P1, and the drain electrode of the PMOS P1 is sequentially connected the node A, institute
NMOS tube N1A drain electrode is stated, the source electrode of the NMOS tube N1A is connected with the drain electrode of the NMOS tube N1B, the NMOS tube
N1B source ground, the grid of the PMOS P1 is connected with the node D, the grid of the NMOS tube N1A and the section
Point B1 is connected, and the grid of the NMOS tube N1B is connected with the node B2.
Preferably, second branch road includes the second branch road power supply, PMOS P2A, NMOS tube N2A, second branch road
Power supply is connected with the source electrode of the PMOS P2A, and the drain electrode of the PMOS P2A is sequentially connected the node B1, described
NMOS tube N2A drain electrode, the source ground of the NMOS tube N2A, the grid of the PMOS P2A is connected with the node A,
The grid of the NMOS tube N2A is connected with the node C1.
Preferably, the 3rd branch road includes the 3rd branch road power supply, PMOS P2B, NMOS tube N2B, the 3rd branch road
Power supply is connected with the source electrode of the PMOS P2B, and the drain electrode of the PMOS P2B is sequentially connected the node B2, described
NMOS tube N2B drain electrode, the source ground of the NMOS tube N2B, the grid of the PMOS P2B is connected with the node A,
The grid of the NMOS tube N2B is connected with the node C2.
Preferably, the 4th branch road includes the 4th branch road power supply, PMOS P3A, NMOS tube N3A, the 4th branch road
Power supply is connected with the source electrode of the PMOS P3A, and the drain electrode of the PMOS P3A is sequentially connected the node C1, described
NMOS tube N3A drain electrode, the source ground of the NMOS tube N3A, the grid of the PMOS P3A is connected with the node D,
The grid of the NMOS tube N3A is connected with the node B1.
Preferably, the 5th branch road includes the 5th branch road power supply, PMOS P3B, NMOS tube N3B, the 5th branch road
Power supply is connected with the source electrode of the PMOS P3B, and the drain electrode of the PMOS P3B is sequentially connected the node C2, described
NMOS tube N3B drain electrode, the source ground of the NMOS tube N3B, the grid of the PMOS P3B is connected with the node D,
The grid of the NMOS tube N3B is connected with the node B2.
Preferably, the 6th branch road includes the 6th branch road power supply, PMOS P4, NMOS tube N4A, NMOS tube N4B, described
6th branch road power supply is connected with the source electrode of the PMOS P4, and the drain electrode of the PMOS P4 is sequentially connected the node D, institute
NMOS tube N4A drain electrode is stated, the source electrode of the NMOS tube N4A is connected with the drain electrode of the NMOS tube N4B, the NMOS tube
N4B source ground, the grid of the PMOS pipes P4 is connected with the node A, the grid of the NMOS tube N4A with it is described
Node C1 is connected, and the grid of the NMOS tube N4B is connected with the node C2.
Preferably, the prefix logic circuit includes the first logic circuit, the second logic circuit, the 3rd logic circuit, the
Four logic circuits, first logic circuit, second logic circuit, the 3rd logic circuit, the 4th logic electricity
Road is respectively connected with each other and formed by 2 PMOSs, 2 NMOS tubes, the input termination data input of first logic circuit
In, clock input clock and clock□, the output termination node B1 of first logic circuit；The second logic electricity
Input termination data input in, the clock input clock and clock on road□, the output termination section of second logic circuit
Point B2；The input termination data input in of 3rd logic circuit□, clock input clock and clock□, the 3rd logic
The output of circuit terminates the node C1；The input termination data input in of 4th logic circuit□, clock input clock
And clock□, the output termination node C2 of the 4th logic circuit.
The beneficial effect that the present invention is reached：The present invention increases anti-SEU performance by increasing redundant storage node, when
0 → 1 and 1 → 0 upset occurs for any of which memory node, and the present invention can have the output of correct logic.
Brief description of the drawings
Fig. 1 is the basic structure schematic diagram of conventional memory cell.
Fig. 2 is a kind of circuit theory schematic diagram of the latch structure of anti-SEU reinforcings of the present invention.
Fig. 3 is the circuit theory schematic diagram of the logic read/write circuit of the present invention.
Fig. 4 is circuit theory schematic diagram when node B1 of the invention is overturn.
Fig. 5 is circuit theory schematic diagram when node B2 of the invention is overturn.
Fig. 6 is circuit theory schematic diagram when node C1 of the invention is overturn.
Fig. 7 is circuit theory schematic diagram when node C2 of the invention is overturn.
Fig. 8 is circuit theory schematic diagram when node A of the invention is overturn.
Fig. 9 is circuit theory schematic diagram when node D of the invention is overturn.
Embodiment
The invention will be further described below in conjunction with the accompanying drawings.Following examples are only used for clearly illustrating the present invention
Technical scheme, and can not be limited the scope of the invention with this.
Fig. 2 is a kind of circuit theory schematic diagram of the latch structure of anti-SEU reinforcings of the present invention.The present invention proposes a kind of
The latch structure that anti-SEU is reinforced, it is characterised in that including memory cell, prefix logic circuit, the memory cell includes the
One branch road, the second branch road, the 3rd branch road, the 4th branch road, the 5th branch road, the 6th branch road, the memory cell also include node A,
Node B1, node B2, node C1, node C2, node D totally six redundant storage nodes, the node A are arranged at described first
Lu Shang, the node B1 is arranged on second branch road, and the node B2 is arranged on the 3rd branch road, the node C1
It is arranged on the 4th branch road, the node C2 is arranged on the 5th branch road, the node D is arranged at described 6th
Lu Shang, the tie point is connected by the node A with second branch road, the 3rd branch road, the 6th branch road,
Second branch road is connected with the tie point, the 4th branch road respectively by the node B1, the 3rd branch road
It is connected respectively with the tie point, the 5th branch road by the node B2, the 4th branch road passes through the node
C1 is connected with second branch road, the 6th branch road respectively, the 5th branch road by the node C2 respectively with it is described
3rd branch road, the 6th branch road are connected, the 6th branch road by the node D respectively with the 4th branch road, described
5th branch road, the tie point are connected, the output end of the prefix logic circuit respectively with the node B1, the node
B2, the node C1, the node C2 are connected.
As a kind of preferred embodiment, the tie point include tie point power supply, PMOS P1, NMOS tube N1A,
NMOS tube N1B, the tie point power supply is connected with the source electrode of the PMOS P1, and the drain electrode of the PMOS P1 connects successively
The node A, the drain electrode of the NMOS tube N1A are connect, the source electrode of the NMOS tube N1A is connected with the drain electrode of the NMOS tube N1B
Connect, the source ground of the NMOS tube N1B, the grid of the PMOS P1 is connected with the node D, the NMOS pipes N1A
Grid be connected with the node B1, the grid of the NMOS tube N1B is connected with the node B2.
As a kind of preferred embodiment, second branch road includes the second branch road power supply, PMOS P2A, NMOS tube
N2A, the second branch road power supply is connected with the source electrode of the PMOS P2A, and the drain electrode of the PMOS P2A is sequentially connected institute
State node B1, the drain electrode of the NMOS tube N2A, the source ground of the NMOS tube N2A, the grid of the PMOS P2A and institute
State node A to be connected, the grid of the NMOS tube N2A is connected with the node C1.
As a kind of preferred embodiment, the 3rd branch road includes the 3rd branch road power supply, PMOS P2B, NMOS tube
N2B, the 3rd branch road power supply is connected with the source electrode of the PMOS P2B, and the drain electrode of the PMOS P2B is sequentially connected institute
State node B2, the drain electrode of the NMOS tube N2B, the source ground of the NMOS tube N2B, the grid of the PMOS P2B and institute
State node A to be connected, the grid of the NMOS tube N2B is connected with the node C2.
As a kind of preferred embodiment, the 4th branch road includes the 4th branch road power supply, PMOS P3A, NMOS tube
N3A, the 4th branch road power supply is connected with the source electrode of the PMOS P3A, and the drain electrode of the PMOS P3A is sequentially connected institute
State node C1, the drain electrode of the NMOS tube N3A, the source ground of the NMOS tube N3A, the grid of the PMOS P3A and institute
State node D to be connected, the grid of the NMOS tube N3A is connected with the node B1.
As a kind of preferred embodiment, the 5th branch road includes the 5th branch road power supply, PMOS P3B, NMOS tube
N3B, the 5th branch road power supply is connected with the source electrode of the PMOS P3B, and the drain electrode of the PMOS P3B is sequentially connected institute
State node C2, the drain electrode of the NMOS tube N3B, the source ground of the NMOS tube N3B, the grid of the PMOS P3B and institute
State node D to be connected, the grid of the NMOS tube N3B is connected with the node B2.
As a kind of preferred embodiment, the 6th branch road includes the 6th branch road power supply, PMOS P4, NMOS tube
N4A, NMOS tube N4B, the 6th branch road power supply are connected with the source electrode of the PMOS P4, the drain electrode of the PMOS P4 according to
The secondary connection node D, the drain electrode of the NMOS tube N4A, the drain electrode of the source electrode of the NMOS tube N4A and the NMOS tube N4B
It is connected, the source ground of the NMOS tube N4B, the grid of the PMOS P4 is connected with the node A, the NMOS tube
N4A grid is connected with the node C1, and the grid of the NMOS tube N4B is connected with the node C2.
Fig. 3 is the circuit theory schematic diagram of the prefix logic circuit of the present invention.The prefix logic circuit is patrolled including first
Collect circuit, the second logic circuit, the 3rd logic circuit, the 4th logic circuit, first logic circuit, second logic electricity
Road, the 3rd logic circuit, the 4th logic circuit are respectively connected with each other and formed by 2 PMOSs, 2 NMOS tubes,
Input termination data input in, the clock input clock and clock of first logic circuit□, first logic circuit
The output termination node B1；Input termination data input in, the clock input clock and clock of second logic circuit□, the output termination node B2 of second logic circuit；The input termination data input in of 3rd logic circuit□、
Clock inputs clock and clock□, the output termination node C1 of the 3rd logic circuit；4th logic circuit
Input termination data input in□, clock input clock and clock□, the output termination node of the 4th logic circuit
C2。
The operation principle of the present invention：The latch structure that a kind of anti-SEU of the present invention is reinforced includes data write operation and guarantor
Hold operation.Data write operation is：(1) as clock and clock□Respectively high level and during low level, if in is high level,
Then in□For low level, B1 and B2 are respectively low level, and C1 and C2 are respectively high level；(2) when clock and clock are respectively
When high level and low level, if in is low level, in□For high level, then B1 and B2 is high level, and C1 and C2 is low electricity
It is flat.It is the circuit conditions under clock and clock is respectively low level and high level to keep operation.
The present invention has the anti-SEU immunitys of single node, because the present invention has symmetry, and following section is worked as in only analysis
Anti- SEU characteristics when point A, B1, B2, C1, C2, D are respectively logic 1,0,0,1,1,0, make a concrete analysis of as follows.
The first situation：Node B1 is hit the transient pulse for occurring 0 → 1 by high energy particle.NMOS tube N1A is become by cut-off
To turn on, but because NMOS tube N1B still ends, so node A will not be overturn.On the other hand, even if B1 negative transient state
Pulse enables to N3A conductings and therefore pulling down node C1 logic level, but this can only allow NMOS tube N4A cut-offs to change
Become node D level, so node D floatings are in high-impedance state, Fig. 4 is circuit theory when node B1 of the invention is overturn
Schematic diagram.
Second of situation：Node B2 is hit the transient pulse for occurring 0 → 1 by high energy particle.NMOS tube N1B is become by cut-off
To turn on, but it is due to that NMOS tube N1A still ends, so node A will not be overturn.On the other hand, even if B2 negative wink
State pulse enables to N3B conductings and therefore pulling down node C2 logic level, but this can only allow NMOS tube N4B cut-offs can't
Concept transfer D level, so node D floatings are in high-impedance state, Fig. 5 is that circuit when node B2 of the invention is overturn is former
Manage schematic diagram.
The third situation：Node C1 is hit the transient pulse for occurring 1 → 0 by high energy particle.It is when node C1 is overturn from 1
When 0, NMOS tube N2A is changed into cut-off from turning on, so node B1 floatings but can't overturn.Likewise, NMOS tube N4A is by turning on
It is changed into cut-off, also only makes node D floatings, Fig. 6 is circuit theory schematic diagram when node C1 of the invention is overturn.
4th kind of situation：Node C2 is hit the transient pulse for occurring 1 → 0 by high energy particle.It is when node C2 is overturn by 1
When 0, NMOS tube N2B is changed into cut-off from turning on, so node B2 floatings but can't overturn.Likewise, NMOS tube N4B is by turning on
It is changed into cut-off, also makes node D floatings, Fig. 7 is circuit theory schematic diagram when node C2 of the invention is overturn.
5th kind of situation：Node A is hit the transient pulse for occurring 1 → 0 by high energy particle.If node A is by high energy
The strike of particle, the transient pulse for occurring 1 → 0, and PMOS P2A may be caused to turn on, but because node C1 makes for high level
NMOS tube N2A conductings are obtained, and NMOS tube N2A has the driving force higher than PMOS P2A, node B1 can't be overturn.Together
Sample, node B2 and node D will not also be overturn, and finish node A level recovers, and the node A that Fig. 8 is the present invention is overturn
When circuit theory schematic diagram.
6th kind of situation：Node D is hit the transient pulse for occurring 0 → 1 by high energy particle.If node D is by high energy grain
The strike of son, it is 1 that node D transient pulse is overturn by 0, only ends PMOS P3A, P3B, and cause node C1, node C2
Floating, can't produce level upset, and Fig. 9 is circuit theory schematic diagram when node D of the invention is overturn.
In summary, the upset of each redundant storage node is all without the upset for causing other any nodes, so that
Whole latch structure will not be overturn, and the present invention is a latch structure that there is single node SEU to be immunized, and the present invention is solved
The problem of anti-SEU.
Described above is only the preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, some improvement and deformation can also be made, these improve and deformed
Also it should be regarded as protection scope of the present invention.
Claims (8)
1. the latch structure that a kind of anti-SEU is reinforced, it is characterised in that including memory cell, prefix logic circuit, the storage
Unit includes tie point, the second branch road, the 3rd branch road, the 4th branch road, the 5th branch road, the 6th branch road, and the memory cell is also
Including node A, node B1, node B2, node C1, node C2, node D, the node A is arranged in the tie point, institute
State node B1 to be arranged on second branch road, the node B2 is arranged on the 3rd branch road, the node C1 is arranged at
On 4th branch road, the node C2 is arranged on the 5th branch road, and the node D is arranged on the 6th branch road,
The tie point is connected by the node A with second branch road, the 3rd branch road, the 6th branch road, described
Second branch road is connected with the tie point, the 4th branch road respectively by the node B1, and the 3rd branch road passes through
The node B2 is connected with the tie point, the 5th branch road respectively, and the 4th branch road passes through the node C1 points
It is not connected with second branch road, the 6th branch road, the 5th branch road is by the node C2 respectively with the described 3rd
Branch road, the 6th branch road are connected, the 6th branch road by the node D respectively with the 4th branch road, the described 5th
Branch road, the tie point are connected, the output end of the prefix logic circuit respectively with the node B1, the node B2,
The node C1, the node C2 are connected.
2. the latch structure that a kind of anti-SEU according to claim 1 is reinforced, it is characterised in that the tie point bag
Tie point power supply, PMOS P1, NMOS tube N1A, NMOS tube N1B are included, the tie point power supply is with the PMOS P1's
Source electrode is connected, and the drain electrode of the PMOS P1 is sequentially connected the node A, the drain electrode of the NMOS tube N1A, the NMOS tube
N1A source electrode is connected with the drain electrode of the NMOS tube N1B, the source ground of the NMOS tube N1B, the grid of the PMOS P1
Pole is connected with the node D, and the grid of the NMOS tube N1A is connected with the node B1, the grid of the NMOS tube N1B
It is connected with the node B2.
3. the latch structure reinforced according to a kind of any described anti-SEU of claim 1 or 2, it is characterised in that described second
Branch road includes the second branch road power supply, PMOS P2A, NMOS tube N2A, the source of the second branch road power supply and the PMOS P2A
Pole is connected, and the drain electrode of the PMOS P2A is sequentially connected the node B1, the drain electrode of the NMOS tube N2A, the NMOS tube
N2A source ground, the grid of the PMOS P2A is connected with the node A, the grid of the NMOS tube N2A with it is described
Node C1 is connected.
4. the latch structure reinforced according to a kind of any described anti-SEU of claims 1 to 3, it is characterised in that the described 3rd
Branch road includes the 3rd branch road power supply, PMOS P2B, NMOS tube N2B, the source of the 3rd branch road power supply and the PMOS P2B
Pole is connected, and the drain electrode of the PMOS P2B is sequentially connected the node B2, the drain electrode of the NMOS tube N2B, the NMOS tube
N2B source ground, the grid of the PMOS P2B is connected with the node A, the grid of the NMOS tube N2B with it is described
Node C2 is connected.
5. the latch structure reinforced according to a kind of any described anti-SEU of Claims 1-4, it is characterised in that the described 4th
Branch road includes the 4th branch road power supply, PMOS P3A, NMOS tube N3A, the source of the 4th branch road power supply and the PMOS P3A
Pole is connected, and the drain electrode of the PMOS P3A is sequentially connected the node C1, the drain electrode of the NMOS tube N3A, the NMOS tube
N3A source ground, the grid of the PMOS P3A is connected with the node D, the grid of the NMOS tube N3A with it is described
Node B1 is connected.
6. the latch structure reinforced according to a kind of any described anti-SEU of claim 1 to 5, it is characterised in that the described 5th
Branch road includes the 5th branch road power supply, PMOS P3B, NMOS tube N3B, the source of the 5th branch road power supply and the PMOS P3B
Pole is connected, and the drain electrode of the PMOS P3B is sequentially connected the node C2, the drain electrode of the NMOS tube N3B, the NMOS tube
N3B source ground, the grid of the PMOS P3B is connected with the node D, the grid of the NMOS tube N3B with it is described
Node B2 is connected.
7. the latch structure reinforced according to a kind of any described anti-SEU of claim 1 to 6, it is characterised in that the described 6th
Branch road includes the 6th branch road power supply, PMOS P4, NMOS tube N4A, NMOS tube N4B, the 6th branch road power supply and the PMOS
Pipe P4 source electrode is connected, and the drain electrode of the PMOS P4 is sequentially connected the node D, the drain electrode of the NMOS tube N4A, described
NMOS tube N4A source electrode is connected with the drain electrode of the NMOS tube N4B, the source ground of the NMOS tube N4B, the PMOS
P4 grid is connected with the node A, and the grid of the NMOS tube N4A is connected with the node C1, the NMOS tube N4B
Grid be connected with the node C2.
8. the latch structure reinforced according to a kind of any described anti-SEU of claim 1 to 7, it is characterised in that described preposition
Logic circuit includes the first logic circuit, the second logic circuit, the 3rd logic circuit, the 4th logic circuit, first logic
Circuit, second logic circuit, the 3rd logic circuit, the 4th logic circuit respectively by 2 PMOSs, 2
NMOS tube is connected with each other and formed, the input of first logic circuit termination data input in, clock input clock andThe output of first logic circuit terminates the node B1；The input terminating data of second logic circuit is defeated
Enter in, clock input clock andThe output of second logic circuit terminates the node B2；3rd logic
The input termination data input of circuitClock input clock andThe output termination institute of 3rd logic circuit
State node C1；The input termination data input of 4th logic circuitClock input clock andDescribed 4th
The output of logic circuit terminates the node C2.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610878141.2A CN106971753B (en) | 2017-01-09 | 2017-01-09 | A kind of latch structure that anti-SEU is reinforced |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610878141.2A CN106971753B (en) | 2017-01-09 | 2017-01-09 | A kind of latch structure that anti-SEU is reinforced |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106971753A true CN106971753A (en) | 2017-07-21 |
| CN106971753B CN106971753B (en) | 2019-06-04 |
Family
ID=59334816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610878141.2A Active CN106971753B (en) | 2017-01-09 | 2017-01-09 | A kind of latch structure that anti-SEU is reinforced |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106971753B (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108320766A (en) * | 2018-02-05 | 2018-07-24 | 上海华虹宏力半导体制造有限公司 | The high-performance double interlocking memory cell of soft fault preventing |
| CN111969998A (en) * | 2020-08-03 | 2020-11-20 | 河海大学常州校区 | Latch structure capable of resisting single event upset |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122950A (en) * | 2011-01-10 | 2011-07-13 | 深圳市国微电子股份有限公司 | High-speed low-power consumption latch device capable of resisting SEU (single event upset) |
| CN104022773A (en) * | 2014-06-24 | 2014-09-03 | 河海大学常州校区 | DICE (dual interlocked storage cell)-based novel SEU (single event upset)-resistant reinforced SR latch |
| US9281807B1 (en) * | 2014-06-09 | 2016-03-08 | Xilinx, Inc. | Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit |
-
2017
- 2017-01-09 CN CN201610878141.2A patent/CN106971753B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102122950A (en) * | 2011-01-10 | 2011-07-13 | 深圳市国微电子股份有限公司 | High-speed low-power consumption latch device capable of resisting SEU (single event upset) |
| US9281807B1 (en) * | 2014-06-09 | 2016-03-08 | Xilinx, Inc. | Master-slave flip-flops and methods of implementing master-slave flip-flops in an integrated circuit |
| CN104022773A (en) * | 2014-06-24 | 2014-09-03 | 河海大学常州校区 | DICE (dual interlocked storage cell)-based novel SEU (single event upset)-resistant reinforced SR latch |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108320766A (en) * | 2018-02-05 | 2018-07-24 | 上海华虹宏力半导体制造有限公司 | The high-performance double interlocking memory cell of soft fault preventing |
| CN111969998A (en) * | 2020-08-03 | 2020-11-20 | 河海大学常州校区 | Latch structure capable of resisting single event upset |
| CN111969998B (en) * | 2020-08-03 | 2022-10-04 | 河海大学常州校区 | Latch structure capable of resisting single event upset |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106971753B (en) | 2019-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN104124971B (en) | Two-stage flow-line modulus converter based on Approach by inchmeal principle | |
| CN103633990B (en) | A kind of anti-single particle upset and the adjustable latch of transient effect time delay | |
| CN103956184B (en) | A kind of improvement SRAM memory cell based on DICE structure | |
| CN106971753A (en) | The latch structure that a kind of anti-SEU is reinforced | |
| TW201251332A (en) | Level shifter | |
| WO2019085617A1 (en) | Voltage-controlled magnetic anisotropy magnetic random access memory and determining method therefor | |
| CN106849913A (en) | The binode upset restoration-online latch of high-performance low overhead | |
| CN109669823B (en) | Multi-bit upset error resisting chip reinforcement method based on improved triple modular redundancy system | |
| CN104022773A (en) | DICE (dual interlocked storage cell)-based novel SEU (single event upset)-resistant reinforced SR latch | |
| CN105047130B (en) | A kind of shifting deposit unit and its driving method, gate driving circuit | |
| CN104464795B (en) | A kind of primary particle inversion resistant static ram cell | |
| CN100471062C (en) | CMOS symmetrical output SR flip-latch with self-correction function | |
| CN103632715A (en) | Two-module redundancy configuration memory unit circuit used in programmable logic device | |
| CN104637530A (en) | Random access memory with redundant structure | |
| CN103677052B (en) | A kind of band-gap reference of anti-single particle effect | |
| CN105869672B (en) | A kind of non-volatile FPGA programming dot circuits and its operating method based on RRAM | |
| CN103076832B (en) | Self-biased current source | |
| CN102957415B (en) | Level converting method and level converting system | |
| CN104897949B (en) | Voltage detecting circuit | |
| CN106059565A (en) | Novel SR latch resisting single event upset | |
| CN107634755A (en) | Majority logic door structure circuit | |
| CN104795089B (en) | Control method for low-power two-stage amplifier STT-RAM (spin transfer torque-random access memory) reading circuit | |
| CN104795095B (en) | STT RAM reading circuits and control method based on collapsible comparator | |
| CN208299780U (en) | A kind of FG gate circuit applied to reversible logic circuits | |
| Onizawa et al. | Redundant STT-MTJ-based nonvolatile flip-flops for low write-error-rate operations |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |