CN106970673B - A kind of reference circuit with wide input supply district characteristic - Google Patents
A kind of reference circuit with wide input supply district characteristic Download PDFInfo
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- CN106970673B CN106970673B CN201710285790.6A CN201710285790A CN106970673B CN 106970673 B CN106970673 B CN 106970673B CN 201710285790 A CN201710285790 A CN 201710285790A CN 106970673 B CN106970673 B CN 106970673B
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- pmos tube
- npn triode
- tube
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- resistance
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
- G05F1/10—Regulating voltage or current
- G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
- G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
- G05F1/561—Voltage to current converters
Abstract
The invention belongs to technical field of integrated circuits, particularly relates to a kind of reference circuit with wide input supply district characteristic.Relative to general reference circuit, reference circuit proposed by the present invention uses the framework of LDO (low pressure difference linear voltage regulator), realizes the purpose in the case of width input supply voltage (such as 10 48V), remaining to normal work.Secondly, it is used for high reference circuit in the case of inputting supply voltage (such as 10 48V) compared to others, reference circuit proposed by the present invention employs a kind of novel frequency compensated manner, so as to the bandwidth for having expanded system largely, the problem of power consumption low bandwidth is small in traditional design is overcome, realizes the mesh that speed is fast, low in energy consumption.
Description
Technical field
The invention belongs to technical field of integrated circuits, particularly relate to a kind of there is wide input supply district characteristic
Reference circuit.
Background technology
In semiconductor integrated circuit, reference circuit is a kind of indispensable important module, it is chip internal circuits
Reference voltage is provided.In the case of low-voltage power supply (being less than or equal to 5V), reference circuit technology is comparatively more mature.
In the case of higher power supply (such as 10-48V), reference circuit technology is also there is a series of problem, for example circuit structure is more
Complexity, power consumption are larger or speed is slower etc..In the case of high supply voltage, normally due to limitation (such as three poles of process conditions
Pipe it is pressure-resistant etc.), reference circuit can not be integrated directly on power rail, thus it is general can all first pass through a linear voltage regulator or
Stabilized input voltage on a relatively low and stable point (such as 5V), is integrated benchmark by Zener diode at that point afterwards
Voltage module.And if using individually integrate a linear voltage regulator scheme, can undoubtedly increase circuit complexity and
Cost, therefore the scheme for integrating reference generating circuit and linear voltage regulator can be used in many cases, and this side
Then there is the limitation of obvious power consumption or speed for case.In general, this scheme is under conditions of low-power consumption (such as 1 microampere),
Its bandwidth only has hundreds of kHz to several megahertzs.
The content of the invention
The purpose of the present invention is be to solve in the case where width inputs supply district (such as 10-48V), in chip integration
A kind of the problem of existing circuit structure is complicated during into reference circuit, power consumption is larger or speed is relatively low, it is proposed that wide input power supply
Scope high-speed low-power-consumption reference circuit.
The technical scheme is that：As shown in figure 4, a kind of reference circuit with wide input supply district characteristic, bag
Include start-up circuit, electrification reset circuit, benchmark core circuit；It is characterized in that,
The start-up circuit by the first PMOS tube MP1, the second PMOS tube MP2, first resistor R1, the first NPN triode N1,
Second NPN triode N2, second resistance R2 are formed；The source electrode of first PMOS tube MP1 connects power supply, the grid of the first PMOS tube MP1
The drain electrode of the first PMOS tube MP1 is connect, the drain electrode of the first PMOS tube MP1 connects the source electrode of the second PMOS tube MP2；Second PMOS tube MP2
Grid connect the drain electrode of the second PMOS tube MP2, the drain electrode of the second PMOS tube connects the first NPN triode N1's by first resistor R1
Collector；The collector of first NPN triode N1 connects the base stage of the first NPN triode N1, and the base stage of the first NPN triode N1 connects
The base stage of second NPN triode N2, the emitter ground connection of the first NPN triode N1；The emitter of second NPN triode N2 passes through
Second resistance R2 is grounded；
The electrification reset circuit is by the 3rd NPN triode N3, the first NMOS tube MN1, the 7th PMOS tube MP7, the 3rd electricity
R3 is hindered to form；The emitter of 3rd NPN triode N3 is grounded by second resistance R2, and the base stage of the 3rd NPN triode N3 connects
The base stage of one NPN triode N1, the collector of the 3rd NPN triode N3 meet drain electrode and the first NMOS of the 7th PMOS tube MP7
The grid of pipe MN1；The drain electrode of first NMOS tube MN1 connects power supply, the source electrode ground connection of the first NMOS tube MN1 by 3rd resistor R3；
The benchmark core circuit is by the 3rd PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS
Pipe MP6, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4,
4th NPN triode N4, the 5th NPN triode N5, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7,
8th resistance R8, the first capacitance C1, the second capacitance C2 are formed；The source electrode of 3rd PMOS tube MP3 meets power supply, the 3rd PMOS tube MP3
Grid connect the 4th PMOS tube MP4 grid and the 3rd PMOS tube MP3 drain electrode, the drain electrode of the 3rd PMOS tube MP3 connects the 5th
The source electrode of PMOS tube MP5；The source electrode of 4th PMOS tube MP4 connects power supply, and the drain electrode of the 4th PMOS tube MP4 meets the 6th PMOS tube MP6
Source electrode；The grid of 5th PMOS tube MP5 connects the drain electrode of the grid and the 5th PMOS tube MP5 of the 6th PMOS tube MP6, and the 5th
The drain electrode of PMOS tube MP5 connects the drain electrode of the collector and the 4th NMOS tube MN4 of the second NPN triode N2；6th PMOS tube MP6
Drain electrode be grounded by the second capacitance C2, the drain electrode of the 6th PMOS tube MP6 passes sequentially through the 6th resistance R6, the 7th resistance R7, the
Eight resistance R8 ground connection, the drain electrode of the 6th PMOS tube MP6 connect the source electrode of the 7th PMOS tube MP7；The source electrode of 8th PMOS tube MP8 connects
The drain electrode of six PMOS tube MP6, the grid of the 8th PMOS tube MP8 connect the grid and the 9th PMOS tube MP9 of the 7th PMOS tube MP7
Grid, the drain electrode of the 8th PMOS tube MP8 connect the drain electrode of the second NMOS tube MN2 and the grid of the 4th NMOS tube MN4；9th PMOS
The source electrode of pipe MP9 connects the drain electrode of the 6th PMOS tube MP6, and the grid of the 9th PMOS tube MP9 connects the drain electrode of the 9th PMOS tube MP9, the
The drain electrode of nine PMOS tube MP9 connects the drain electrode of the 3rd NMOS tube MN3；The grid of second NMOS tube MN2 connects the grid of the 3rd NMOS tube MN3
Pole, the source electrode of the second NMOS tube MN2 connect the collector of the 4th NPN triode N4；The grid of 3rd NMOS tube MN3 passes through the 6th electricity
Resistance R6 connects the drain electrode of the 6th PMOS tube MP6, and the source electrode of the 3rd NMOS tube MN3 connects the collector of the 5th NPN triode N5；4th
The drain electrode of NMOS tube MN4 connects the collector of the 4th NPN triode N4 by the first capacitance C1, and the source electrode of the 4th NMOS tube MN4 leads to
Cross second resistance R2 ground connection；The base stage of 4th NPN triode N4 meets the base stage of the 5th NPN triode N5, the 4th NPN triode N4
Emitter be grounded by resistance R5；The base stage of 5th NPN triode N5 is grounded by the 8th resistance R8, the 5th NPN triode
Emitter pass sequentially through the 4th resistance R4, the 5th resistance R5 ground connection；
3rd resistor R3, the tie point of the first NMOS tube MN1 are power-on reset signal POR output ports；6th PMOS tube
MP6, the 7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the second capacitance C2, the tie point of the 6th resistance R6 are
Reference voltage REF_1 output ports；4th NPN triode N4, the 5th NPN triode N5, the 7th resistance R7, the 8th resistance R8
Tie point is reference voltage REF_BG output ports.
The beneficial effects of the invention are as follows：Relative to general reference circuit, reference circuit proposed by the present invention uses LDO
The framework of (low pressure difference linear voltage regulator), realizes in the case of width input supply voltage (such as 10-48V), remains to normal work
The purpose of work.Secondly, it is used for high reference circuit in the case of inputting supply voltage (such as 10-48V), the present invention compared to others
The reference circuit of proposition employs a kind of novel frequency compensated manner, so that the bandwidth for having expanded system largely,
The problem of power consumption low bandwidth is small in traditional design is overcome, realizes the mesh that speed is fast, low in energy consumption.
Brief description of the drawings
Fig. 1 is the system architecture diagram of the present invention；
Fig. 2 is traditional frequency compensated manner；
Fig. 3 is a kind of novel frequency compensated manner proposed by the present invention；
Fig. 4 is a kind of concrete implementation circuit diagram of reference circuit proposed by the present invention；
Fig. 5 is the frequency response characteristic of system when not doing frequency compensation；
Fig. 6 is the frequency response characteristic of traditional frequency compensated manner；
Fig. 7 is the frequency response characteristic of reference circuit proposed by the present invention；
Fig. 8 is the operating voltage simulation curve of reference circuit proposed by the present invention.
Embodiment
The present invention is described in detail below in conjunction with the accompanying drawings.
Fig. 1 is the system architecture diagram of the present invention.As shown in the figure, reference circuit proposed by the present invention is used produces electricity by benchmark
The scheme that road is combined together with linear voltage regulator, they collectively form LDO (low pressure difference linear voltage regulator) module.In LDO moulds
On the basis of block, start-up circuit and electrification reset circuit are added in scheme proposed by the present invention.The wherein mesh of start-up circuit
Be allow reference circuit proposed by the present invention to establish appropriate operating point, electrification reset circuit during powering on
It is then the signal whether established for output reference voltage, to ensure the normal work of other modular circuits.
Fig. 2 is traditional frequency compensated manner for reference circuit framework proposed by the present invention.It is as shown in the figure, traditional
Frequency compensated manner is the grid addition compensating electric capacity C1 in LDO adjustment pipes MN1, and this compensation way can seriously limit whole system
The bandwidth of system, so as to influence the speed and power consumption of system.
Fig. 3 is a kind of novel frequency compensated manner proposed by the present invention.As shown in the figure, frequency compensation proposed by the present invention
Mode, is to add compensating electric capacity C1 between the output of LDO adjustment pipe MN1 and the input of LDO, so as to greatly expand and be
The bandwidth of system, improves the speed of system, while reduces the power consumption of system.
Fig. 4 is a kind of concrete implementation circuit diagram of reference circuit proposed by the present invention, and specific connection relation is being sent out
Had been described in bright content, details are not described herein.
The present invention operation principle be：
Start-up circuit：The purpose of start-up circuit is to make circuit break away from system degeneracy bias point during powering on, drives
Circuit is set to establish appropriate bias point, so that circuit works normally.As shown in figure 4, the start-up circuit of the present invention is by first
PMOS tube MP1, the second PMOS tube MP2, first resistor R1, the first NPN triode N1, the electricity of the second NPN triode N2 and second
R2 is hindered to form.During system electrification, when VCC is higher than the threshold voltage of N1, N1 is begun to turn on, so that MP3, MP5,
The circuit that N2, R2 are formed also begins to work, finally so that whole circuit enters normal working point.When system enters normal working point
Afterwards, due to the partial pressure of resistance R2 so that N2 is turned off, so as to reduce system power consumption.
Electrification reset circuit：The purpose of electrification reset circuit is to detect whether reference circuit has built up.Such as Fig. 4 institutes
Show, electrification reset circuit of the invention is by the 3rd NPN triode N3, the 7th PMOS tube MP7, the first NMOS tube MN1 and the 3rd
Resistance R3 is formed.The design philosophy that the electrification reset circuit of the present invention compares using electric current.During system electrification,
Due to the conducting of N1 so that N2 and N3 are also switched on, so that MN1 is turned off, por signal output high level.When system enters
After normal operating point, reference circuit is started to work, and current mirror MP7, MP8, MP9 start to work normally, so that the grid by MN1
Pole level puts height so that MN1 is turned on, and por signal output is low level, completes electrification reset process.Simultaneously as resistance R2
Partial pressure acts on so that N3 is turned off, so as to reduce system power dissipation.
Benchmark core circuit：The benchmark core circuit of the present invention includes reference generating circuit and linear voltage regulator, they
Collectively form the LDO modules in Fig. 1.As shown in figure 4, the output of wherein reference generating circuit is：
Wherein, VBE4For the base stage and emitter voltage of N4, there is negative temperature coefficient.(VBE4-VBE5) for N4 and N5 base stage with
The difference of emitter voltage, has positive temperature coefficient.By rationally setting the ratio before R4 and R5, it is possible to obtain a temperature system
The preferable reference voltage of number.In addition, the value by rationally setting R4 and R5, can cause the power consumption of reference generating circuit greatly
Reduce.And the resistance pressure-dividing network being made of R6, R7, R8, then it can obtain the reference voltages of various different values.
As shown in Figure 1, in LDO modules, after adjustment pipe MN1 is by sampling the voltage of reference generating circuit, lead to
Cross after the current mirror that MP1 and MP2 is formed and feed back to reference generating circuit, so as to maintain the stability of reference generating circuit.
In LDO systems, there is two important limits, and one positioned at output terminal REF_1, a grid positioned at adjustment pipe MN1.By
System stability principle understands that, when system is there is during two or more limits, there may be stability problem for system.
As shown in figure 5, giving the system intrinsic frequency response characteristic, thus demonstrate system mentioned above and there is stabilization
The conclusion of sex chromosome mosaicism.On the other hand, the intrinsic bandwidth that we can obtain the system is about several megahertzs.
As shown in Fig. 2, give traditional frequency compensated manner.During using this kind of compensation way, in order to reduce system
Power consumption, the electric current of start-up circuit must very little.On the other hand, due to the addition of MN1 grid compensating electric capacities C1, the grid of MN1 are made
Appropriate operating point is established in pole, it is necessary to charges to compensating electric capacity C1, reaches appropriate voltage.Since system starts electricity
Stream is smaller, therefore the settling time of the point is very long, so as to significantly limit the operating rate of system.Adopted as shown in fig. 6, giving
During with traditional frequency compensated manner, the frequency response characteristic of system, its bandwidth only has hundreds of kHz, so as to demonstrate
The traditional compensation way mentioned in the above process can greatly reduce the conclusion of the speed of system.
As shown in figure 3, give a kind of novel frequency compensated manner proposed by the present invention.Compensation side proposed by the present invention
Formula is by adding feedforward path between the output of adjustment pipe MN1 of LDO and the input signal of reference generating circuit.Upper
In the process of electricity, the output added from adjustment pipe MN1 passes through compensating electric capacity C1 to the path on ground, so that in power up
Electric current be no longer limited by start-up circuit, so as to dramatically improve the speed of system.As shown in fig. 7, give this hair
The frequency response characteristic of the reference circuit of bright proposition, its bandwidth are up to tens megahertzs, it is achieved thereby that in low-power consumption
Precondition is issued to the purpose of high speed.
Fig. 5 is the frequency response characteristic of system when reference circuit framework proposed by the present invention does not add frequency compensation.Such as
Shown in figure, when not doing frequency compensation, there are stability problem for system, it is therefore necessary to carries out frequency compensation to system.
Fig. 6 is the frequency response characteristic of traditional frequency compensated manner.As shown in the figure, using traditional frequency compensation
During mode, the bandwidth of system only has hundreds of kHz.
Fig. 7 is the frequency response characteristic of reference circuit proposed by the present invention.As shown in the figure, in equal consumption conditions
Under, the bandwidth of reference circuit proposed by the present invention can reach tens megahertzs, dramatically improve the speed of system.
As shown in figure 8, give the dc simulation curves of the input supply voltage of reference circuit proposed by the present invention.The present invention
The reference circuit of proposition by using LDO framework so that it adapts to the requirement of wide input supply district.It can be obtained by Fig. 7,
Its input supply district of reference circuit proposed by the present invention can reach 10-48V, thus demonstrate wide input proposed by the present invention
The requirement of supply district.
It in summary it can be seen, a kind of technology of wide input supply district high-speed low-power-consumption reference circuit proposed by the present invention is excellent
Point：Relative to general reference circuit, reference circuit of the invention realizes the purpose of wide input supply district (such as 10-48V).
Compared to other reference circuits in the case of high supply voltage (such as 10-48V), reference circuit proposed by the present invention is adopted
With a kind of novel frequency compensated manner, it is achieved thereby that the precondition in low-power consumption is issued to the purpose of high speed.Specifically
For, under conditions of identical power consumption (such as 1 microampere), the system bandwidth of traditional reference circuit only has hundreds of kHz to several million
Hertz, and reference circuit proposed by the present invention its bandwidth can reach tens megahertzs, so as to dramatically improve system
Speed.
Claims (1)
1. a kind of reference circuit with wide input supply district characteristic, including start-up circuit, electrification reset circuit, benchmark core
Circuit；It is characterized in that,
The start-up circuit is by the first PMOS tube MP1, the second PMOS tube MP2, first resistor R1, the first NPN triode N1, second
NPN triode N2, second resistance R2 are formed；The source electrode of first PMOS tube MP1 connects power supply, and the grid of the first PMOS tube MP1 connects
The drain electrode of one PMOS tube MP1, the drain electrode of the first PMOS tube MP1 connect the source electrode of the second PMOS tube MP2；The grid of second PMOS tube MP2
Pole connects the drain electrode of the second PMOS tube MP2, and the drain electrode of the second PMOS tube connects the current collection of the first NPN triode N1 by first resistor R1
Pole；The collector of first NPN triode N1 connects the base stage of the first NPN triode N1, and the base stage of the first NPN triode N1 connects second
The base stage of NPN triode N2, the emitter ground connection of the first NPN triode N1；The emitter of second NPN triode N2 passes through second
Resistance R2 is grounded；
The electrification reset circuit is by the 3rd NPN triode N3, the first NMOS tube MN1, the 7th PMOS tube MP7,3rd resistor R3
Form；The emitter of 3rd NPN triode N3 is grounded by second resistance R2, and the base stage of the 3rd NPN triode N3 meets the first NPN
The base stage of triode N1, the collector of the 3rd NPN triode N3 meet drain electrode and the first NMOS tube MN1 of the 7th PMOS tube MP7
Grid；The drain electrode of first NMOS tube MN1 connects power supply, the source electrode ground connection of the first NMOS tube MN1 by 3rd resistor R3；
The benchmark core circuit is by the 3rd PMOS tube MP3, the 4th PMOS tube MP4, the 5th PMOS tube MP5, the 6th PMOS tube
MP6, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4,
Four NPN triode N4, the 5th NPN triode N5, the 4th resistance R4, the 5th resistance R5, the 6th resistance R6, the 7th resistance R7,
Eight resistance R8, the first capacitance C1, the second capacitance C2 are formed；The source electrode of 3rd PMOS tube MP3 connects power supply, the 3rd PMOS tube MP3's
Grid connects the drain electrode of the grid and the 3rd PMOS tube MP3 of the 4th PMOS tube MP4, and the drain electrode of the 3rd PMOS tube MP3 connects the 5th
The source electrode of PMOS tube MP5；The source electrode of 4th PMOS tube MP4 connects power supply, and the drain electrode of the 4th PMOS tube MP4 meets the 6th PMOS tube MP6
Source electrode；The grid of 5th PMOS tube MP5 connects the drain electrode of the grid and the 5th PMOS tube MP5 of the 6th PMOS tube MP6, and the 5th
The drain electrode of PMOS tube MP5 connects the drain electrode of the collector and the 4th NMOS tube MN4 of the second NPN triode N2；6th PMOS tube MP6
Drain electrode be grounded by the second capacitance C2, the drain electrode of the 6th PMOS tube MP6 passes sequentially through the 6th resistance R6, the 7th resistance R7, the
Eight resistance R8 ground connection, the drain electrode of the 6th PMOS tube MP6 connect the source electrode of the 7th PMOS tube MP7；The source electrode of 8th PMOS tube MP8 connects
The drain electrode of six PMOS tube MP6, the grid of the 8th PMOS tube MP8 connect the grid and the 9th PMOS tube MP9 of the 7th PMOS tube MP7
Grid, the drain electrode of the 8th PMOS tube MP8 connect the drain electrode of the second NMOS tube MN2 and the grid of the 4th NMOS tube MN4；9th PMOS
The source electrode of pipe MP9 connects the drain electrode of the 6th PMOS tube MP6, and the grid of the 9th PMOS tube MP9 connects the drain electrode of the 9th PMOS tube MP9, the
The drain electrode of nine PMOS tube MP9 connects the drain electrode of the 3rd NMOS tube MN3；The grid of second NMOS tube MN2 connects the grid of the 3rd NMOS tube MN3
Pole, the source electrode of the second NMOS tube MN2 connect the collector of the 4th NPN triode N4；The grid of 3rd NMOS tube MN3 passes through the 6th electricity
Resistance R6 connects the drain electrode of the 6th PMOS tube MP6, and the source electrode of the 3rd NMOS tube MN3 connects the collector of the 5th NPN triode N5；4th
The drain electrode of NMOS tube MN4 connects the collector of the 4th NPN triode N4 by the first capacitance C1, and the source electrode of the 4th NMOS tube MN4 leads to
Cross second resistance R2 ground connection；The base stage of 4th NPN triode N4 meets the base stage of the 5th NPN triode N5, the 4th NPN triode N4
Emitter be grounded by resistance R5；The base stage of 5th NPN triode N5 is grounded by the 8th resistance R8, the 5th NPN triode
Emitter pass sequentially through the 4th resistance R4, the 5th resistance R5 ground connection；
3rd resistor R3, the tie point of the first NMOS tube MN1 are power-on reset signal POR output ports；6th PMOS tube MP6,
7th PMOS tube MP7, the 8th PMOS tube MP8, the 9th PMOS tube MP9, the second capacitance C2, the tie point of the 6th resistance R6 are reference
Voltage REF_1 output ports；The connection of 4th NPN triode N4, the 5th NPN triode N5, the 7th resistance R7, the 8th resistance R8
Point is reference voltage REF_BG output ports.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710285790.6A CN106970673B (en) | 2017-04-27 | 2017-04-27 | A kind of reference circuit with wide input supply district characteristic |
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| CN201710285790.6A CN106970673B (en) | 2017-04-27 | 2017-04-27 | A kind of reference circuit with wide input supply district characteristic |
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| CN106970673B true CN106970673B (en) | 2018-04-13 |
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| CN107861554B (en) * | 2017-10-26 | 2019-07-12 | 西安微电子技术研究所 | The circuit for starting up band gap basis and method of wide power range are used for based on Flouride-resistani acid phesphatase bipolar process |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1287294A (en) * | 1999-09-02 | 2001-03-14 | 深圳赛意法微电子有限公司 | Band-gap reference circuit |
| CN101329586A (en) * | 2007-06-19 | 2008-12-24 | 凹凸电子（武汉）有限公司 | Reference voltage generator and method for providing multiple reference voltages |
| US7633334B1 (en) * | 2005-01-28 | 2009-12-15 | Marvell International Ltd. | Bandgap voltage reference circuit working under wide supply range |
| CN102053645A (en) * | 2011-01-31 | 2011-05-11 | 成都瑞芯电子有限公司 | Wide-input voltage high-power supply rejection ratio reference voltage source |
| CN104122918A (en) * | 2013-04-26 | 2014-10-29 | 中国科学院深圳先进技术研究院 | Band-gap reference circuit |
| CN106406412A (en) * | 2016-11-23 | 2017-02-15 | 电子科技大学 | Band-gap reference circuit with high-order temperature compensation |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP5637096B2 (en) * | 2011-08-10 | 2014-12-10 | 株式会社デンソー | Band gap reference voltage circuit and power-on reset circuit using the same |
-
2017
- 2017-04-27 CN CN201710285790.6A patent/CN106970673B/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1287294A (en) * | 1999-09-02 | 2001-03-14 | 深圳赛意法微电子有限公司 | Band-gap reference circuit |
| US7633334B1 (en) * | 2005-01-28 | 2009-12-15 | Marvell International Ltd. | Bandgap voltage reference circuit working under wide supply range |
| CN101329586A (en) * | 2007-06-19 | 2008-12-24 | 凹凸电子（武汉）有限公司 | Reference voltage generator and method for providing multiple reference voltages |
| CN102053645A (en) * | 2011-01-31 | 2011-05-11 | 成都瑞芯电子有限公司 | Wide-input voltage high-power supply rejection ratio reference voltage source |
| CN104122918A (en) * | 2013-04-26 | 2014-10-29 | 中国科学院深圳先进技术研究院 | Band-gap reference circuit |
| CN106406412A (en) * | 2016-11-23 | 2017-02-15 | 电子科技大学 | Band-gap reference circuit with high-order temperature compensation |
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