CN106920740B - The production method of fin doping method and fin formula field effect transistor - Google Patents
The production method of fin doping method and fin formula field effect transistor Download PDFInfo
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- CN106920740B CN106920740B CN201511003228.7A CN201511003228A CN106920740B CN 106920740 B CN106920740 B CN 106920740B CN 201511003228 A CN201511003228 A CN 201511003228A CN 106920740 B CN106920740 B CN 106920740B
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- 230000005669 field effect Effects 0.000 title claims abstract description 37
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- 238000009792 diffusion process Methods 0.000 claims abstract description 165
- 230000004888 barrier function Effects 0.000 claims abstract description 93
- 239000000758 substrate Substances 0.000 claims abstract description 43
- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 238000000137 annealing Methods 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 12
- 238000000926 separation method Methods 0.000 claims description 12
- 229910052710 silicon Inorganic materials 0.000 claims description 12
- 239000010703 silicon Substances 0.000 claims description 12
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- UMVBXBACMIOFDO-UHFFFAOYSA-N [N].[Si] Chemical compound [N].[Si] UMVBXBACMIOFDO-UHFFFAOYSA-N 0.000 claims description 7
- 238000000231 atomic layer deposition Methods 0.000 claims description 7
- 239000011521 glass Substances 0.000 claims description 6
- 239000004576 sand Substances 0.000 claims description 6
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 5
- RZVAJINKPMORJF-UHFFFAOYSA-N Acetaminophen Chemical group CC(=O)NC1=CC=C(O)C=C1 RZVAJINKPMORJF-UHFFFAOYSA-N 0.000 claims description 4
- IJGRMHOSHXDMSA-UHFFFAOYSA-N nitrogen Substances N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 4
- 239000005297 pyrex Substances 0.000 claims description 4
- 230000003667 anti-reflective effect Effects 0.000 claims description 3
- 239000012530 fluid Substances 0.000 claims description 3
- 238000005468 ion implantation Methods 0.000 claims description 3
- 229910052757 nitrogen Inorganic materials 0.000 claims description 3
- 229910003978 SiClx Inorganic materials 0.000 claims description 2
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- 230000000717 retained effect Effects 0.000 claims description 2
- HIVGXUNKSAJJDN-UHFFFAOYSA-N [Si].[P] Chemical group [Si].[P] HIVGXUNKSAJJDN-UHFFFAOYSA-N 0.000 claims 2
- 150000002500 ions Chemical class 0.000 description 115
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
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- 238000002955 isolation Methods 0.000 description 2
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- 241000486679 Antitype Species 0.000 description 1
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- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
- H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of production method of fin doping method and fin formula field effect transistor, for fin doping method, in thermal annealing process, semiconductor substrate surface between fin has bottom diffusion barrier layer, it can prevent the P-type ion in P-type ion diffusion source thereon, the N-type ion in N-type ion diffusion source from diffusing into semiconductor substrate, thus, in same well region or each fin formula field effect transistor source/drain regions of adjacent well region do not turn on, it avoids read-write and crosstalk occurs in the process, improve the performance of fin formula field effect transistor.Furthermore, since the P-type ion in P-type ion diffusion source that with bottom diffusion barrier layer, the N-type ion in N-type ion diffusion source on P-type ion diffusion source can not be diffused on substrate or N-type ion diffusion source can not diffuse into substrate, thus upper layer ion diffusion source need not remove, and save process.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of fin doping method and fin formula field effect transistor
Production method.
Background technique
With the continuous development of semiconductor process technique, as process node is gradually reduced, rear grid (gate-last) technique
It is widely applied, to obtain ideal threshold voltage, improves device performance.But when device characteristic size (CD,
Critical Dimension) further decline when, even if the structure of conventional metal-oxide-semiconductor field effect transistor is also using rear grid technique
It is unable to satisfy the demand to device performance, multi-gate device has obtained extensive concern as the substitution of conventional device.
Fin formula field effect transistor (Fin FET) is a kind of common multi-gate device, and Fig. 1 shows in the prior art one
The schematic perspective view of kind fin formula field effect transistor.As shown in Figure 1, comprising: semiconductor substrate 10, the semiconductor substrate
The fin 14 of protrusion is formed on 10；Separation layer 11 covers the surface of semiconductor substrate 10 and the Partial Height of fin 14；Grid
Pole structure 12 covers top and the side wall of fin 14 across on fin 14, gate structure 12 include gate dielectric layer (in figure not
Show) and gate electrode (not shown) on gate dielectric layer.The fin 14 covered for Fin FET, gate structure 12
For channel region, that is, there are multiple grid, is conducive to increase driving current, improves device performance.
Such as p-type fin formula field effect transistor, semiconductor substrate 10 is interior to have N-type well region, fin 14 thereon
For N-type ion doping.In the prior art, N-type fin 14 is generally doped by ion implanting, actual result show this from
Sub- injection process can damage fin, cause defect, influence device performance.To avoid the above problem, in recent years, from gradually sending out in industry
Solid source doping method (solid-source doping, SSD) has been opened up, i.e., has deposited one layer of N-type ion source or p-type in fin portion surface
Ion source, under high temperature, by solid source N-type ion or P-type ion diffuse into fin.In recent years, as Fin FET density increases
Greatly, critical size reduces, and the fin formula field effect transistor of above-mentioned SSD production is easy to appear string during read-write between each other
It disturbs, performance is still to be improved.
Summary of the invention
The purpose that the present invention realizes is to improve the performance of existing fin formula field effect transistor, avoids each fin during read-write
There is crosstalk between formula field effect transistor.
To achieve the above object, an aspect of of the present present invention provides a kind of fin doping method, comprising:
Semiconductor substrate is provided, the semiconductor substrate includes be used to form first kind fin formula field effect transistor the
One region and the second area for being used to form Second Type fin formula field effect transistor, the first kind and Second Type are anti-
Type, the first area have Second Type well region, and the second area has first kind well region, the first area and the
Two region upper surfaces have several discrete fins；
Semiconductor substrate surface between the fin portion surface and fin deposits a bottom diffusion barrier layer, and in institute
It states and forms a sacrificial layer on the diffusion barrier layer of bottom, the sacrificial layer is filled up completely the gap between the fin；
It is etched back the sacrificial layer, the bottom diffusion barrier layer of exposure fin portion surface, and retains partly leading between fin
Sacrificial layer in body substrate；
With the bottom diffusion barrier layer of the semiconductor substrate surface between the sacrificial layer protection fin of the reservation, fin is removed
The bottom diffusion barrier layer on portion surface；The sacrificial layer of the reservation is removed afterwards；
Bottom diffusion barrier layer upper surface between the fin portion surface and fin sequentially forms first kind ion
Diffusion source layer, first kind ion diffusion barrier layer；
Patterned mask layer is formed on the first kind ion diffusion barrier layer, dry method removal is located at described second
First kind ion diffusion source layer, the first kind ion diffusion barrier layer in region；
The first kind ion diffusion barrier layer upper surface of the first area, the fin of second area and fin it
Between bottom diffusion barrier layer upper surface sequentially form Second Type ion diffusion source layer, Second Type ion diffusion barrier layer；
Thermal annealing makes the first kind ion in first kind ion diffusion source layer diffuse into the fin of first area, the
Second Type ion in two types of ion diffusion source layers diffuses into the fin of second area to be correspondingly formed the doping in two regions
Fin.
Optionally, before thermal annealing, separation layer is formed on the Second Type ion diffusion barrier layer, the separation layer is sudden and violent
Expose the upper part region of the fin of first area and second area.
Optionally, the material of the bottom diffusion barrier layer is silicon nitride, in silicon oxynitride, fire sand, nitrogen silicon boride
At least one, generated using chemical vapor deposition or atomic layer deposition method.
Optionally, the thickness range of the bottom diffusion barrier layer is
Optionally, the first kind is N-type, and the Second Type is p-type, the material of first kind ion diffusion source layer
For Pyrex, the material of Second Type ion diffusion source layer is phosphorosilicate glass；Or the first kind be p-type, described second
Type is N-type, and the material of first kind ion diffusion source layer is phosphorosilicate glass, and the material of Second Type ion diffusion source layer is boron
Silica glass.
Optionally, the first kind ion diffusion barrier layer is identical as the material of Second Type ion diffusion barrier layer.
Optionally, the material of the first kind ion diffusion barrier layer and Second Type ion diffusion barrier layer is nitridation
At least one of silicon, silicon oxynitride, fire sand, nitrogen silicon boride are generated using chemical vapor deposition or atomic layer deposition method.
Optionally, the temperature range of the thermal annealing is 800 DEG C~1200 DEG C.
Optionally, the first kind ion diffusion source layer, first kind ion diffusion barrier layer thickness range be
Optionally, the Second Type ion diffusion source layer, Second Type ion diffusion barrier layer thickness range be
Optionally, the material of the sacrificial layer is unformed silicon, in organic bottom antireflective layer, organic fluid material layer
It is at least one.
Optionally, after being etched back the sacrificial layer, the sacrificial layer thickness range retained in the semiconductor substrate between fin is
Another aspect of the present invention provides a kind of production method of fin formula field effect transistor, comprising:
Doping fin is formed using the fin doping method of any of the above-described scheme；
It is developed across the gate structure of the doping fin；
Using the gate structure as exposure mask, ion implantation doping is carried out to form source to the doping fin of gate structure two sides
Drain region.
Compared with prior art, fin doping method of the invention has the advantage that the semiconductor between fin serves as a contrast
Bottom surface formed a bottom diffusion barrier layer, it is rear a) be sequentially depositing on the diffusion barrier layer of bottom P-type ion diffusion source, p-type from
Sub- diffusion barrier layer removes the predetermined P-type ion for forming p-type fin formula field effect transistor region using patterning process and spreads
Source, P-type ion diffusion barrier layer, retain the predetermined P-type ion diffusion source for forming N-type fin formula field effect transistor region, p-type from
Sub- diffusion barrier layer (patterning process)；In the P-type ion diffusion barrier layer of the bottom diffusion barrier layer, reservation that expose
On be sequentially depositing N-type ion diffusion source, N-type ion diffusion barrier layer；Or b) be sequentially depositing on the diffusion barrier layer of bottom N-type from
Sub- diffusion source, N-type ion diffusion barrier layer are removed using patterning process and make a reservation for form N-type fin formula field effect transistor region
N-type ion spread source, N-type ion diffusion barrier layer, retain the predetermined N-type for forming p-type fin formula field effect transistor region from
Sub- diffusion source, N-type ion diffusion barrier layer (patterning process)；In the N-type of the bottom diffusion barrier layer, reservation that expose
P-type ion diffusion source, P-type ion diffusion barrier layer are sequentially depositing on ion diffusion barrier layer；No matter a) or b) scheme, Zhi Houre
Annealing makes the N-type ion in N-type ion diffusion source diffuse into predetermined fin, the p-type for forming p-type fin formula field effect transistor region
P-type ion in ion diffusion source diffuses into the predetermined fin for forming N-type fin formula field effect transistor region.Thermal annealing process
In, the semiconductor substrate surface between fin has bottom diffusion barrier layer, can prevent in P-type ion diffusion source thereon
N-type ion in P-type ion, N-type ion diffusion source diffuses into semiconductor substrate, and then avoids same well region interior or adjacent trap
There is crosstalk between each fin formula field effect transistor in area.Further, since there is bottom diffusion barrier layer, for a) scheme, p-type
N-type ion diffusion source on ion diffusion source can not diffuse into substrate, thus N-type ion diffusion source thereon need not remove, and save
Save process；For b) scheme, the N-type ion diffusion source on P-type ion diffusion source can not diffuse into substrate, thus p-type thereon
Ion diffusion source need not remove, and save process.
Due to not influencing the isolation effect of well region in substrate in above-mentioned doping fin manufacturing process.Thus, it can also improve fin
The performance of formula field effect transistor.
Detailed description of the invention
Fig. 1 is a kind of schematic perspective view of fin formula field effect transistor in the prior art；
Fig. 2 to Fig. 9 is the structural schematic diagram of the doping fin in the different production phases of one embodiment of the invention.
Specific embodiment
As described in the background art, crosstalk is easy to appear between existing fin formula field effect transistor.In view of the above-mentioned problems,
The reason of inventor is analyzed, and discovery is led to the problem of is: during fin solid-source doping, the Doped ions of Solid Source
Also it has diffused into the well region in substrate, under serious conditions, will lead in same well region or each fin field effect of adjacent well region is brilliant
, there is crosstalk in the conducting of body pipe source region or drain region conducting during read-write.Based on above-mentioned analysis, the present invention proposes: in fin solid-state
During source doping, bottom diffusion barrier layer is formed between the semiconductor substrate and Solid Source between fin, is prevented in Solid Source
Doped ions diffuse into the well region of substrate, and then prevent each fin formula field effect transistor source/drain regions conducting.
To make the above purposes, features and advantages of the invention more obvious and understandable, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.
Fig. 2 to Fig. 9 is the structural schematic diagram of the doping fin in the different production phases of one embodiment of the invention.Referring to
Shown in Fig. 2 to Fig. 9, the doping method of fin is discussed in detail.
Firstly, semiconductor substrate 20 includes being used to form p-type fin field effect refering to what is shown in Fig. 2, providing semiconductor substrate 20
It answers the first area I of transistor and is used to form the second area II of N-type fin formula field effect transistor, first area I and second
Region II upper surface has several discrete fins 21.
The material of semiconductor substrate 20 can be monocrystalline silicon or silicon-on-insulator (SOI), and fin 21 is by etching portion
What the monocrystalline silicon or SOI of point height were formed.In addition, semiconductor substrate 20 also may include monocrystalline silicon (or SOI) and monocrystalline silicon
Epitaxial layer on (or SOI), discrete fin 21 are formed by etching the epitaxial layer.
There is N-type well region (not shown) in the semiconductor substrate 20 of first area I, the semiconductor substrate 20 of second area II
It is interior that there is P type trap zone (not shown).In well region, separated between each transistor using fleet plough groove isolation structure (STI).
In the present embodiment, first area I, second area II are illustrated by taking two discrete fins 21 as an example respectively,
In its embodiment, discrete fin 21 or other numbers in this step.
In addition, being formed in the etching process of fin 21, opening is long compared with the etch period of open bottom, thus the area removed
Domain is big in opening, bottom is small, and then the fin 21 of the reservation complementary with removal region is the shape that top is small, bottom is big.
Then, refering to what is shown in Fig. 3,20 surface of semiconductor substrate between 21 surface of fin and fin 21 deposits a bottom
Portion's diffusion barrier layer 22, and a sacrificial layer 23 is formed on bottom diffusion barrier layer 22, which is filled up completely fin 21
Between gap.
In the specific implementation process, the material of bottom diffusion barrier layer 22 can be silicon nitride, silicon oxynitride, nitrogen carbonization
At least one of silicon, nitrogen silicon boride are generated using chemical vapor deposition or atomic layer deposition method.Thickness range can beIt is preferred that
The material of sacrificial layer 23 can for filling capacity preferably and the material that easily removes, for example, unformed silicon (α-Si),
At least one of organic bottom antireflective layer (BARC), organic fluid material layer (DUO).
Later, refering to what is shown in Fig. 4, eatch-back sacrificial layer 23, exposes the bottom diffusion barrier layer 22 on 21 surface of fin, and retain
The sacrificial layer 23 in semiconductor substrate 20 between fin 21.
In this step, eatch-back (Etch Back) is no mask etching, carries out dry etching for example, by using fluoro-gas,
CF4、C3F8Deng.23 thickness range of sacrificial layer of reservation is, for example,
Then, referring to Figure 5, the bottom on 20 surface of semiconductor substrate between fin 21 is protected with the sacrificial layer of reservation 23
Portion's diffusion barrier layer 22 removes the bottom diffusion barrier layer 22 on 21 surface of fin；The sacrificial layer 23 of reservation is removed afterwards.
The bottom diffusion barrier layer 22 on 21 surface of fin is removed for example, by using wet process, and diffusion barrier layer 22 material in bottom is nitrogen
When SiClx, it is hot phosphoric acid which, which removes solution,.The sacrificial layer 23 of reservation is removed using ashing method.
Later, referring to shown in Fig. 6,22 upper surface of bottom diffusion barrier layer between 21 surface of fin and fin 21
Sequentially form P-type ion diffusion source layer 24, P-type ion diffusion barrier layer 25.Later, the shape on P-type ion diffusion barrier layer 25
At patterned mask layer 26, dry method removal is located at P-type ion diffusion source layer 24, the P-type ion diffusion barrier layer of first area I
25。
P-type ion diffusion source layer 24 is, for example, Pyrex (BSG), can use chemical vapor deposition or spin-coating method shape
At.In one embodiment, the thickness range of P-type ion diffusion source layer 24 can be It is preferred that
The material of P-type ion diffusion barrier layer 25 be silicon nitride, silicon oxynitride, fire sand, in nitrogen silicon boride at least
One kind is generated using chemical vapor deposition or atomic layer deposition method.In one embodiment, the thickness of P-type ion diffusion barrier layer 25
Degree may range fromIt is preferred that
P-type ion diffusion barrier layer 25 can prevent the P-type ion in P-type ion diffusion source layer 24 through it to extending out
It dissipates.
Patterned mask layer 26 can be photoresist layer, or metal hard mask layer.
Then, refering to what is shown in Fig. 7, in 25 upper surface of P-type ion diffusion barrier layer of second area II, first area I
22 upper surface of bottom diffusion barrier layer between fin 21 and fin 21 sequentially forms N-type ion diffusion source layer 27, N-type ion
Diffusion barrier layer 28.
N-type ion diffusion source layer 27 is, for example, phosphorosilicate glass (PSG), can use chemical vapor deposition or spin-coating method shape
At.In one embodiment, the thickness range of N-type ion diffusion source layer 27 can be It is preferred that
The material of N-type ion diffusion barrier layer 28 be silicon nitride, silicon oxynitride, fire sand, in nitrogen silicon boride at least
One kind is generated using chemical vapor deposition or atomic layer deposition method.In one embodiment, the thickness of N-type ion diffusion barrier layer 28
Degree may range fromIt is preferred that
N-type ion diffusion barrier layer 28 can prevent the N-type ion in N-type ion diffusion source layer 27 through it to extending out
It dissipates.
In other embodiments, in structure basis shown in Fig. 5, referring to shown in Fig. 8, can also first 21 surface of fin, with
And 22 upper surface of bottom diffusion barrier layer between fin 21 sequentially forms N-type ion diffusion source layer 27, N-type ion diffusion barrier
Layer 28.Later, patterned mask layer 26 is formed on N-type ion diffusion barrier layer 28, dry method removal is located at second area II
N-type ion diffusion source layer 27, N-type ion diffusion barrier layer 28.Followed by N-type ion diffusion barrier layer in first area I
28 upper surfaces, second area II fin 21 and fin 21 between 22 upper surface of bottom diffusion barrier layer sequentially form p-type
Ion diffusion source layer 24, P-type ion diffusion barrier layer 25.
No matter having N-type ion diffusion source layer 27 or first area on the P-type ion diffusion source layer 24 of second area II
There is P-type ion diffusion source layer 24, later, thermal annealing, so that P-type ion diffusion source layer 24 on I N-type ion diffusion source layer 27
In P-type ion diffuse into the fin 21 of first area I, the N-type ion in N-type ion diffusion source layer 27 diffuses into second area
II fin 21 is to be correspondingly formed the doping fin 21 ' in two regions.
Thermal annealing temperatures in this step may range from 800 DEG C~1200 DEG C, can be using to semiconductor substrate 20
Heating is realized, can also be realized using the hot processing procedure in subsequent technique.
It is understood that 20 surface of semiconductor substrate between fin 21 has bottom diffusion barrier layer 22, thermal annealing
The P-type ion in P-type ion diffusion source layer 24 thereon, the N-type ion in N-type ion diffusion source layer 27 can be prevented in the process
It diffuses into the well region of semiconductor substrate 20, the electrically isolated performance of well region will not be changed.Further, since having bottom diffusion barrier
Layer 22, for embodiment shown in Fig. 7, in second area II, the N-type ion diffusion source layer 27 on P-type ion diffusion source layer 24
In N-type ion can not diffuse into substrate 20, thus the N-type ion diffusion source layer 27 of second area II need not remove, and save
Process.For embodiment shown in Fig. 8, in first area I, in the P-type ion diffusion source layer 24 on N-type ion diffusion source layer 27
P-type ion can not diffuse into substrate 20, thus the P-type ion diffusion source layer 24 of first area I need not remove, and save work
Sequence.
In the specific implementation process, this step can also with as shown in figure 9, on N-type ion diffusion barrier layer 28 formed every
Absciss layer 29 is etched back the upper part region that the separation layer 29 exposes the fin 21 of first area I and second area II afterwards.It
Afterwards, then annealing operation is carried out.In the above process, separation layer 29 can play the role of heat preservation.
The material of separation layer 29 can be silica, and silane or TEOS chemical vapor deposition is used to generate.
Based on above-mentioned fin doping method, the present invention also provides a kind of production method of fin formula field effect transistor, tools
Body, comprising: on the basis of there is the substrate of doping fin 21 ', mixed first what 29 surface of separation layer, separation layer 29 exposed
Miscellaneous 21 ' surface of fin is developed across the gate structure (not shown) of the doping fin 21 '；It is right afterwards using the gate structure as exposure mask
The doping fin 21 ' of gate structure two sides carries out ion implantation doping to form source-drain area.
In other embodiments, for first annealing, so that P-type ion diffusion source layer 24, N-type ion diffusion source layer 27 diffuse into
The scheme of corresponding fin 21 is initially formed separation layer 29 when making fin formula field effect transistor, after 29 surface of separation layer, every
21 ' the surface of doping fin that absciss layer 29 exposes forms gate structure.It is understood that during above-mentioned fin 21 adulterates,
Doped ions are not injected to well region in substrate 20, thus, in same well region or each fin formula field effect transistor source of adjacent well region
Area/drain region does not turn on, and avoids read-write and crosstalk occurs in the process, improves the performance of fin formula field effect transistor.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (13)
1. a kind of fin doping method characterized by comprising
Semiconductor substrate is provided, the semiconductor substrate includes being used to form the firstth area of first kind fin formula field effect transistor
Domain and the second area for being used to form Second Type fin formula field effect transistor, the first kind and Second Type transoid, institute
First area is stated with Second Type well region, the second area has first kind well region, the first area and the secondth area
Domain upper surface has several discrete fins；
Semiconductor substrate surface between the fin portion surface and fin deposits a bottom diffusion barrier layer, and at the bottom
A sacrificial layer is formed on portion's diffusion barrier layer, the sacrificial layer is filled up completely the gap between the fin；
It is etched back the sacrificial layer, the bottom diffusion barrier layer of exposure fin portion surface, and retains the semiconductor lining between fin
Sacrificial layer on bottom；
With the bottom diffusion barrier layer of the semiconductor substrate surface between the sacrificial layer protection fin of the reservation, fin table is removed
The bottom diffusion barrier layer in face；The sacrificial layer of the reservation is removed afterwards；
Bottom diffusion barrier layer upper surface between the fin portion surface and fin sequentially forms the diffusion of first kind ion
Active layer, first kind ion diffusion barrier layer；
Patterned mask layer is formed on the first kind ion diffusion barrier layer, dry method removal is located at the second area
First kind ion diffusion source layer, first kind ion diffusion barrier layer；
Between the first kind ion diffusion barrier layer upper surface of the first area, the fin and fin of second area
Bottom diffusion barrier layer upper surface sequentially forms Second Type ion diffusion source layer, Second Type ion diffusion barrier layer；
Thermal annealing makes the first kind ion in first kind ion diffusion source layer diffuse into the fin of first area, the second class
Second Type ion in type ion diffusion source layer diffuses into the fin of second area to be correspondingly formed the doping fin in two regions.
2. fin doping method according to claim 1, which is characterized in that before thermal annealing, in the Second Type ion
Separation layer is formed on diffusion barrier layer, the separation layer exposes the upper part area of the fin of first area and second area
Domain.
3. fin doping method according to claim 1, which is characterized in that the material of the bottom diffusion barrier layer is nitrogen
At least one of SiClx, silicon oxynitride, fire sand, nitrogen silicon boride, it is raw using chemical vapor deposition or atomic layer deposition method
At.
4. fin doping method according to claim 3, which is characterized in that the thickness range of the bottom diffusion barrier layer
For
5. fin doping method according to claim 1, which is characterized in that the first kind is N-type, second class
Type is p-type, and the material of first kind ion diffusion source layer is Pyrex, and the material of Second Type ion diffusion source layer is phosphorus silicon
Glass；Or the first kind is p-type, the Second Type is N-type, and the material of first kind ion diffusion source layer is phosphorus silicon glass
Glass, the material of Second Type ion diffusion source layer are Pyrex.
6. fin doping method according to claim 5, which is characterized in that the first kind ion diffusion barrier layer with
The material of Second Type ion diffusion barrier layer is identical.
7. fin doping method according to claim 1 or 6, which is characterized in that the first kind ion diffusion barrier
Layer and the material of Second Type ion diffusion barrier layer are silicon nitride, silicon oxynitride, fire sand, at least one in nitrogen silicon boride
Kind, it is generated using chemical vapor deposition or atomic layer deposition method.
8. fin doping method according to claim 1, which is characterized in that the temperature range of the thermal annealing is 800 DEG C
~1200 DEG C.
9. fin doping method according to claim 1, which is characterized in that the first kind ion diffusion source layer,
The thickness range of one type ion diffusion barrier layer is
10. according to claim 1 or fin doping method described in 9, which is characterized in that the Second Type ion spreads source
Layer, Second Type ion diffusion barrier layer thickness range be
11. fin doping method according to claim 1, which is characterized in that the material of the sacrificial layer be unformed silicon,
At least one of organic bottom antireflective layer, organic fluid material layer.
12. fin doping method according to claim 1, which is characterized in that after being etched back the sacrificial layer, between fin
The sacrificial layer thickness range retained in semiconductor substrate is
13. a kind of production method of fin formula field effect transistor characterized by comprising
Doping fin is formed using fin doping method described in any one of the claims 1 to 12；
It is developed across the gate structure of the doping fin；
Using the gate structure as exposure mask, ion implantation doping is carried out to form source and drain to the doping fin of gate structure two sides
Area.
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| CN113161230B (en) * | 2020-12-14 | 2022-05-17 | 安徽安芯电子科技股份有限公司 | Diffusion process of phosphorus-boron synchronous one-time diffusion graded junction chip |
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