CN106919857A - Chip, and starting protection device and method of chip - Google Patents
Chip, and starting protection device and method of chip Download PDFInfo
- Publication number
- CN106919857A CN106919857A CN201511000312.3A CN201511000312A CN106919857A CN 106919857 A CN106919857 A CN 106919857A CN 201511000312 A CN201511000312 A CN 201511000312A CN 106919857 A CN106919857 A CN 106919857A
- Authority
- CN
- China
- Prior art keywords
- check code
- frequency
- chip
- memory cell
- default
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
Abstract
The invention provides a chip, a chip starting protection device and a chip starting protection method. Wherein the protection device comprises: a storage unit storing a first check code; the adjustable clock generating unit is used for outputting a clock signal with a preset frequency after being electrified and reducing the frequency of the output clock signal according to the received frequency reduction instruction; and the check code comparison unit is connected with the adjustable clock generation unit and the storage unit and is used for comparing the first check code stored in the storage unit with a preset second check code, if the first check code is consistent with the preset second check code, each working hardware in the chip is triggered to start running according to a clock signal of the current frequency, and if the first check code is inconsistent with the preset second check code, the frequency reduction instruction is sent to the adjustable clock generation unit. The invention solves the working method that the chip automatically adapts to the external environment under the condition that the system ensures the highest performance and the high stability of the system.
Description
Technical field
The present invention relates to chip field, more particularly to a kind of chip, chip starting protection device and method.
Background technology
With the development of chip high integration, comprising sensors such as processor, memories in many integrated chips
Part.These Sensitive Apparatuses have strict requirements to working environment, clock frequency.Therefore, in design,
Delay circuit is generally comprised in high reliability chip, it is steady with the clock signal for ensuring the circuit containing Sensitive Apparatus
It is fixed.
However, due to disturbing the factor of sensitive circuit a lot, level shake when as above electric, external electromagnetic field
Interference, temperature and humidity interference etc., too high, fixed clock signal be likely to result in chip interference ring
Cannot be run under border, repeated priming, the problems such as mispronounce information.
Accordingly, it would be desirable to be improved to prior art.
The content of the invention
The present invention provides a kind of chip, the starting protection device and method of chip, for solving in the prior art
The too high fixed clock signal of frequency cannot ensure the problem of the stability of a system of chip operation.
Based on above-mentioned purpose, the present invention provides a kind of starting protection device of chip, including：There is the first school
Test the memory cell of code；Adjustable clock generating unit, the clock for exporting predeterminated frequency after the power-up is believed
Number, and the frequency of exported clock signal is reduced according to the frequency reducing instruction for being received；With the adjustable clock
The check code comparing unit that generating unit is connected with memory cell, for comparing what the memory cell was preserved
First check code and default second check code, if unanimously, each working hardware in flip chip is according to working as
The clock start signal operation of preceding frequency, if inconsistent, the drop is sent to the adjustable clock generating unit
Frequency is instructed.
Preferably, the adjustable clock generating unit includes：Counter circuit and comprising adjustable resistance can
Adjust clock generating circuit；The counter circuit is used to be based on the received frequency reducing instruction count frequency reducing frequency,
And the adjustable resistance is adjusted based on the frequency reducing frequency.
Preferably, the adjustable clock occurs circuit includes：Comparator, the resistance R0 and adjustable resistance of series connection
R1, some switches sets of controlled end cascade, ground capacity, the Shaping Module of correspondence switches set quantity；
The negative input end connection reference voltage of the comparator, positive input terminal are accessed between resistance R0 and R1,
The output end of the comparator by resistance R0 and R1 be grounded, while also with the input phase of each switches set
Even, the signal output part of each switches set connects corresponding ground capacity.Wherein, rear stage switches set is controlled
The signal output part of end connection previous stage switches set, the signal output part connection sizing die of afterbody switches set
The input of block.Meanwhile, the controlled end of first order switches set is also connected with the input of Shaping Module.
Preferably, the check code comparing unit includes：The address generator being connected with the memory cell,
For storing the address information of the first check code in the generation correspondence memory cell when upper electric, and utilize institute
The address information of generation obtains first check code；With the address generator and adjustable clock generating unit
Connected check code Comparison Circuit, for by the first check code from the address generator and default
Second check code is compared, if unanimously, exporting for representing the correct instruction of verification, if inconsistent,
The information related to clock signal frequency after then record is adjusted, and sent to the adjustable clock generating unit
The frequency reducing instruction；The trigger being connected with the check code Comparison Circuit, for based on being used for for being received
The correct instruction of verification is represented, the check code Comparison Circuit is triggered by the correlation letter of presently described clock signal
Breath is saved in the memory cell, and indicates each working hardware to be transported according to the clock start signal of current frequency
OK.
Preferably, multiple first check codes are included in the memory cell；Corresponding, the check code is compared
The first check code that unit is additionally operable to be provided the address generator enters with corresponding default second check code
Row compares, and when all comparative results are consistent, exports for representing the correct instruction of verification.
Preferably, the check code comparing unit is additionally operable to according to default number of repetition, and repeat more describedly
The first check code that location generator is provided and default second check code, and it is one in all comparative results
During cause, export for representing the correct instruction of verification.
Based on above-mentioned purpose, the present invention also provides a kind of chip, including：As above any described starting protection
Device.
Based on above-mentioned purpose, the present invention also provides a kind of starting protection method of chip, wherein, the chip
In comprising there being the memory cell of the first check code, including：The clock letter of predeterminated frequency is produced when upper electric
Number；Compare the first check code and default second check code that the memory cell is preserved；If consistent,
Each working hardware in flip chip runs according to the clock start signal of current frequency；If inconsistent, drop
The frequency of the clock signal produced by low, compares two check codes again, untill comparison result is consistent.
Preferably, it is described to compare the first check code and default second check code that the memory cell is preserved
Mode include：The address information of the first check code is stored in the generation correspondence memory cell when upper electric,
And utilize generated address information to obtain first check code；By acquired the first check code and pre-
If the second check code compare.
Preferably, first check code is multiple；It is corresponding, it is described to compare memory cell is preserved the
One check code includes with the mode of default second check code：Each first verification will be stored in the memory cell
Code is compared with corresponding default second check code, and when all comparative results are consistent, exporting is used for
Represent the correct instruction of verification.
Preferably, the side for comparing the first check code for being preserved of memory cell and default second check code
Formula includes：According to default number of repetition, repeat the first check code for being stored in the memory cell with it is pre-
If the second check code, and when all comparative results are consistent, export for representing verification correctly finger
Order.
As described above, the starting protection device and method of chip of the invention, chip, with following beneficial effect
Really：By before Sensitive Apparatus startup work in the chips using part number circuit to the frequency of clock signal
Verified, and the frequency of current clock signal is adjusted according to the result, the present invention is by being reduced
The mode of chip operation clock frequency, it is ensured that the stability of a system of chip, effectively prevent when chip runs
Existing CPU mispronounces information, program run-time error, resets repeatedly and the vicious circle such as restart；In addition, using by
The mode of frequency reducing is walked, clock frequency as high as possible can be provided for chip, it is ensured that the operating efficiency of chip；
Further, in order to prevent from being accidentally proved to be successful, and for Sensitive Apparatus provides the clock frequency for being not suitable for working environment,
The present invention is also by the way of multiple authentication, it is ensured that whole system trouble free service in any condition is needed
Ask.
Brief description of the drawings
Technical scheme in order to illustrate more clearly the embodiments of the present invention, will retouch to the embodiment of the present invention below
The accompanying drawing to be used needed for stating is briefly described, it should be apparent that, drawings in the following description are only
Some embodiments of the present invention, for those of ordinary skill in the art, are not paying creative work
Under the premise of, content that can also be according to embodiments of the present invention and these accompanying drawings obtain other accompanying drawings.
Fig. 1 is the block diagram of one embodiment of chip of the invention.
Fig. 2 is the structure side of one embodiment of adjustable clock generation circuit in starting protection device of the invention
Block diagram.
Fig. 3 is the structure square frame of one embodiment of verification comparing unit in starting protection device of the invention
Figure.
Fig. 4 is the time diagram after electricity on starting protection device of the invention.
Fig. 5 is the flow chart of one embodiment of starting protection method of the invention.
Specific embodiment
For make present invention solves the technical problem that, the technical scheme that uses and the technique effect that reaches it is more clear
Chu, is described in further detail below in conjunction with accompanying drawing to the technical scheme of the embodiment of the present invention, it is clear that
Described embodiment is only a part of embodiment of the invention, rather than whole embodiments.Based on this hair
Embodiment in bright, those skilled in the art obtained under the premise of creative work is not made it is all its
His embodiment, belongs to the scope of protection of the invention.
As shown in figure 1, the present invention provides a kind of chip.The chip includes clock-signal generator, with
And based on the logical sequence that clock signal is provided come the digital circuit of work, such as CPU, memory cell,
Trigger, logical device etc..
The chip 1 also includes：Starting protection device 11.When electricity on chip 1, the starting protection dress
Put 11 to be started working based on power supply signal, and under the frequency of current clock signal, carry out check code checking,
And the frequency of clock signal is reduced according to the result.Sensitive digital device (such as CPU) in for chip
For, it is now and not actuated, but after being verified according to clock frequency startup optimization when being verified.
The starting protection device 11 includes：The memory cell 111, adjustable clock generating unit 112, school
Test yard comparing unit 113.
There is the first check code in the memory cell 111.The memory cell 111 is included but is not limited to：
Flash memories, read-only memory, memory device, the disposable programmable memory part of repeatable programming etc..
The adjustable clock generating unit 112 is the improvement to existing clock-signal generator, and it not only exists
The clock signal of predeterminated frequency is exported when upper electric, always according to the frequency reducing instruction adjustment clock signal for being received
Frequency.
Here, the adjustable clock generating unit 112 includes：There is electricity in counter circuit and adjustable clock
Road.
The counter circuit is used to be based on the received frequency reducing instruction count frequency reducing frequency, and based on described
The frequency reducing frequency adjusts the adjustable resistance during the adjustable clock occurs circuit, so that after its output reduces frequency
Clock signal.
There is the circuit unit that circuit is based on RC circuit theories and builds in the adjustable clock, including：
Adjustable resistance.The controlled end of the adjustable resistance is connected with the counter circuit, to adjust itself resistance.
The adjustable resistance also resets to preset resistive value when upper electric, and circuit occurs upper to allow the adjustable clock
The clock signal of predeterminated frequency is exported when electric.Wherein, the predeterminated frequency is workable for the chip most
High-frequency.For example, the output predeterminated frequency of adjustable clock generating unit 112 is 50MHz's when upper electric
Clock signal.
The counter circuit progressively adjusts adjustable resistance according to the step-length of default adjustable resistance resistance,
To reduce frequency.
For example, being preset with resistance step-length in the counter circuit for a, the counter circuit is often exported
Resistance step-length a, the adjustable resistance that the adjustable clock occurs in circuit is just corresponded to be increased/reduce resistance a.
Designed according to side circuit, the change of adjustable resistance resistance, will cause that RC circuits export sinusoidal signal
Frequency correspondence is reduced, by the shaping to sinusoidal signal, the adjustable clock occurs circuit will be exported
Clock signal after frequency reducing.
Preferably, with reference to Fig. 2, the adjustable clock occurs circuit to be included：Comparator, the resistance R0 of series connection
Some switches sets, ground capacity, the shaping of correspondence switches set quantity cascaded with adjustable resistance R1, controlled end
Module.
The negative input end connection reference voltage of the comparator, positive input terminal are accessed between resistance R0 and R1,
The output end of the comparator is grounded by resistance R0 and R1, while the input also with each switches set is connected,
The signal output part of each switches set connects corresponding ground capacity.Wherein, the controlled end of rear stage switches set connects
The signal output part of previous stage switches set is connect, the signal output part connection Shaping Module of afterbody switches set
Input.Meanwhile, the controlled end of first order switches set is also connected with the input of Shaping Module.
The check code comparing unit 113 and the adjustable clock generating unit 112 and the phase of memory cell 111
Even, for comparing the first check code and default second check code that the memory cell 111 is preserved, if
Unanimously, then each working hardware in flip chip runs according to the clock start signal of current frequency, if differing
Cause, sending the frequency reducing to the adjustable clock generating unit 112 instructs.
Specifically, the verification comparing unit includes address generator 1131, the and of check code Comparison Circuit 1132
Trigger 1133.As shown in Figure 3.
The address generator 1131 is connected with the memory cell 111, for generating correspondence institute when upper electric
State and store the address information of the first check code in memory cell 111, and utilize generated address information to obtain
First check code.
Here, the address generator 1131 can be set previously according to the storage address of the first check code.Institute
State address generator 1131 and the ground that the first check code is stored in the correspondence memory cell 111 is generated when upper electric
Location information, and read the first check code corresponding to generated address information from the memory cell 111.
The check code Comparison Circuit 1132 and the address generator 1131 and adjustable clock generating unit 112
It is connected, for the first check code from the address generator 1131 and default second check code to be entered
Row is compared, if unanimously, exporting for representing the correct instruction of verification, if inconsistent, after record adjustment
The information related to clock signal frequency, and send the frequency reducing to the adjustable clock generating unit 112
Instruction.
Here, the check code Comparison Circuit 1132 can be used to constitute judgement first comprising multiple logical devices
Check code and the whether consistent decision circuitry of the second check code.
For example, in the check code contrast circuit comprising correspondence everybody comparator of the second check code and with it is each
The connected XOR gate of comparator output terminal, an input second check code of default correspondence of each comparator
The datum of position, another input receives the corresponding code bit of the first check code.When check code contrast
When circuit receives the first check code, according to code bit order by each first verify code bit corresponding to level with
The datum of corresponding second verification code bit is compared.When all inputs of XOR gate are consistent,
Export for representing the correct instruction (such as high level) of verification；Conversely, exporting frequency reducing instruction (such as low electricity
It is flat).
The reset terminal and adjustable clock generating unit of the trigger 1133 in the check code comparing unit 113
Output end of the 112 frequency reducing command input with the XOR gate is connected.
For example, the reset terminal high level is effectively, frequency reducing command input Low level effective.When the verification
Code contrast circuit is exported for representing the correct instruction of verification, then the trigger 1133 is based on received having
Effect signal, reads the frequency reducing frequency counted in the adjustable clock generating unit 112, and deposited described in write-in
Storage unit 111.Now, the frequency reducing command input receives inactive level.
It is opposite, when the significant level of frequency reducing command input correspondence frequency reducing instruction, it is described can timing
Clock generating unit 112 performs frequency redution operation and updates the information related to clock signal frequency after frequency reducing (such as
Frequency reducing frequency etc.).Now, the reset terminal of the trigger 1133 receives inactive level.
In a kind of preferred embodiment, in order to prevent accidentally being proved to be successful, it is impossible to ensure that Sensitive Apparatus can run
Under the working environment of stabilization.The check code comparing unit 113 includes program process when being able to carry out following
Circuit.
Therefore, including multiple first check codes in the memory cell 111.The check code comparing unit 113
The first check code for being additionally operable to be provided the address generator 1131 enters with corresponding default second check code
Row compares, and when all comparative results are consistent, exports for representing the correct instruction of verification.
Specifically, the check code Comparison Circuit 1132 in the check code comparing unit 113 can according to it is current when
The temporal order of clock signal compares one by one；Or, the check code Comparison Circuit 1132 simultaneously will be acquired
It is multiple that first check code is corresponding with default each second check code compares.When all comparative results are consistent,
Export for representing the correct instruction of verification.
In another preferred scheme, the check code comparing unit 113 is additionally operable to according to default number of repetition,
The first check code and default second check code that the repetition address generator 1131 is provided, and
When all comparative results are consistent, export for representing the correct instruction of verification.
Specifically, the temporal order that the verification Comparison Circuit is provided according to current clock signal, repeats to compare
The first check code that the address generator 1131 is provided and default second check code.Compare when every time
When consistent, number of times is updated successfully, when number of success is consistent with number of repetition, then output represents that verification is correct
Instruction.
Due to it is described verification Comparison Circuit CPU startup before run, then it is described verification Comparison Circuit by comprising
The circuit that the hardware device such as comparator and door, XOR gate is constituted realizes the checking of above-mentioned various modes
Process.
The course of work of above-mentioned starting protection device 11 is exemplified below：
Sequential as shown in Figure 4, when upper electric, each hardware device in chip resets, wherein, adjustable clock
Generating unit 112 resets and exports clock signal T1 according to default highest frequency, and initializes the frequency reducing frequency
It is 0, in the case of current clock signal T1, the address generator 1131 in check code comparing unit 113
The address information of the first check code in generation memory cell 111, and the first check code is obtained, check code is compared
Circuit 1132 compares the first check code and default within several clock cycle of current clock signal T1
Second check code.
If consistent comparative result can be obtained under the frequency of current clock signal T1, in can assert chip
Such as memory cell 111, CPU Sensitive Apparatuses can run under the working frequency of current clock signal T1.
Based on this, the check code Comparison Circuit 1132 enables signal (i.e. to the coupled output of trigger 1133
For representing the correct instruction of verification), the frequency reducing that the enable signal will be recorded in adjustable clock generating unit 112
The frequency transports to memory cell 111 and is preserved and start the Sensitive Apparatuses such as CPU, and Sensitive Apparatus is with present clock
Based on the frequency of signal T1, or clock signal T1 is directly used as work clock, or when described
Frequency multiplication/frequency dividing is carried out on the basis of clock signal T1, its work clock is obtained.
If consistent comparative result can not be obtained under the frequency of current clock signal T1, in can assert chip
Such as memory cell 111, CPU Sensitive Apparatuses can cannot under the working frequency of current clock signal T1
Normal operation.Based on this, the check code Comparison Circuit 1132 is to coupled adjustable clock generating unit
112 output frequency reducing instructions, the adjustable clock generating unit 112 is based on the frequency reducing frequency of frequency reducing instruction change
It is 1, and adjusts the adjustable resistance R1 during adjustable clock occurs circuit, so that adjustable clock occurs circuit output
The correspondence frequency reducing frequency be 1, clock signal T2 (frequencies of T1 after frequency reducing>The frequency of T2).It is described
Address generator 1131 in check code comparing unit 113 is repeated under the frequency of new clock signal T2
Generation address information simultaneously reads the first check code, and transfer to check code Comparison Circuit 1132 to be verified, lays equal stress on
Newly judge under the frequency that clock signal T2 is provided, consistent comparative result can be obtained.So constantly drop
There is the clock signal of circuit output in low adjustable clock, until being verified.In this way, the starting protection dress
Put 11 and be able to ensure that what chip was caused by upper electric shaking interference, external electromagnetic interference, temperature and humidity interference etc.,
Under the conditions of high-frequency operation, Sensitive Apparatus in chip cannot normal work situation.
As shown in figure 5, the present invention also provides a kind of starting protection method of chip.Included in the chip and deposited
There are the memory cell of the first check code, and as above any described starting protection device.On chip during electricity,
The starting protection plant running, to perform the guard method.
In step sl, the starting protection device produces the clock signal of predeterminated frequency when upper electric.
Specifically, the starting protection device generates clock after electrification reset according to default peak frequency
Signal, and exported, to provide sequential for other devices in the starting protection device.Except this it
Outward, the frequency of the clock signal that the starting protection device is generated is adjustable.
In step s 2, the starting protection device compare the first check code that the memory cell preserved with
Default second check code；If consistent, step S3 is performed, if inconsistent, perform step S4.
Specifically, the starting protection device stores the first school during the correspondence memory cell is generated when upper electric
The address information of code is tested, and utilizes generated address information to obtain first check code.
Here, storage first is verified during the starting protection device generates the correspondence memory cell when upper electric
The address information of code, and read the first check code corresponding to generated address information from the memory cell.
Whether the starting protection device verifies two check codes by the way of hardware circuit consistent.
Specifically, the check code Comparison Circuit in the starting protection device can be used comprising multiple logical devices
Judge the first check code and the whether consistent decision circuitry of the second check code to constitute.
For example, in the check code contrast circuit comprising correspondence everybody comparator of the second check code and with it is each
The connected XOR gate of comparator output terminal, an input second check code of default correspondence of each comparator
The datum of position, another input receives the corresponding code bit of the first check code.When check code contrast
When circuit receives the first check code, according to code bit order by each first verify code bit corresponding to level with
The datum of corresponding second verification code bit is compared.When all inputs of XOR gate are consistent,
Perform step S3；Conversely, performing step S4.
The reset terminal of the trigger that the check code Comparison Circuit is connected and the drop of adjustable clock generating unit
Output end of the frequency command input with the XOR gate is connected.
For example, the reset terminal high level is effectively, frequency reducing command input Low level effective.When the verification
Code contrast circuit is exported for representing the correct instruction of verification, then the trigger is based on received effectively letter
Number, the frequency reducing frequency counted in the adjustable clock generating unit is read, and write the memory cell.
Now, the frequency reducing command input receives inactive level.
It is opposite, when the significant level of frequency reducing command input correspondence frequency reducing instruction, it is described can timing
Clock generating unit performs frequency redution operation.Now, the reset terminal of the trigger receives inactive level.
In a kind of preferred embodiment, in order to prevent accidentally being proved to be successful, it is impossible to ensure that Sensitive Apparatus can run
Under the working environment of stabilization.The starting protection device includes the circuit of program process when being able to carry out following.
Therefore, including multiple first check codes in the memory cell.The starting protection device is deposited described
Each first check code is stored in storage unit to be compared with corresponding default second check code, and in all comparings
When result is consistent, step S3 is performed.
Specifically, the check code Comparison Circuit in the starting protection device can according to current clock signal when
Sequence order compares one by one；Or, the check code Comparison Circuit is simultaneously by acquired multiple first check codes
It is corresponding with default each second check code to compare.When all comparative results are consistent, step S3 is performed.
In another preferred scheme, the starting protection device compares institute according to default number of repetition, repetition
The first check code and default second check code stored in memory cell are stated, and is in all comparative results
When consistent, step S3 is performed.
Specifically, the temporal order that the starting protection device is provided according to current clock signal, repeats to compare
The first check code that the address generator is provided and default second check code.When every time than more consistent
When, number of times is updated successfully, when number of success is consistent with number of repetition, then perform step S3.
Due to the starting protection device CPU startup before run, then the starting protection device by comprising
The circuit that the hardware device such as comparator and door, XOR gate is constituted realizes the checking of above-mentioned various modes
Process.
In step s3, each working hardware in the starting protection device flip chip is according to current frequency
Clock start signal runs.
Specifically, the starting protection device exports enabling signal to the memory cell in chip, CPU etc.,
And memory cell will be saved in the information of current clock signal frequency dependence (such as frequency reducing frequency).
In step s 4, the frequency of the clock signal produced by the starting protection device reduction, and hold again
Row step S2, untill comparison result is consistent.
Specifically, the adjustable clock generating unit in the starting protection device includes：Counter circuit and can
Adjust clock generating circuit.
The counter circuit is controlled by verification comparison circuit, counts the frequency reducing frequency, and based on the drop
Again and again there is the adjustable resistance in circuit in time adjustment adjustable clock, so that after its output reduces frequency
Clock signal.
There is the circuit unit that circuit is based on RC circuit theories and builds in the adjustable clock, including：
Adjustable resistance.The controlled end of the adjustable resistance is connected with the counter circuit, to adjust itself resistance.
The adjustable resistance also resets to preset resistive value when upper electric, and circuit occurs upper to allow the adjustable clock
The clock signal of predeterminated frequency is exported when electric.Wherein, the predeterminated frequency is workable for the chip most
High-frequency.For example, the adjustable clock generating unit output predeterminated frequency is the clock of 50MHz when upper electric
Signal.
The counter circuit progressively adjusts adjustable resistance according to the step-length of default adjustable resistance resistance,
To reduce frequency.
For example, being preset with resistance step-length in the counter circuit for a, the counter circuit is often exported
Resistance step-length a, the adjustable resistance that the adjustable clock occurs in circuit is just corresponded to be increased/reduce resistance a.
Designed according to side circuit, the change of adjustable resistance resistance, will cause that RC circuits export sinusoidal signal
Frequency correspondence is reduced, by the shaping to sinusoidal signal, the adjustable clock occurs circuit will be exported
Clock signal after frequency reducing.
Preferably, with reference to Fig. 2, the adjustable clock occurs circuit to be included：Comparator, the resistance R0 of series connection
Some switches sets, ground capacity, the shaping of correspondence switches set quantity cascaded with adjustable resistance R1, controlled end
Module.
The negative input end connection reference voltage of the comparator, positive input terminal are accessed between resistance R0 and R1,
The output end of the comparator is grounded by resistance R0 and R1, while the input also with each switches set is connected,
The signal output part of each switches set connects corresponding ground capacity.Wherein, the controlled end of rear stage switches set connects
The signal output part of previous stage switches set is connect, the signal output part connection Shaping Module of afterbody switches set
Input.Meanwhile, the controlled end of first order switches set is also connected with the input of Shaping Module.
The course of work of above-mentioned starting protection device is exemplified below：
Sequential as shown in Figure 4, when upper electric, each hardware device in chip resets, wherein, can timing
Clock generating unit resets and simultaneously export clock signal T1 according to default highest frequency, and initializes the frequency reducing frequency and be
0, in the case of current clock signal T1, the first check code in check code comparing unit generation memory cell
Address information, and within several clock cycle of current clock signal T1, compare the first check code and pre-
If the second check code.
If consistent comparative result can be obtained under the frequency of current clock signal T1, in can assert chip
Such as memory cell, CPU Sensitive Apparatuses can run under the working frequency of current clock signal T1.Base
In this, it is single that the frequency reducing frequency recorded in adjustable clock generating unit is transported to storage by the check code comparing unit
Unit is preserved and is started the Sensitive Apparatuses such as CPU, and Sensitive Apparatus is with the frequency of current clock signal T1 as base
Plinth, or clock signal T1 is directly used as work clock, or on the basis of the clock signal T1
Frequency multiplication/frequency dividing is carried out, its work clock is obtained.
If consistent comparative result can not be obtained under the frequency of current clock signal T1, in can assert chip
Such as memory cell, CPU Sensitive Apparatuses can cannot be normal under the working frequency of current clock signal T1
Operation.Based on this, the check code Comparison Circuit exports frequency reducing to coupled adjustable clock generating unit
Instruction, the frequency reducing frequency that the adjustable clock generating unit is based on frequency reducing instruction change is 1, and adjusts adjustable
Resistance R1 so that adjustable clock occur the circuit output correspondence frequency reducing frequency be 1, clock after frequency reducing letter
Number T2 (frequencies of T1>The frequency of T2).Frequency of the check code comparing unit in new clock signal T2
Under rate, repeatedly generate address information and read the first check code, and verified, to rejudge in clock
Under the frequency that signal T2 is provided, consistent comparative result can be obtained.So constantly reduce adjustable clock hair
The clock signal of raw circuit output, until being verified.In this way, the starting protection device is able to ensure that core
Piece is caused by upper electric shaking interference, external electromagnetic interference, temperature and humidity interference etc., in high-frequency operation
Under the conditions of, Sensitive Apparatus in chip cannot normal work situation.
In sum, the starting protection device and method of chip of the invention, chip, by the chips
The frequency of clock signal is verified using part number circuit before Sensitive Apparatus startup work, and according to testing
Card result is adjusted to the frequency of current clock signal, and the present invention is by reducing chip operation clock frequency
Mode, it is ensured that the stability of a system of chip, effectively prevent the CPU that occurs when chip runs mispronounce information,
Program run-time error, reset repeatedly and the vicious circle such as restart；In addition, by the way of progressively frequency reducing, can
For chip provides clock frequency as high as possible, it is ensured that the operating efficiency of chip；Further, in order to prevent accidentally
It is proved to be successful, and for Sensitive Apparatus provides the clock frequency for being not suitable for working environment, the present invention is also using multiple
The mode of checking, it is ensured that whole system trouble free service demand in any condition.So, the present invention
Effectively overcome various shortcoming of the prior art and have high industrial utilization.
The above-described embodiments merely illustrate the principles and effects of the present invention, not for the limitation present invention.
Any person skilled in the art can all enter under without prejudice to spirit and scope of the invention to above-described embodiment
Row modifications and changes.Therefore, such as those of ordinary skill in the art without departing from institute of the present invention
All equivalent modifications completed under the spirit and technological thought of announcement or change, should be by right of the invention
It is required that being covered.
Claims (11)
1. the starting protection device of a kind of chip, it is characterised in that including：
There is the memory cell of the first check code；
Adjustable clock generating unit, the clock signal for exporting predeterminated frequency after the power-up, and according to being connect
The frequency reducing instruction of receipts reduces the frequency of exported clock signal；
The check code comparing unit being connected with the adjustable clock generating unit and memory cell, for comparing
The first check code and default second check code that memory cell is preserved are stated, if unanimously, in flip chip
Each working hardware according to current frequency clock start signal run, if inconsistent, to the adjustable clock
Generating unit sends the frequency reducing instruction.
2. the starting protection device of chip according to claim 1, it is characterised in that the adjustable clock
Generating unit includes：There is circuit in counter circuit and the adjustable clock comprising adjustable resistance；
The counter circuit is used to be based on the received frequency reducing instruction count frequency reducing frequency, and based on described
The frequency reducing frequency adjusts the adjustable resistance.
3. the starting protection device of chip according to claim 2, it is characterised in that the adjustable clock
Generation circuit includes：Comparator, the resistance R0 of series connection and adjustable resistance R1, some the opening of controlled end cascade
Ground capacity, the Shaping Module of pass group, correspondence switches set quantity；
The negative input end connection reference voltage of the comparator, positive input terminal are accessed between resistance R0 and R1,
The output end of the comparator is grounded by resistance R0 and R1, while the input also with each switches set is connected,
The signal output part of each switches set connects corresponding ground capacity.Wherein, the controlled end of rear stage switches set connects
The signal output part of previous stage switches set is connect, the signal output part connection Shaping Module of afterbody switches set
Input.Meanwhile, the controlled end of first order switches set is also connected with the input of Shaping Module.
4. the starting protection device of chip according to claim 1, it is characterised in that the check code ratio
Unit is included：
The address generator being connected with the memory cell, for generating the correspondence memory cell when upper electric
The address information of the first check code of middle storage, and utilize generated address information to obtain first check code；
The check code Comparison Circuit being connected with the address generator and adjustable clock generating unit, in the future
Compare from first check code and default second check code of the address generator, if unanimously,
Export for representing the correct instruction of verification, if inconsistent, after record adjustment with clock signal frequency phase
The information of pass, and send the frequency reducing instruction to the adjustable clock generating unit；
The trigger being connected with the check code Comparison Circuit, for based on received for represent verification just
True instruction, triggers the check code Comparison Circuit and the relevant information of presently described clock signal is saved in into institute
In stating memory cell, and each working hardware is indicated to be run according to the clock start signal of current frequency.
5. the starting protection device of chip according to claim 1, it is characterised in that the memory cell
In include multiple first check codes；Corresponding, the check code comparing unit is additionally operable to there is the address
The first check code that device is provided is compared with corresponding default second check code, and in all comparative results
For it is consistent when, export for representing the correct instruction of verification.
6. the starting protection device of chip according to claim 1, it is characterised in that the check code ratio
Unit is additionally operable to according to default number of repetition, repeats the first verification that the address generator is provided
Code and default second check code, and when all comparative results are consistent, export for representing verification just
True instruction.
7. a kind of chip, it is characterised in that including：
Starting protection device as described in any in claim 1-5.
8. a kind of starting protection method of chip, wherein, comprising the storage for having the first check code in the chip
Unit, it is characterised in that including：
The clock signal of predeterminated frequency is produced when upper electric；
Compare the first check code and default second check code that the memory cell is preserved；
If consistent, each working hardware in flip chip runs according to the clock start signal of current frequency；
If inconsistent, the frequency of produced clock signal is reduced, two check codes are compared again, until than
Untill being consistent to result.
9. the starting protection method of chip according to claim 7, it is characterised in that described in the comparison
The first check code that memory cell is preserved includes with the mode of default second check code：
The address information of the first check code is stored in the generation correspondence memory cell when upper electric, and utilizes institute
The address information of generation obtains first check code；
Acquired the first check code and default second check code are compared.
10. the starting protection method of chip according to claim 7, it is characterised in that first verification
Code is multiple；It is corresponding, it is described to compare the first check code and the default second verification that memory cell is preserved
The mode of code includes：
Each first check code will be stored in the memory cell to be compared with corresponding default second check code,
And when all comparative results are consistent, export for representing the correct instruction of verification.
The starting protection method of 11. chips according to claim 7, it is characterised in that the comparison storage
The first check code that unit is preserved includes with the mode of default second check code：
According to default number of repetition, repeat the first check code for being stored in the memory cell with it is default
Second check code, and when all comparative results are consistent, export for representing the correct instruction of verification.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000312.3A CN106919857B (en) | 2015-12-28 | 2015-12-28 | Chip, and starting protection device and method of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000312.3A CN106919857B (en) | 2015-12-28 | 2015-12-28 | Chip, and starting protection device and method of chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106919857A true CN106919857A (en) | 2017-07-04 |
| CN106919857B CN106919857B (en) | 2019-11-12 |
Family
ID=59455915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511000312.3A Active CN106919857B (en) | 2015-12-28 | 2015-12-28 | Chip, and starting protection device and method of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106919857B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111274196A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Start control device and method |
| CN113032791A (en) * | 2021-04-01 | 2021-06-25 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
| CN113065173A (en) * | 2021-04-22 | 2021-07-02 | 西安电掣风云智能科技有限公司 | Encryption method and device for protecting processor embedded algorithm and storage medium |
| CN113176965A (en) * | 2021-04-25 | 2021-07-27 | 山东英信计算机技术有限公司 | Board burning prevention method, system and medium based on VR configuration CRC check |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055486A (en) * | 2010-12-29 | 2011-05-11 | 启东金凤凰科技发展有限公司 | Application of low-density check code in wireless data communication |
| CN102445916A (en) * | 2011-09-15 | 2012-05-09 | 福建星网锐捷网络有限公司 | Method and system of programmable controller and clock frequency control |
| CN103268459A (en) * | 2012-08-01 | 2013-08-28 | 天地融科技股份有限公司 | Electronic device with secure character library, and electronic equipment with electronic device |
-
2015
- 2015-12-28 CN CN201511000312.3A patent/CN106919857B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055486A (en) * | 2010-12-29 | 2011-05-11 | 启东金凤凰科技发展有限公司 | Application of low-density check code in wireless data communication |
| CN102445916A (en) * | 2011-09-15 | 2012-05-09 | 福建星网锐捷网络有限公司 | Method and system of programmable controller and clock frequency control |
| CN103268459A (en) * | 2012-08-01 | 2013-08-28 | 天地融科技股份有限公司 | Electronic device with secure character library, and electronic equipment with electronic device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111274196A (en) * | 2018-12-05 | 2020-06-12 | 锐迪科（重庆）微电子科技有限公司 | Start control device and method |
| CN111274196B (en) * | 2018-12-05 | 2023-08-22 | 锐迪科（重庆）微电子科技有限公司 | Start control device and method |
| CN113032791A (en) * | 2021-04-01 | 2021-06-25 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
| CN113065173A (en) * | 2021-04-22 | 2021-07-02 | 西安电掣风云智能科技有限公司 | Encryption method and device for protecting processor embedded algorithm and storage medium |
| CN113176965A (en) * | 2021-04-25 | 2021-07-27 | 山东英信计算机技术有限公司 | Board burning prevention method, system and medium based on VR configuration CRC check |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106919857B (en) | 2019-11-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106919857A (en) | Chip, and starting protection device and method of chip | |
| CN108885475B (en) | System and method for adaptive clock design | |
| CN108363640B (en) | Data verification method and device and computer readable storage medium | |
| US9449153B2 (en) | Unique and unclonable platform identifiers using data-dependent circuit path responses | |
| CN110334007A (en) | A kind of functional interface calls verification method and device, electronic equipment and storage medium | |
| US7526087B2 (en) | Random number generator | |
| WO2017112339A1 (en) | Serial i/o functional tester | |
| US20180181187A1 (en) | Method for dynamically updating financial data and processing system using the same, and method for dynamically adjusting power configuration and processing system using the same | |
| CN108829596A (en) | Interrupt random verification method, device, computer equipment and storage medium | |
| CN109240130B (en) | Programmable pin level control circuit | |
| CN105956322A (en) | Process corner detection device and method of digital circuit | |
| CN103973266B (en) | Oscillator correction circuit and method and integrated circuit | |
| CN106160739B (en) | Clock data recovery circuit module, memory storage apparatus and phase-locking method | |
| US10627841B2 (en) | Reference voltage generation circuit with reduced process variation on the reference voltage | |
| US9837170B2 (en) | Systems and methods for testing performance of memory modules | |
| CN109407807A (en) | A kind of chip reset circuit, repositioning method and MCU chip | |
| CN203338067U (en) | Circuit structure controlled by programming by OTP storage element in embedded system | |
| WO2018236502A1 (en) | Tunable delay control of a power delivery network | |
| CN104133966A (en) | Faulty circuit behavior modeling method based on signal feature extraction | |
| CN105677527A (en) | System and method for automatically measuring maximum working frequency of embedded memory | |
| CN114155888B (en) | Hard disk power supply control device and method, computer equipment and storage medium | |
| CN208654778U (en) | A kind of OTA upgrading circuit | |
| JP6062795B2 (en) | Semiconductor device | |
| CN106406425A (en) | EMMC access method and apparatus | |
| CN111382822A (en) | Chip and method for manufacturing the same |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |