CN111274196B - Start control device and method - Google Patents
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- CN111274196B CN111274196B CN201811481465.8A CN201811481465A CN111274196B CN 111274196 B CN111274196 B CN 111274196B CN 201811481465 A CN201811481465 A CN 201811481465A CN 111274196 B CN111274196 B CN 111274196B
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- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
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Abstract
The present disclosure relates to a start control apparatus and method. The device comprises: a plurality of processing chips connected in series; a control chip connected to a first stage of the plurality of processing chips and configured to: at a first moment when the plurality of processing chips are started, sending a starting signal with a first frequency to a first-stage processing chip, so that the plurality of processing chips sequentially run at the first frequency; at a second moment which is spaced from the first moment by a first time length, sending a starting signal of the next starting frequency to the first-stage processing chip; and at a third time which is spaced from the time for transmitting the starting signal of the Mth starting frequency by a second time length, transmitting the starting signal of the target frequency to the first-stage processing chip, so that a plurality of processing chips sequentially run at the target frequency. In the starting process, a plurality of starting frequencies are sequentially configured, so that the operating frequencies of a plurality of processing chips are sequentially adjusted upwards, the voltage distribution of each chip is balanced, and the performance of a link is improved.
Description
Technical Field
The disclosure relates to the field of electronic technology, and in particular, to a start control device and a start control method.
Background
In the current chip design, a multi-chip cascade mode is generally adopted to improve the overall information processing capability. When multiple chips are cascaded, in the period from the start of a link to the stable operation, the impedance fluctuation generated by each chip is large due to the difference of the frequency, the calculation force and the like of the chips, and the voltage distributed to each chip is unstable. If the voltage value of each chip on the whole link is too large, the performance of the whole link is affected, and even functional errors or chip damage can occur.
Disclosure of Invention
In view of this, the disclosure proposes a start control device and method, which can stabilize impedance fluctuation of each chip on a link in a multi-chip cascade link start process, so as to balance voltage distribution of each chip, improve performance of the whole link, and avoid occurrence of functional errors or chip damage.
According to an aspect of the present disclosure, there is provided a start control apparatus including:
a plurality of processing chips connected in series;
a control chip connected to a first level processing chip of the plurality of processing chips, the control chip configured to:
at a first moment when the plurality of processing chips are started, sending a starting signal with a first frequency to the first-stage processing chip so that the plurality of processing chips sequentially run at the first frequency, wherein the first frequency is the first of M preset starting frequencies, and M is an integer larger than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second time which is spaced from the first time by a first time length, wherein the first time length corresponds to the first frequency;
at a third time spaced from the time of transmitting the start signal of the mth start frequency by a second time period, transmitting the start signal of the target frequency to the first stage processing chip so that the plurality of processing chips sequentially operate at the target frequency, wherein the second time period corresponds to the mth start frequency,
wherein the M start frequencies are less than the target frequency.
In one possible implementation, each processing chip includes N sets of processing units, N being an integer greater than 1,
wherein the control chip is further configured to:
at a fourth moment when the plurality of processing chips are started, a first configuration signal in N preset configuration signals is sent to the first-stage processing chip, so that a first group of processing units in N groups of processing units of each processing chip are started;
according to the corresponding relation between the N configuration signals and the duration, at a fifth moment which is spaced from the fourth moment by a third duration, a next configuration signal is sent to the first-stage processing chip so as to enable a second group of processing units in the N groups of processing units of each processing chip to be started, wherein the third duration corresponds to the first configuration signal;
and at a sixth moment of a fourth time length between the moment of transmitting the N-1 th configuration signal and the moment of transmitting the N-1 th configuration signal, transmitting the N-th configuration signal to the first-stage processing chip so as to enable an N-th group of processing units in N groups of processing units of each processing chip to be started, wherein the fourth time length corresponds to the N-1 th configuration signal.
In one possible implementation, the duration corresponding to each start-up frequency is greater than the duration required for the plurality of processing chips to run smoothly in sequence.
In one possible implementation, the duration corresponding to each start-up frequency is the same.
In one possible implementation, the M start frequencies increase with a transmission sequence of the start signals.
In one possible implementation, each set of processing units includes at least one processing unit.
In one possible implementation, the duration corresponding to each configuration signal is greater than the duration required for the plurality of processing chips to run smoothly in sequence.
In one possible implementation, the duration corresponding to each configuration signal is the same.
According to another aspect of the present disclosure, there is provided a start-up control method applied to a control chip of a start-up control apparatus, the apparatus further including a plurality of processing chips connected in series, the control chip being connected to a first stage of processing chips among the plurality of processing chips, the method including:
at a first moment when the plurality of processing chips are started, sending a starting signal with a first frequency to the first-stage processing chip so that the plurality of processing chips sequentially run at the first frequency, wherein the first frequency is the first of M preset starting frequencies, and M is an integer larger than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second time which is spaced from the first time by a first time length, wherein the first time length corresponds to the first frequency;
at a third time spaced from the time of transmitting the start signal of the mth start frequency by a second time period, transmitting the start signal of the target frequency to the first stage processing chip so that the plurality of processing chips sequentially operate at the target frequency, wherein the second time period corresponds to the mth start frequency,
wherein the M start frequencies are less than the target frequency.
In one possible implementation, each processing chip includes N sets of processing units, N being an integer greater than 1,
wherein the method further comprises:
at a fourth moment when the plurality of processing chips are started, a first configuration signal in N preset configuration signals is sent to the first-stage processing chip, so that a first group of processing units in N groups of processing units of each processing chip are started;
according to the corresponding relation between the N configuration signals and the duration, at a fifth moment which is spaced from the fourth moment by a third duration, a next configuration signal is sent to the first-stage processing chip so as to enable a second group of processing units in the N groups of processing units of each processing chip to be started, wherein the third duration corresponds to the first configuration signal;
and at a sixth moment of a fourth time length between the moment of transmitting the N-1 th configuration signal and the moment of transmitting the N-1 th configuration signal, transmitting the N-th configuration signal to the first-stage processing chip so as to enable an N-th group of processing units in N groups of processing units of each processing chip to be started, wherein the fourth time length corresponds to the N-1 th configuration signal.
According to the embodiment of the disclosure, in the starting process of the multi-chip cascade link, the control chip is used for sending the starting frequency to the first-stage processing chip in the plurality of processing chips, so that the running frequency of each processing chip is sequentially adjusted upwards, the impedance fluctuation of each chip on the link is stabilized in the starting process of the multi-chip cascade link, the voltage distribution of each chip is balanced, the performance of the whole link is improved, and the situation of functional errors or chip damage is avoided.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features and aspects of the present disclosure and together with the description, serve to explain the principles of the disclosure.
FIG. 1 illustrates a block diagram of a start-up control device according to an embodiment of the present disclosure;
FIG. 2 illustrates a schematic diagram of a startup process of a startup control device according to an embodiment of the present disclosure;
FIG. 3 illustrates a schematic diagram of a start-up process of a start-up control device according to an embodiment of the present disclosure;
fig. 4 shows a flowchart of a startup control method according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the disclosure will be described in detail below with reference to the drawings. In the drawings, like reference numbers indicate identical or functionally similar elements. Although various aspects of the embodiments are illustrated in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
In addition, numerous specific details are set forth in the following detailed description in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements, and circuits well known to those skilled in the art have not been described in detail in order not to obscure the present disclosure.
Fig. 1 shows a block diagram of a start-up control device according to an embodiment of the present disclosure. As shown in fig. 1, the starting device includes:
a plurality of processing chips 12 connected in series;
a control chip 11 connected to a first stage processing chip 121 of the plurality of processing chips,
the control chip 11 is configured to:
at a first moment when the plurality of processing chips 12 are started, sending a starting signal with a first frequency to the first stage processing chip 121 so that the plurality of processing chips 12 sequentially run at the first frequency, wherein the first frequency is the first of a preset M starting frequencies, and M is an integer greater than 1;
according to the correspondence between the M starting frequencies and the duration, sending a starting signal of the next starting frequency to the first stage processing chip 121 at a second moment spaced from the first moment by a first duration, where the first duration corresponds to the first frequency;
at a third time spaced from the time of transmitting the start signal of the mth start frequency by a second time period corresponding to the mth start frequency, transmitting the start signal of the target frequency to the first stage processing chip 121 to cause the plurality of processing chips 12 to sequentially operate at the target frequency,
wherein the M start frequencies are less than the target frequency.
According to the embodiment of the disclosure, in the starting process of the multi-chip cascade link, the control chip sends the preset M starting frequencies and the preset target frequency to the first-stage processing chip, so that all chips on the link run at the same frequency, the impedance changes of the chips tend to be stable and similar, the distribution of voltages is balanced, and the performance of the whole link is improved.
For example, M start frequencies (M is an integer greater than 1) may be preset to configure the start frequencies for the respective processing chips on the link. Wherein M start frequencies can representIs f 1 、f 2 、……、f M M start frequencies f 1 、f 2 、……、f M Are all smaller than the target frequency f of the plurality of processing chips 12 on the link in normal operation T 。
In one possible implementation, each start-up frequency may correspond to a duration that is greater than or equal to the duration required for the respective processing chip on the link to run smoothly at the corresponding start-up frequency. After the multiple processing chips 12 receive the new starting frequency, the operating frequency is adjusted to the newly received starting frequency and a certain time is required for stable operation, and the time length corresponding to each starting frequency is set to be longer than the time length required by the multiple processing chips 12 to operate in sequence, so that each processing chip on the link can operate stably. In this way, correspondence (e.g., mapping table) between M start frequencies and durations may be established.
Fig. 2 is a schematic diagram of a start-up procedure of a start-up control device according to an embodiment of the present disclosure. In one possible implementation, as shown in fig. 2, at a first time when the plurality of processing chips 12 are activated, the control chip 11 may send the first frequency f to the first stage processing chip 121 1 The plurality of processing chips 12 sequentially operate at a first frequency f 1 And (5) running. For example, a first frequency f 1 May be a clock-configurable minimum frequency 26M of the control chip 11.
In one possible implementation, the first frequency f is transmitted at the control chip 11 1 After the start signal of (2), according to the corresponding relation between M start frequencies and time length, the first frequency f can be determined 1 After the start signal (first time period T 1 ). Thus, at a first time interval of a first time period T 1 The control chip 11 can send the next start frequency f to the first stage processing chip 121 2 To enable the plurality of processing chips 12 to sequentially operate at an enabling frequency f 2 And (5) running. For example, f 2 Configured as 100M.
In one possible implementation manner, according to the preset sending order of the M start frequencies and the corresponding relation between the start frequencies and the duration, the control chip 11 may send the next start frequency at intervals corresponding to the duration after sending one start frequency until the M start frequencies are sequentially sent to complete. During this time, the plurality of processing chips 12 are each operated at the received start-up frequency.
In one possible implementation, the control chip 11 sends the mth start frequency f M After the start signal of (2), according to the corresponding relation between M start frequencies and time length, the transmission f can be determined M After the start signal (second time period T M ). Thus, the second time period T is spaced from the time of transmitting the start signal of the Mth start frequency M The control chip 11 can send the target frequency f to the first stage processing chip 121 T To enable the plurality of processing chips 12 to sequentially operate at a target frequency f T And (5) running.
It will be appreciated that the chip is different and the target frequency f of its operation is T Possibly different, the target frequency f can be set according to the actual situation T The present disclosure is not limited in this regard.
In one possible implementation, the duration corresponding to each start-up frequency is the same. That is, the duration of the M start-up frequencies may be set to a fixed longer duration (e.g., 0.5 seconds), so as to ensure that the multiple processing chips 12 on the link can operate smoothly in each case.
In one possible implementation, the duration of the M start frequencies may also be set to correspond to the time required for data transmission at each start frequency, for example, the duration corresponding to each start frequency is set to be greater than the number of clock cycles according to the number of clock cycles required for data transmission from the control chip 11 to the last stage processing chip.
In one possible implementation, the duration of the M start frequencies may be further set according to the feedback signals of the steady operation of the multiple processing chips, for example, after the control chip 11 sends a start signal of one start frequency to the first stage processing chip 121, the control chip receives the feedback signals of the steady operation of the multiple processing chips 12 at the start frequency, and the duration corresponding to each start frequency may be set to be greater than the time interval between the start signal and the feedback signal thereof.
The specific values of the corresponding durations of the starting frequencies are not limited in the present disclosure.
In one possible implementation, the M start frequencies may increase with the order of transmission of the start signals. That is, M start frequencies f 1 、f 2 、f 3 、……、f M For example, the values of the M starting frequencies can be sequentially configured to be 26M, 100M, and 200M … …, and the operating frequencies of the plurality of processing chips 12 can be gradually increased upwards by configuring the starting frequencies to increase along with the transmission sequence, so that the performance and efficiency of the whole link are improved. It should be understood that, the preset starting frequencies may be different from one chip to another, and the specific setting values of the starting frequencies are not limited in this disclosure.
Fig. 3 shows a schematic diagram of a start-up procedure of a start-up control device according to an embodiment of the present disclosure. As shown in fig. 3, in one possible implementation, each processing chip includes N groups of processing units, N being an integer greater than 1, where the control chip 11 is further configured to:
at a fourth moment when the plurality of processing chips 12 are started, a first configuration signal of the preset N configuration signals is sent to the first stage processing chip 121, so that a first group of processing units of the N groups of processing units of each processing chip are started;
according to the correspondence between the N configuration signals and the duration, at a fifth moment spaced from the fourth moment by a third duration, a next configuration signal is sent to the first stage processing chip 121, so that a second group of processing units in the N groups of processing units of each processing chip is started, and the third duration corresponds to the first configuration signal;
and at a sixth time spaced from the time of transmitting the (N-1) th configuration signal by a fourth time length, the nth configuration signal is transmitted to the first stage processing chip 121, so that the nth group of processing units in the N groups of processing units of each processing chip is started, and the fourth time length corresponds to the (N-1) th configuration signal.
According to the embodiment of the disclosure, in the starting process of the multi-chip cascade link, the control chip sends the preset N configuration signals to the first-stage processing chip, so that N groups of processing units in each chip on the link are sequentially started, impedance changes of the chips tend to be stable and similar, voltage distribution is balanced, and the performance of the whole link is improved.
For example, each processing chip includes N groups of processing units (N is an integer greater than 1), corresponding to the N groups of processing units, N configuration signals can be preset, and the N configuration signals can be expressed as S 1 ，S 2 ，……S N 。
In one possible implementation, each configuration signal may correspond to a duration that is greater than or equal to the duration required by each processing chip on the link to initiate smooth operation of the corresponding processing unit. After receiving the new configuration signals, the multiple processing chips 12 start a new group of processing units and a certain time is required for reaching stable operation, and the time length corresponding to each configuration signal is set to be longer than the time, so that each chip on the link can be stably operated. In this way, correspondence (e.g., a mapping table) between the N configuration signals and the duration can be established.
In one possible implementation, at the fourth moment when the multiple processing chips 12 are started, the control chip 11 sends a first configuration signal S of the preset N configuration signals to the first stage processing chip 121 1 The plurality of processing chips 12 are arranged according to the first configuration signal S 1 The first set of processing units of each processing chip is started in turn.
In one possible implementation, the control chip 11 sends a first configuration signal S 1 Then, according to the corresponding relation between the N configuration signals and the duration, the first configuration signal S can be determined to be sent 1 Later waiting time period (third time period T S1 ). Thus, at a third time period T from the fourth time period S1 The control chip 11 can send the next configuration signal S to the first stage processing chip 121 2 So that the plurality of processing chips 12 sequentially activate the second group of processing chipsAnd (5) a management unit.
In one possible implementation manner, according to the preset transmission order of the N configuration signals and the corresponding relation between the configuration signals and the duration, the control chip 11 transmits one configuration signal and the next configuration signal at intervals corresponding to the duration until the N-1 configuration signals are sequentially transmitted. During this time, the plurality of processing chips 12 activate corresponding ones of the N groups of processing units of the respective processing chips in accordance with the received configuration signals;
in one possible implementation, after the control chip 11 transmits the nth-1 st configuration signal, the transmission of the nth configuration signal S may be determined according to the correspondence between the nth configuration signal and the duration N The previous waiting time period (fourth time period T SN-1 ). Thus, a fourth time period T is provided between the transmission of the N-1 th configuration signal and the transmission of the N-1 st configuration signal SN-1 The control chip 11 can send an Nth configuration signal S to the first stage processing chip 121 N So that an nth group of processing units among the N groups of processing units of the respective processing chips is started.
In one possible implementation, each set of processing units includes at least one processing unit. Of the N configuration signals sent by the control chip 11 to the first stage processing chip 121, each configuration signal corresponds to a set of processing units, and each set of processing units includes at least one processing unit. For example, the first set of processing units comprises one processing unit and the second set of processing units comprises one processing unit. The number of the processing units included in each group of processing units may be the same or different, and the specific number of the processing units included in each group of processing units is not limited in the disclosure.
In one possible implementation, the duration corresponding to each configuration signal is the same. That is, the duration of the N configuration signals may be set to a fixed longer duration (e.g., 0.5 seconds), so as to ensure that the multiple processing chips 12 on the link can operate smoothly in each case.
In a possible implementation, the duration of the N configuration signals may also be set to correspond to the time required for the data transfer of the activated processing unit, for example, the duration corresponding to each configuration signal is set to be greater than the number of clock cycles according to the number of clock cycles required for the data transfer from the control chip 11 to the last stage processing chip.
In one possible implementation, the duration of the N configuration signals may be further set according to feedback signals of the steady operation of the multiple processing chips, for example, after the control chip 11 sends a configuration signal to the first stage processing chip 121, the control chip 11 receives feedback signals of the steady operation of the corresponding processing units according to the configuration signal, and the duration corresponding to each configuration signal may be set to be greater than a time interval between the configuration signal and the feedback signal thereof.
The present disclosure does not limit the specific value of the corresponding duration of each configuration signal.
In a possible implementation manner, during starting of the multi-chip cascade link, the control chip 11 may send a starting frequency to the first stage processing chip 121 to gradually adjust the operating frequency, or send configuration signals to the first stage processing chip 121 in sequence to start the corresponding processing unit group, where there is no requirement of a given usage manner, and the two may be set according to actual needs, for example, a manner of setting the starting frequency first and then setting the configuration signals, a manner of setting the configuration signals first and then setting the starting frequency, or a manner of setting the starting frequency and setting the configuration signals in combination may be adopted. The present disclosure does not limit the manner in which the start frequency and the set configuration signal are used in the start process.
Fig. 4 shows a flowchart of a startup control method according to an embodiment of the present disclosure. As shown in fig. 4, the method is applied to a control chip of a start control device, the device further including a plurality of processing chips connected in series, the control chip being connected to a first stage of processing chips among the plurality of processing chips, the method including:
step S41, at a first moment when the plurality of processing chips are started, sending a starting signal with a first frequency to the first-stage processing chip so that the plurality of processing chips sequentially run at the first frequency, wherein the first frequency is the first of M preset starting frequencies, and M is an integer greater than 1;
step S42, according to the corresponding relation between M starting frequencies and duration, a starting signal of the next starting frequency is sent to the first-stage processing chip at a second moment which is spaced from the first moment by a first duration, wherein the first duration corresponds to the first frequency;
step S43, at a third time spaced from the time of sending the starting signal of the Mth starting frequency by a second time, sending the starting signal of the target frequency to the first-stage processing chip, so that the processing chips sequentially run at the target frequency, wherein the second time corresponds to the Mth starting frequency, and the M starting frequencies are smaller than the target frequency.
In one possible implementation, each processing chip includes N sets of processing units, N being an integer greater than 1, wherein the method further includes:
at a fourth moment when the plurality of processing chips are started, a first configuration signal in N preset configuration signals is sent to the first-stage processing chip, so that a first group of processing units in N groups of processing units of each processing chip are started;
according to the corresponding relation between the N configuration signals and the duration, at a fifth moment which is spaced from the fourth moment by a third duration, a next configuration signal is sent to the first-stage processing chip so as to enable a second group of processing units in the N groups of processing units of each processing chip to be started, wherein the third duration corresponds to the first configuration signal;
and at a sixth moment of a fourth time length between the moment of transmitting the N-1 th configuration signal and the moment of transmitting the N-1 th configuration signal, transmitting the N-th configuration signal to the first-stage processing chip so as to enable an N-th group of processing units in N groups of processing units of each processing chip to be started, wherein the fourth time length corresponds to the N-1 th configuration signal.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the various embodiments described. The terminology used herein was chosen in order to best explain the principles of the embodiments, the practical application, or the technical improvement of the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (8)
1. A start-up control device, the device comprising:
a plurality of processing chips connected in series;
a control chip connected to a first level processing chip of the plurality of processing chips, the control chip configured to:
at a first moment when the plurality of processing chips are started, sending a starting signal with a first frequency to the first-stage processing chip so that the plurality of processing chips sequentially run at the first frequency, wherein the first frequency is the first of M preset starting frequencies, and M is an integer larger than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second time which is spaced from the first time by a first time length, wherein the first time length corresponds to the first frequency;
at a third time spaced from the time of transmitting the start signal of the mth start frequency by a second time period, transmitting the start signal of the target frequency to the first stage processing chip so that the plurality of processing chips sequentially operate at the target frequency, wherein the second time period corresponds to the mth start frequency,
wherein the M start frequencies are less than the target frequency; the duration corresponding to each starting frequency is longer than the duration required by the plurality of processing chips to run stably in sequence; the M start frequencies increase with the transmission order of the start signals.
2. The apparatus of claim 1, wherein each processing chip comprises N sets of processing units, N being an integer greater than 1,
wherein the control chip is further configured to:
at a fourth moment when the plurality of processing chips are started, a first configuration signal in N preset configuration signals is sent to the first-stage processing chip, so that a first group of processing units in N groups of processing units of each processing chip are started;
according to the corresponding relation between the N configuration signals and the duration, at a fifth moment which is spaced from the fourth moment by a third duration, a next configuration signal is sent to the first-stage processing chip so as to enable a second group of processing units in the N groups of processing units of each processing chip to be started, wherein the third duration corresponds to the first configuration signal;
and at a sixth moment of a fourth time length between the moment of transmitting the N-1 th configuration signal and the moment of transmitting the N-1 th configuration signal, transmitting the N-th configuration signal to the first-stage processing chip so as to enable an N-th group of processing units in N groups of processing units of each processing chip to be started, wherein the fourth time length corresponds to the N-1 th configuration signal.
3. The apparatus of claim 1, wherein a duration corresponding to each of the activation frequencies is the same.
4. The apparatus of claim 2, wherein each set of processing units comprises at least one processing unit.
5. The apparatus of claim 2, wherein a duration corresponding to each configuration signal is greater than a duration required for the plurality of processing chips to run smoothly in sequence.
6. The apparatus of claim 2, wherein a duration corresponding to each configuration signal is the same.
7. A start-up control method, characterized in that the method is applied to a control chip of a start-up control device, the device further comprising a plurality of processing chips connected in series, the control chip being connected to a first stage of processing chips of the plurality of processing chips, the method comprising:
at a first moment when the plurality of processing chips are started, sending a starting signal with a first frequency to the first-stage processing chip so that the plurality of processing chips sequentially run at the first frequency, wherein the first frequency is the first of M preset starting frequencies, and M is an integer larger than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second time which is spaced from the first time by a first time length, wherein the first time length corresponds to the first frequency;
at a third time spaced from the time of transmitting the start signal of the mth start frequency by a second time period, transmitting the start signal of the target frequency to the first stage processing chip so that the plurality of processing chips sequentially operate at the target frequency, wherein the second time period corresponds to the mth start frequency,
wherein the M start frequencies are less than the target frequency; the duration corresponding to each starting frequency is longer than the duration required by the plurality of processing chips to run stably in sequence; the M start frequencies increase with the transmission order of the start signals.
8. The method of claim 7, wherein each processing chip comprises N sets of processing units, N being an integer greater than 1,
wherein the method further comprises:
at a fourth moment when the plurality of processing chips are started, a first configuration signal in N preset configuration signals is sent to the first-stage processing chip, so that a first group of processing units in N groups of processing units of each processing chip are started;
according to the corresponding relation between the N configuration signals and the duration, at a fifth moment which is spaced from the fourth moment by a third duration, a next configuration signal is sent to the first-stage processing chip so as to enable a second group of processing units in the N groups of processing units of each processing chip to be started, wherein the third duration corresponds to the first configuration signal;
and at a sixth moment of a fourth time length between the moment of transmitting the N-1 th configuration signal and the moment of transmitting the N-1 th configuration signal, transmitting the N-th configuration signal to the first-stage processing chip so as to enable an N-th group of processing units in N groups of processing units of each processing chip to be started, wherein the fourth time length corresponds to the N-1 th configuration signal.
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