CN111274196A - Start control device and method - Google Patents
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- CN111274196A CN111274196A CN201811481465.8A CN201811481465A CN111274196A CN 111274196 A CN111274196 A CN 111274196A CN 201811481465 A CN201811481465 A CN 201811481465A CN 111274196 A CN111274196 A CN 111274196A
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Abstract
The present disclosure relates to a start control apparatus and method. The device includes: a plurality of processing chips connected in series; a control chip coupled to a first stage of the plurality of processing chips and configured to: at the first moment when the processing chips are started, a starting signal of a first frequency is sent to the first-stage processing chip, so that the processing chips sequentially run at the first frequency; at a second moment separated from the first moment by a first duration, sending a starting signal of the next starting frequency to the first-stage processing chip; and sending the starting signal of the target frequency to the first-stage processing chip at a third moment separated by a second duration from the moment of sending the starting signal of the Mth starting frequency, so that the plurality of processing chips sequentially run at the target frequency. In the starting process, a plurality of starting frequencies are sequentially configured, so that the operating frequencies of a plurality of processing chips are sequentially adjusted upwards, the voltage distribution of each chip is balanced, and the performance of a link is improved.
Description
Technical Field
The present disclosure relates to the field of electronic technologies, and in particular, to a start control device and method.
Background
In the current chip design, a multi-chip cascade method is generally adopted to improve the overall information processing capability. When multiple chips are cascaded, in the period from the start of a link to the stable operation, due to the difference of the frequency, the computational power and the like of the chips, the impedance fluctuation generated by each chip is large, and the voltage distributed to each chip is unstable. If the voltage values of the chips on the whole link are too different, the performance of the whole link is affected, and even a functional error or a chip damage condition can occur.
Disclosure of Invention
In view of this, the present disclosure provides a start control apparatus and method, which can stabilize impedance fluctuation of each chip on a link in a multi-chip cascade link start process, thereby balancing voltage distribution of each chip, improving performance of the entire link, and avoiding a situation of function error or chip damage.
According to an aspect of the present disclosure, there is provided a start-up control apparatus including:
a plurality of processing chips connected in series;
a control chip connected to a first level processing chip of the plurality of processing chips, the control chip configured to:
at a first moment when the processing chips are started, sending a starting signal of a first frequency to the first-stage processing chip so as to enable the processing chips to sequentially run at the first frequency, wherein the first frequency is a first one of M preset starting frequencies, and M is an integer greater than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second moment separated from the first moment by a first time length, wherein the first time length corresponds to the first frequency;
sending a starting signal of a target frequency to the first-stage processing chip at a third time which is separated from the time of sending the starting signal of the Mth starting frequency by a second time length so as to enable the plurality of processing chips to sequentially run at the target frequency, wherein the second time length corresponds to the Mth starting frequency,
wherein the M starting frequencies are less than the target frequency.
In one possible implementation, each processing chip includes N groups of processing units, N being an integer greater than 1,
wherein the control chip is further configured to:
at a fourth moment when the plurality of processing chips are started, sending a first configuration signal in preset N configuration signals to the first-stage processing chip so as to start a first group of processing units in the N groups of processing units of each processing chip;
according to the corresponding relation between the N configuration signals and the time length, at a fifth moment separated from the fourth moment by a third time length, sending a next configuration signal to the first-stage processing chip so as to start a second group of processing units in the N groups of processing units of each processing chip, wherein the third time length corresponds to the first configuration signal;
and sending an Nth configuration signal to the first-stage processing chip at a sixth time spaced by a fourth time length from the time of sending the (N-1) th configuration signal, so as to start an Nth group of processing units in the N groups of processing units of each processing chip, wherein the fourth time length corresponds to the (N-1) th configuration signal.
In one possible implementation, the duration corresponding to each starting frequency is longer than the duration required for the plurality of processing chips to operate stably in sequence.
In one possible implementation, the time duration corresponding to each activation frequency is the same.
In one possible implementation, the M start frequencies increase with the transmission order of the start signals.
In one possible implementation, each group of processing units includes at least one processing unit.
In one possible implementation, the time duration corresponding to each configuration signal is longer than the time duration required for the plurality of processing chips to operate stably in sequence.
In one possible implementation, the time duration corresponding to each configuration signal is the same.
According to another aspect of the present disclosure, there is provided a start-up control method applied to a control chip of a start-up control apparatus, the apparatus further including a plurality of processing chips connected in series, the control chip being connected to a first-stage processing chip of the plurality of processing chips, the method including:
at a first moment when the processing chips are started, sending a starting signal of a first frequency to the first-stage processing chip so as to enable the processing chips to sequentially run at the first frequency, wherein the first frequency is a first one of M preset starting frequencies, and M is an integer greater than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second moment separated from the first moment by a first time length, wherein the first time length corresponds to the first frequency;
sending a starting signal of a target frequency to the first-stage processing chip at a third time which is separated from the time of sending the starting signal of the Mth starting frequency by a second time length so as to enable the plurality of processing chips to sequentially run at the target frequency, wherein the second time length corresponds to the Mth starting frequency,
wherein the M starting frequencies are less than the target frequency.
In one possible implementation, each processing chip includes N groups of processing units, N being an integer greater than 1,
wherein the method further comprises:
at a fourth moment when the plurality of processing chips are started, sending a first configuration signal in preset N configuration signals to the first-stage processing chip so as to start a first group of processing units in the N groups of processing units of each processing chip;
according to the corresponding relation between the N configuration signals and the time length, at a fifth moment separated from the fourth moment by a third time length, sending a next configuration signal to the first-stage processing chip so as to start a second group of processing units in the N groups of processing units of each processing chip, wherein the third time length corresponds to the first configuration signal;
and sending an Nth configuration signal to the first-stage processing chip at a sixth time spaced by a fourth time length from the time of sending the (N-1) th configuration signal, so as to start an Nth group of processing units in the N groups of processing units of each processing chip, wherein the fourth time length corresponds to the (N-1) th configuration signal.
According to the embodiment of the disclosure, in the starting process of the multi-chip cascade link, the control chip sends the starting frequency to the first-stage processing chip in the plurality of processing chips, so that the operating frequency of each processing chip is sequentially adjusted upwards, and the impedance fluctuation of each chip on the link is stabilized in the starting process of the multi-chip cascade link, thereby balancing the voltage distribution of each chip, improving the performance of the whole link, and avoiding the condition of function error or chip damage.
Other features and aspects of the present disclosure will become apparent from the following detailed description of exemplary embodiments, which proceeds with reference to the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate exemplary embodiments, features, and aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure.
FIG. 1 shows a block diagram of an activation control device according to an embodiment of the present disclosure;
FIG. 2 illustrates a schematic diagram of a startup process of a startup control device according to an embodiment of the present disclosure;
FIG. 3 illustrates a schematic diagram of a startup process of a startup control device according to an embodiment of the present disclosure;
FIG. 4 shows a flow chart of a startup control method according to an embodiment of the present disclosure.
Detailed Description
Various exemplary embodiments, features and aspects of the present disclosure will be described in detail below with reference to the accompanying drawings. In the drawings, like reference numbers can indicate functionally identical or similar elements. While the various aspects of the embodiments are presented in drawings, the drawings are not necessarily drawn to scale unless specifically indicated.
The word "exemplary" is used exclusively herein to mean "serving as an example, embodiment, or illustration. Any embodiment described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other embodiments.
Furthermore, in the following detailed description, numerous specific details are set forth in order to provide a better understanding of the present disclosure. It will be understood by those skilled in the art that the present disclosure may be practiced without some of these specific details. In some instances, methods, means, elements and circuits that are well known to those skilled in the art have not been described in detail so as not to obscure the present disclosure.
Fig. 1 shows a block diagram of a start control device according to an embodiment of the present disclosure. As shown in fig. 1, the starting apparatus includes:
a plurality of processing chips 12 connected in series;
a control chip 11 connected to a first-stage processing chip 121 of the plurality of processing chips,
the control chip 11 is configured to:
at a first time when the plurality of processing chips 12 are started, sending a start signal of a first frequency to the first-stage processing chip 121, so that the plurality of processing chips 12 sequentially operate at the first frequency, where the first frequency is a first one of M preset start frequencies, and M is an integer greater than 1;
according to the corresponding relationship between the M start frequencies and the durations, at a second time spaced from the first time by a first duration, sending a start signal of a next start frequency to the first-stage processing chip 121, where the first duration corresponds to the first frequency;
at a third time spaced from the time of sending the start signal of the mth start frequency by a second time length, sending the start signal of the target frequency to the first-stage processing chip 121, so as to sequentially operate the plurality of processing chips 12 at the target frequency, where the second time length corresponds to the mth start frequency,
wherein the M starting frequencies are less than the target frequency.
According to the embodiment of the disclosure, in the starting process of the multi-chip cascade link, the control chip sends M preset starting frequencies and target frequencies to the first-stage processing chip, so that each chip on the link runs at the same frequency, the impedance change of the chips tends to be stable and similar, the distribution of voltage is further balanced, and the performance of the whole link is improved.
For example, M start-up frequencies (M is an integer greater than 1) may be preset to configure the start-up frequency for each processing chip on the link. Wherein M starting frequencies can be expressed as f1、f2、……、fMM starting frequencies f1、f2、……、fMAre all less than the target frequency f of the plurality of processing chips 12 in the link when working normallyT。
In one possible implementation, each start-up frequency may correspond to a duration that is greater than or equal to a duration required for each processing chip on the link to operate smoothly at the corresponding start-up frequency. After receiving the new start frequency, the processing chips 12 adjust the operating frequency to the newly received start frequency and require a certain time for stable operation, and the time duration corresponding to each start frequency is set to be longer than the time duration required for the sequential operation of the processing chips 12, so that each processing chip on the link can operate stably. In this way, the correspondence (e.g., mapping table) between the M start frequencies and the time durations can be established.
Fig. 2 is a schematic diagram of a starting process of a starting control device according to an embodiment of the disclosure. In one possible implementation, as shown in fig. 2, at a first time when the plurality of processing chips 12 are started, the control chip 11 may send a first frequency f to the first stage processing chip 1211A plurality of processing chips 12 sequentially at a first frequency f1And (5) operating. For example, the first frequency f1There may be a minimum frequency 26M configurable by the clock of the control chip 11.
In a possible implementation mannerIn the control chip 11, the first frequency f is transmitted1According to the correspondence between the M start frequencies and the durations, the first frequency f of transmission can be determined1Is started (first time period T)1). Thus, a first time interval T is formed between the first time and the second time1At the second moment, the control chip 11 can send the next starting frequency f to the first stage processing chip 1212So that the plurality of processing chips 12 are sequentially activated at the activation frequency f2And (5) operating. For example, f2The configuration is 100M.
In a possible implementation manner, according to a preset sending sequence of M starting frequencies and a corresponding relationship between the starting frequencies and the durations, the control chip 11 may send a next starting frequency at intervals of the corresponding durations after sending one starting frequency until the M starting frequencies are sent in sequence. During this time, the plurality of processing chips 12 are each operated at the received start-up frequency.
In one possible implementation, the control chip 11 sends the mth start frequency fMAccording to the correspondence between the M starting frequencies and the time lengths, the transmission f can be determined after the starting signal is sentMIs started, is followed by a wait period (second period T)M). Thus, the second time interval T is set between the sending of the starting signal of the Mth starting frequencyMAt the third time, the control chip 11 may send the target frequency f to the first stage processing chip 121TSo that the plurality of processing chips 12 are sequentially at the target frequency fTAnd (5) operating.
It should be understood that the target frequency f of operation is different for the chipsTThe target frequency f may be set according to actual conditionsTThe present disclosure is not so limited.
In one possible implementation, the time duration corresponding to each activation frequency is the same. That is, the duration of the M start-up frequencies can be set to a fixed longer duration (e.g., 0.5 seconds), which can ensure that the processing chips 12 on the link can operate smoothly under various conditions.
In a possible implementation manner, the duration of the M start-up frequencies may also be set to correspond to the time required for data transmission at each start-up frequency, for example, the duration corresponding to each start-up frequency is set to be greater than the number of clock cycles according to the number of clock cycles required for data transmission from the control chip 11 to the last stage processing chip.
In a possible implementation manner, the durations of the M start frequencies may also be set according to feedback signals of the plurality of processing chips running stably, for example, after the control chip 11 sends a start signal of a start frequency to the first-stage processing chip 121, the control chip receives feedback signals of the plurality of processing chips 12 running stably at the start frequency, and the duration corresponding to each start frequency may be set to be greater than the time interval between the start signal and its feedback signal.
The specific value of the corresponding duration of each starting frequency is not limited in the present disclosure.
In one possible implementation, the M start frequencies may increase with the transmission order of the start signals. That is, M starting frequencies f1、f2、f3、……、fMFor example, the values of the M start frequencies may be sequentially configured to be 26M, 100M, and 200M … …, and the operating frequencies of the processing chips 12 may be gradually increased upwards by configuring the start frequencies to increase with the transmission sequence, so as to improve the performance and efficiency of the entire link. It should be understood that, the preset starting frequencies may be different from chip to chip, and the specific setting values of the starting frequencies are not limited by the disclosure.
Fig. 3 shows a schematic diagram of a start-up process of a start-up control device according to an embodiment of the present disclosure. As shown in fig. 3, in one possible implementation, each processing chip includes N groups of processing units, where N is an integer greater than 1, and the control chip 11 is further configured to:
at a fourth time when the plurality of processing chips 12 are started, sending a first configuration signal of preset N configuration signals to the first-stage processing chip 121, so as to start a first group of processing units of the N groups of processing units of each processing chip;
according to the corresponding relationship between the N configuration signals and the time length, at a fifth time spaced from the fourth time by a third time length, sending a next configuration signal to the first-stage processing chip 121, so as to start a second group of processing units in the N groups of processing units of each processing chip, where the third time length corresponds to the first configuration signal;
and at a sixth time spaced by a fourth time length from the time of sending the N-1 th configuration signal, sending the nth configuration signal to the first-stage processing chip 121, so as to start the nth group of processing units in the N groups of processing units of each processing chip, where the fourth time length corresponds to the N-1 th configuration signal.
According to the embodiment of the disclosure, in the starting process of the multi-chip cascade link, the control chip sends N preset configuration signals to the first-stage processing chip, so that N groups of processing units in each chip on the link are started in sequence, the impedance change of the chips tends to be stable and similar, the distribution of voltage is balanced, and the performance of the whole link is improved.
For example, each processing chip includes N groups of processing units (N is an integer greater than 1), and N configuration signals, which may be represented as S, may be preset corresponding to the N groups of processing units1，S2，……SN。
In one possible implementation, each configuration signal may correspond to a time duration that is greater than or equal to a time duration required for each processing chip on the link to start the corresponding processing unit to run smoothly. After receiving the new configuration signal, the processing chips 12 start a new group of processing units and need a certain time for stable operation, and the time duration corresponding to each configuration signal is set to be longer than the time, so that each chip on the link can operate stably. In this way, the correspondence (e.g., mapping table) between the N configuration signals and the time duration can be established.
In a possible implementation manner, at the fourth time when the plurality of processing chips 12 are started, the control chip 11 sends the first configuration of the preset N configuration signals to the first-stage processing chip 121Signal S1The plurality of processing chips 12 are arranged according to the first configuration signal S1The first group of processing units of each processing chip is sequentially started.
In a possible implementation, the control chip 11 sends the first configuration signal S1Then, according to the corresponding relation between the N configuration signals and the time length, the first configuration signal S can be determined to be sent1The subsequent waiting period (third period T)S1). Thus, spaced from the fourth time by a third time period TS1At the fifth moment, the control chip 11 may send the next configuration signal S to the first stage processing chip 1212So that the plurality of processing chips 12 sequentially activate the second group of processing units of the respective processing chips.
In a possible implementation manner, according to a preset sending order of the N configuration signals and a corresponding relationship between the configuration signals and the time lengths, the control chip 11 sends one configuration signal and then sends the next configuration signal at intervals of the corresponding time lengths until the N-1 configuration signals are sent in sequence. During this period, the plurality of processing chips 12 activate the corresponding processing unit group of the N groups of processing units of each processing chip according to the received configuration signal;
in a possible implementation manner, after the control chip 11 sends the nth-1 configuration signal, according to the corresponding relationship between the N configuration signals and the time length, it may be determined to send the nth configuration signal SNPrevious waiting period (fourth period T)SN-1). Thus, the fourth time period T is separated from the time of sending the N-1 configuration signalSN-1At the sixth time, the control chip 11 may send the nth configuration signal S to the first stage processing chip 121NSo that the Nth group of processing units in the N groups of processing units of each processing chip are started.
In one possible implementation, each group of processing units includes at least one processing unit. In the N configuration signals sent by the control chip 11 to the first-stage processing chip 121, each configuration signal corresponds to a group of processing units, and each group of processing units includes at least one processing unit. For example, the first set of processing elements includes one processing element and the second set of processing elements includes one processing element. The number of the processing units included in each group of processing units may be the same or different, and the specific number of the processing units included in each group of processing units is not limited in the present disclosure.
In one possible implementation, the time duration corresponding to each configuration signal is the same. That is, the duration of the N configuration signals may be set to a fixed longer duration (e.g., 0.5 seconds), which may ensure that the plurality of processing chips 12 on the link operate smoothly under various conditions.
In a possible implementation, the time lengths of the N configuration signals may also be set to correspond to the time required for the data transmission of the activated processing unit, for example, the time length corresponding to each configuration signal is set to be greater than the number of clock cycles according to the number of clock cycles required for the data transmission from the control chip 11 to the last stage processing chip.
In a possible implementation manner, the time lengths of the N configuration signals may also be set according to feedback signals of the multiple processing chips that operate stably, for example, after the control chip 11 sends a configuration signal to the first-stage processing chip 121, the control chip receives feedback signals of the multiple processing chips 12 that start the corresponding processing units to operate stably according to the configuration signal, and the time length corresponding to each configuration signal may be set to be greater than the time interval between the configuration signal and the feedback signal thereof.
The present disclosure does not limit the specific value of the corresponding duration of each configuration signal.
In a possible implementation manner, in the multi-chip cascade link starting process, the control chip 11 may send a start frequency to the first-stage processing chip 121 to gradually adjust the operating frequency, or may send a configuration signal to the first-stage processing chip 121 in sequence to start the corresponding processing unit group, where both have no requirement on a predetermined use mode, and may be set according to actual needs, for example, a mode of setting the start frequency first and then setting the configuration signal, a mode of setting the configuration signal first and then setting the start frequency, or a mode of setting the start frequency and setting the configuration signal in combination may be used. The present disclosure does not limit the manner of use of setting the start-up frequency and setting the configuration signal during start-up.
FIG. 4 shows a flow chart of a startup control method according to an embodiment of the present disclosure. As shown in fig. 4, the method is applied to a control chip for starting a control device, the device further comprises a plurality of processing chips connected in series, the control chip is connected to a first-level processing chip in the plurality of processing chips, and the method comprises the following steps:
step S41, at a first time when the plurality of processing chips are started, sending a start signal of a first frequency to the first-stage processing chip, so that the plurality of processing chips sequentially operate at the first frequency, where the first frequency is a first one of M preset start frequencies, and M is an integer greater than 1;
step S42, according to the corresponding relation between M starting frequencies and duration, at a second moment separated from the first moment by a first duration, sending a starting signal of the next starting frequency to the first-stage processing chip, wherein the first duration corresponds to the first frequency;
step S43, at a third time spaced by a second time length from the time of sending the start signal of the mth start frequency, sending the start signal of the target frequency to the first-stage processing chip, so that the plurality of processing chips sequentially operate at the target frequency, where the second time length corresponds to the mth start frequency, and the M start frequencies are smaller than the target frequency.
In one possible implementation, each processing chip includes N groups of processing units, where N is an integer greater than 1, and the method further includes:
at a fourth moment when the plurality of processing chips are started, sending a first configuration signal in preset N configuration signals to the first-stage processing chip so as to start a first group of processing units in the N groups of processing units of each processing chip;
according to the corresponding relation between the N configuration signals and the time length, at a fifth moment separated from the fourth moment by a third time length, sending a next configuration signal to the first-stage processing chip so as to start a second group of processing units in the N groups of processing units of each processing chip, wherein the third time length corresponds to the first configuration signal;
and sending an Nth configuration signal to the first-stage processing chip at a sixth time spaced by a fourth time length from the time of sending the (N-1) th configuration signal, so as to start an Nth group of processing units in the N groups of processing units of each processing chip, wherein the fourth time length corresponds to the (N-1) th configuration signal.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (10)
1. An activation control apparatus, characterized in that the apparatus comprises:
a plurality of processing chips connected in series;
a control chip connected to a first level processing chip of the plurality of processing chips, the control chip configured to:
at a first moment when the processing chips are started, sending a starting signal of a first frequency to the first-stage processing chip so as to enable the processing chips to sequentially run at the first frequency, wherein the first frequency is a first one of M preset starting frequencies, and M is an integer greater than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second moment separated from the first moment by a first time length, wherein the first time length corresponds to the first frequency;
sending a starting signal of a target frequency to the first-stage processing chip at a third time which is separated from the time of sending the starting signal of the Mth starting frequency by a second time length so as to enable the plurality of processing chips to sequentially run at the target frequency, wherein the second time length corresponds to the Mth starting frequency,
wherein the M starting frequencies are less than the target frequency.
2. The apparatus of claim 1, wherein each processing chip comprises N sets of processing units, N being an integer greater than 1,
wherein the control chip is further configured to:
at a fourth moment when the plurality of processing chips are started, sending a first configuration signal in preset N configuration signals to the first-stage processing chip so as to start a first group of processing units in the N groups of processing units of each processing chip;
according to the corresponding relation between the N configuration signals and the time length, at a fifth moment separated from the fourth moment by a third time length, sending a next configuration signal to the first-stage processing chip so as to start a second group of processing units in the N groups of processing units of each processing chip, wherein the third time length corresponds to the first configuration signal;
and sending an Nth configuration signal to the first-stage processing chip at a sixth time spaced by a fourth time length from the time of sending the (N-1) th configuration signal, so as to start an Nth group of processing units in the N groups of processing units of each processing chip, wherein the fourth time length corresponds to the (N-1) th configuration signal.
3. The apparatus of claim 1, wherein a time duration corresponding to each of the plurality of start-up frequencies is greater than a time duration required for the plurality of processing chips to run smoothly in sequence.
4. The apparatus of claim 1, wherein the time duration corresponding to each activation frequency is the same.
5. The apparatus of claim 1, wherein the M activation frequencies increase with an order of transmission of activation signals.
6. The apparatus of claim 2, wherein each group of processing units comprises at least one processing unit.
7. The apparatus of claim 2, wherein a time duration corresponding to each configuration signal is greater than a time duration required for the plurality of processing chips to operate steadily in sequence.
8. The apparatus of claim 2, wherein the time duration corresponding to each configuration signal is the same.
9. A start-up control method is applied to a control chip of a start-up control device, the device further comprises a plurality of processing chips connected in series, the control chip is connected to a first-level processing chip in the plurality of processing chips, and the method comprises the following steps:
at a first moment when the processing chips are started, sending a starting signal of a first frequency to the first-stage processing chip so as to enable the processing chips to sequentially run at the first frequency, wherein the first frequency is a first one of M preset starting frequencies, and M is an integer greater than 1;
according to the corresponding relation between the M starting frequencies and the time length, sending a starting signal of the next starting frequency to the first-stage processing chip at a second moment separated from the first moment by a first time length, wherein the first time length corresponds to the first frequency;
sending a starting signal of a target frequency to the first-stage processing chip at a third time which is separated from the time of sending the starting signal of the Mth starting frequency by a second time length so as to enable the plurality of processing chips to sequentially run at the target frequency, wherein the second time length corresponds to the Mth starting frequency,
wherein the M starting frequencies are less than the target frequency.
10. The method of claim 9, wherein each processing chip includes N sets of processing units, N being an integer greater than 1,
wherein the method further comprises:
at a fourth moment when the plurality of processing chips are started, sending a first configuration signal in preset N configuration signals to the first-stage processing chip so as to start a first group of processing units in the N groups of processing units of each processing chip;
according to the corresponding relation between the N configuration signals and the time length, at a fifth moment separated from the fourth moment by a third time length, sending a next configuration signal to the first-stage processing chip so as to start a second group of processing units in the N groups of processing units of each processing chip, wherein the third time length corresponds to the first configuration signal;
and sending an Nth configuration signal to the first-stage processing chip at a sixth time spaced by a fourth time length from the time of sending the (N-1) th configuration signal, so as to start an Nth group of processing units in the N groups of processing units of each processing chip, wherein the fourth time length corresponds to the (N-1) th configuration signal.
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