CN106919857B - Chip, and starting protection device and method of chip - Google Patents
Chip, and starting protection device and method of chip Download PDFInfo
- Publication number
- CN106919857B CN106919857B CN201511000312.3A CN201511000312A CN106919857B CN 106919857 B CN106919857 B CN 106919857B CN 201511000312 A CN201511000312 A CN 201511000312A CN 106919857 B CN106919857 B CN 106919857B
- Authority
- CN
- China
- Prior art keywords
- check code
- frequency
- storage unit
- chip
- preset
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
Abstract
The invention provides a chip, a chip starting protection device and a chip starting protection method. Wherein the protection device comprises: a storage unit storing a first check code; the adjustable clock generating unit is used for outputting a clock signal with a preset frequency after being electrified and reducing the frequency of the output clock signal according to the received frequency reduction instruction; and the check code comparison unit is connected with the adjustable clock generation unit and the storage unit and is used for comparing the first check code stored in the storage unit with a preset second check code, if the first check code is consistent with the preset second check code, each working hardware in the chip is triggered to start running according to a clock signal of the current frequency, and if the first check code is inconsistent with the preset second check code, the frequency reduction instruction is sent to the adjustable clock generation unit. The invention solves the working method that the chip automatically adapts to the external environment under the condition that the system ensures the highest performance and the high stability of the system.
Description
Technical field
The present invention relates to chip field more particularly to the starting protection device and methods of a kind of chip, chip.
Background technique
With the development of chip high integration, the Sensitive Apparatuses such as processor, memory are included in many integrated chips.These
Sensitive Apparatus has strict requirements to working environment, clock frequency.Therefore, it in design, is usually wrapped in high reliability chip
Containing delay circuit, to ensure the stable clock signal of the circuit containing Sensitive Apparatus.
However, since there are many factor of interference sensitive circuit, the shake of level when such as powering on, the interference of external electromagnetic field,
Temperature and humidity interference etc., excessively high, fixed clock signal are likely to result in chip and are unable to run under interference environment, repeat to open
It moves, mispronounce the problems such as information.
Therefore, it is necessary to improve to the prior art.
Summary of the invention
The present invention provides the starting protection device and method of a kind of chip, chip, for solving frequency mistake in the prior art
The problem of high fixed clock signal is unable to ensure the system stability of chip operation.
Based on above-mentioned purpose, the present invention provides a kind of starting protection device of chip, comprising: has depositing for the first check code
Storage unit；Adjustable clock generating unit, for exporting the clock signal of predeterminated frequency after the power-up, and according to the received frequency reducing of institute
Instruction reduces the frequency of exported clock signal；The check code ratio being connected with the adjustable clock generating unit and storage unit
To unit, for comparing the first check code and preset second check code that the storage unit is saved, if unanimously, triggering
Each working hardware in chip is run according to the clock start signal of current frequency, if inconsistent, Xiang Suoshu adjustable clock occurs
Unit sends the frequency reducing instruction.
Preferably, the adjustable clock generating unit includes: counter circuit and the adjustable clock hair comprising adjustable resistance
Raw circuit；The counter circuit is used for based on the received frequency reducing instruction count frequency reducing frequency of institute, and is based on the frequency reducing frequency
Adjust the adjustable resistance.
Preferably, the adjustable clock occur circuit include: comparator, concatenated resistance R0 and adjustable resistance R1, it is controlled
Hold cascade several switching groups, the ground capacity of corresponding switching group quantity, Shaping Module；
Negative input end connection reference voltage, the positive input terminal of the comparator access between resistance R0 and R1, the comparison
The output end of device is grounded by resistance R0 and R1, while being also connected with the input terminal of each switching group, the signal output of each switching group
End connects corresponding ground capacity.Wherein, the signal output end of the controlled end connection previous stage switching group of rear stage switching group, most
The input terminal of the signal output end connection Shaping Module of rear stage switching group.Meanwhile the controlled end of first order switching group also with it is whole
The input terminal of shape module is connected.
Preferably, the check code comparing unit includes: the address generator being connected with the storage unit, is used for
The address information for storing the first check code in the corresponding storage unit is generated when electric, and is obtained using address information generated
First check code；The check code Comparison Circuit being connected with the address generator and adjustable clock generating unit, being used for will
The first check code from the address generator is compared with preset second check code, if unanimously, output is used for table
Show that correctly instruction if inconsistent records information relevant to clock signal frequency adjusted for verification, and to described adjustable
Clock generation unit sends the frequency reducing instruction；The trigger being connected with the check code Comparison Circuit is received for being based on
For indicating verification correctly instruction, trigger the check code Comparison Circuit and protect the relevant information of presently described clock signal
It is stored in the storage unit, and indicates that each working hardware is run according to the clock start signal of current frequency.
It preferably, include multiple first check codes in the storage unit；Corresponding, the check code comparing unit is also used
In the first check code provided by the address generator is compared with corresponding default second check code, and in all ratios
When relatively result is consistent, output is for indicating verification correctly instruction.
Preferably, the check code comparing unit is also used to repeat the address according to default number of repetition and occur
First check code provided by device and preset second check code, and when all comparison results are consistent, output is used for table
Show verification correctly instruction.
Based on above-mentioned purpose, the present invention also provides a kind of chips, comprising: as above any starting protection device.
Based on above-mentioned purpose, the present invention also provides a kind of starting protection methods of chip, wherein comprising depositing in the chip
There is the storage unit of the first check code, comprising: the clock signal of predeterminated frequency is generated when powering on；Compare the storage unit institute
The first check code and preset second check code saved；If consistent, each working hardware in flip chip is according to current frequency
The clock start signal of rate is run；If inconsistent, the frequency of generated clock signal is reduced, compares two check codes again,
Until comparison result is consistent.
Preferably, the mode for comparing the first check code and preset second check code that the storage unit is saved
It include: the address information that the first check code is stored in the corresponding storage unit to be generated when powering on, and utilize generatedly
First check code described in the acquisition of information of location；It is compared by the first acquired check code, with preset second check code.
Preferably, first check code is multiple；It is corresponding, first check code for comparing storage unit and being saved
And the mode of preset second check code includes: that each first check code and corresponding default second will be stored in the storage unit
Check code is compared, and when all comparison results are consistent, and output is for indicating verification correctly instruction.
Preferably, the mode packet for comparing the first check code and preset second check code that storage unit is saved
It includes: according to default number of repetition, repeating the first check code more stored in the storage unit and preset second check code,
And when all comparison results are consistent, output is for indicating verification correctly instruction.
As described above, the starting protection device and method of chip of the invention, chip, has the advantages that and passes through
It is verified before Sensitive Apparatus starting work in the chips using frequency of the part number circuit to clock signal, and according to testing
Card result is adjusted the frequency of current clock signal, and the present invention is by way of reducing chip operation clock frequency, it is ensured that
The system stability of chip, the CPU for effectively preventing occurring when chip operation mispronounce information, program run-time error, reset repeatedly
Restart equal vicious circles；In addition, clock frequency as high as possible can be provided by the way of gradually frequency reducing for chip, it is ensured that
The working efficiency of chip；In addition, being accidentally proved to be successful in order to prevent, and the clock for being not suitable for working environment is provided for Sensitive Apparatus
Frequency, the present invention is also by the way of multiple authentication, it is ensured that the trouble free service demand of whole system in any condition.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, institute in being described below to the embodiment of the present invention
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the invention
Example, for those of ordinary skill in the art, without creative efforts, can also implement according to the present invention
The content of example and these attached drawings obtain other attached drawings.
Fig. 1 is the structural block diagram of one embodiment of chip of the invention.
Fig. 2 is the structural block diagram of one embodiment that circuit occurs for adjustable clock in starting protection device of the invention.
Fig. 3 is the structural block diagram that one embodiment of comparing unit is verified in starting protection device of the invention.
Fig. 4 is the time diagram after starting protection device of the invention powers on.
Fig. 5 is the flow chart of one embodiment of starting protection method of the invention.
Specific embodiment
To keep the technical problems solved, the adopted technical scheme and the technical effect achieved by the invention clearer, below
It will the technical scheme of the embodiment of the invention will be described in further detail in conjunction with attached drawing, it is clear that described embodiment is only
It is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those skilled in the art exist
Every other embodiment obtained under the premise of creative work is not made, shall fall within the protection scope of the present invention.
As shown in Figure 1, the present invention provides a kind of chip.The chip includes clock-signal generator, and is based on clock
Logical sequence provided by signal comes the digital circuit of work, such as CPU, storage unit, trigger, logical device.
The chip 1 further include: starting protection device 11.When chip 1 powers on, the starting protection device 11 is based on electricity
Source signal is started to work, and under the frequency of current clock signal, carries out check code verifying, and reduce clock according to verification result
The frequency of signal.It is at this time and inactive for the sensitive digital device (such as CPU) in chip, but be verified
Start operation according to clock frequency when being verified afterwards.
The starting protection device 11 includes: the storage unit 111, adjustable clock generating unit 112, check code comparison
Unit 113.
There is the first check code in the storage unit 111.The storage unit 111 includes but is not limited to: flash memory storage
Device, read-only memory, memory device, the disposable programmable memory part of repeatable programming etc..
The adjustable clock generating unit 112 is the improvement to existing clock-signal generator, not only defeated when powering on
The clock signal of predeterminated frequency out, also according to received frequency reducing instruction adjustment clock signal frequency.
Here, the adjustable clock generating unit 112 includes: that circuit occurs for counter circuit and adjustable clock.
The counter circuit is used for based on the received frequency reducing instruction count frequency reducing frequency of institute, and is based on the frequency reducing frequency
The adjustable resistance in the adjustable clock generation circuit is adjusted, so that its output reduces the clock signal after frequency.
The circuit unit that circuit is constructed based on RC circuit theory occurs for the adjustable clock, including: adjustable resistance.
The controlled end of the adjustable resistance is connect with the counter circuit, to adjust itself resistance value.The adjustable resistance is also powering on
When reset to preset resistive value, to allow the adjustable clock that the clock signal that circuit exports predeterminated frequency when powering on occurs.Its
In, the predeterminated frequency is the workable highest frequency of the chip.For example, the adjustable clock generating unit when powering on
The clock signal that 112 output predeterminated frequencies are 50MHz.
The counter circuit gradually adjusts adjustable resistance according to the step-length of preset adjustable resistance resistance value, to reduce frequency
Rate.
For example, be preset in the counter circuit resistance value step-length be a, the every resistance value step-length a of counter circuit,
The adjustable resistance that the adjustable clock occurs in circuit just corresponds to increase/reduction resistance value a.It is designed according to actual circuit, adjustable electric
The change for hindering resistance value will make the frequency of the exported sinusoidal signal of RC circuit by corresponding reduction, by the shaping to sinusoidal signal,
Circuit occurs for the adjustable clock by the clock signal after exporting frequency reducing.
Preferably, with reference to Fig. 2, it includes: comparator, concatenated resistance R0 and adjustable resistance that circuit, which occurs, for the adjustable clock
The cascade several switching groups of R1, controlled end, the ground capacity of corresponding switching group quantity, Shaping Module.
Negative input end connection reference voltage, the positive input terminal of the comparator access between resistance R0 and R1, the comparison
The output end of device is grounded by resistance R0 and R1, while being also connected with the input terminal of each switching group, the signal output of each switching group
End connects corresponding ground capacity.Wherein, the signal output end of the controlled end connection previous stage switching group of rear stage switching group, most
The input terminal of the signal output end connection Shaping Module of rear stage switching group.Meanwhile the controlled end of first order switching group also with it is whole
The input terminal of shape module is connected.
The check code comparing unit 113 is connected with the adjustable clock generating unit 112 and storage unit 111, is used for
The first check code and preset second check code that the storage unit 111 is saved are compared, if unanimously, in flip chip
Each working hardware is run according to the clock start signal of current frequency, if inconsistent, Xiang Suoshu adjustable clock generating unit 112 is sent out
The frequency reducing is sent to instruct.
Specifically, the verification comparing unit includes address generator 1131, check code Comparison Circuit 1132 and trigger
1133.As shown in Figure 3.
The address generator 1131 is connected with the storage unit 111, for generating the corresponding storage when powering on
The address information of the first check code is stored in unit 111, and obtains first check code using address information generated.
Here, the address generator 1131 can previously according to the first check code storage address and be arranged.The address
Generator 1131 generates the address information that the first check code is stored in the corresponding storage unit 111 when powering on, and from described
Storage unit 111 reads the first check code corresponding to address information generated.
The check code Comparison Circuit 1132 is connected with the address generator 1131 and adjustable clock generating unit 112,
For being compared by the first check code from the address generator 1131, with preset second check code, if unanimously,
Output verifies correct instruction for indicating, if inconsistent, records information relevant to clock signal frequency adjusted, and
The frequency reducing instruction is sent to the adjustable clock generating unit 112.
Here, the check code Comparison Circuit 1132 may include multiple logical devices, the first check code is judged to constitute
With the whether consistent decision circuitry of the second check code.
For example, in the check code contrast circuit comprising corresponding everybody comparator of second check code and with each comparator
The connected XOR gate of output end, the reference level of the default corresponding second verification code bit of an input terminal of each comparator, separately
One input terminal receives the corresponding code bit of the first check code.When the check code contrast circuit receives the first check code, press
Level corresponding to each first verification code bit is compared with the reference level of corresponding second verification code bit according to the sequence of code bit
Compared with.When all input terminals of XOR gate are consistent, output is for indicating verification correctly instruction (such as high level)；Conversely,
Export the frequency reducing instruction (such as low level).
The reset terminal of trigger 1133 in the check code comparing unit 113 and the drop of adjustable clock generating unit 112
Frequency command input is connected with the output end of the XOR gate.
For example, the reset terminal high level is effective, frequency reducing command input low level is effective.When the check code compares electricity
Road output is for indicating verification correctly instruction, then the trigger 1133 is based on received useful signal, can described in reading
The frequency reducing frequency counted in clock generation unit 112 is adjusted, and the storage unit 111 is written.At this point, the frequency reducing instruction is defeated
Enter end and receives inactive level.
Opposite, when the frequency reducing command input corresponds to the significant level of frequency reducing instruction, the adjustable clock occurs
Unit 112 executes frequency redution operation and updates the information relevant to clock signal frequency (such as frequency reducing frequency) after frequency reducing.At this point,
The reset terminal of the trigger 1133 receives inactive level.
It in a kind of preferred embodiment, is accidentally proved to be successful in order to prevent, cannot ensure that Sensitive Apparatus can operate in stabilization
Working environment under.The check code comparing unit 113 includes the circuit of program process when being able to carry out following.
For this purpose, including multiple first check codes in the storage unit 111.The check code comparing unit 113 is also used to
First check code provided by the address generator 1131 is compared with corresponding default second check code, and all
When comparison result is consistent, output is for indicating verification correctly instruction.
Specifically, the check code Comparison Circuit 1132 in the check code comparing unit 113 can be according to current clock signal
Temporal order compare one by one；Alternatively, the check code Comparison Circuit 1132 simultaneously by acquired multiple first check codes with
Preset each second check code is corresponding to be compared.When all comparison results are consistent, output is for indicating verification correctly instruction.
In another preferred embodiment, the check code comparing unit 113 is also used to repeat ratio according to default number of repetition
First check code provided by the address generator 1131 and preset second check code, and be in all comparison results
When consistent, output is for indicating verification correctly instruction.
Specifically, the verification Comparison Circuit repeats relatively more described according to temporal order provided by current clock signal
First check code provided by address generator 1131 and preset second check code.When every time than it is more consistent when, be updated successfully
Number, when number of success is consistent with number of repetition, then exporting indicates verification correctly instruction.
Due to the verification Comparison Circuit CPU starting before run, then the verification Comparison Circuit by comprising comparator,
The circuit constituted with hardware devices such as door, XOR gates, to realize the verification process of above-mentioned various modes.
The course of work of above-mentioned starting protection device 11 is exemplified below:
Timing as shown in Figure 4, when powering on, each hardware device in chip resets, wherein adjustable clock generating unit
112 reset and export clock signal T1 according to preset highest frequency, and initializing the frequency reducing frequency is 0, in current clock signal
In the case where T1, the address generator 1131 in check code comparing unit 113 generates the ground of the first check code in storage unit 111
Location information, and obtain the first check code, check code Comparison Circuit 1132 within several clock cycle of current clock signal T1,
Compare the first check code and preset second check code.
If consistent comparison result can be obtained under the frequency of current clock signal T1, can assert in chip as deposited
The Sensitive Apparatuses such as storage unit 111, CPU can be run under the working frequency of current clock signal T1.Based on this, the check code
Comparison Circuit 1132 exports enable signal (i.e. for indicating verification correctly instruction) to coupled trigger 1133, this makes
Can signal the frequency reducing frequency recorded in adjustable clock generating unit 112 is transported into storage unit 111 saved and start CPU etc.
Sensitive Apparatus, Sensitive Apparatus is based on the frequency of current clock signal T1, or directly uses clock signal T1 as work
Clock, or frequency multiplication/frequency dividing is carried out on the basis of the clock signal T1, obtain its work clock.
If consistent comparison result cannot be obtained under the frequency of current clock signal T1, can assert in chip as deposited
The Sensitive Apparatuses such as storage unit 111, CPU can be unable to operate normally under the working frequency of current clock signal T1.Based on this, institute
It states check code Comparison Circuit 1132 and exports frequency reducing instruction, the adjustable clock to coupled adjustable clock generating unit 112
The frequency reducing frequency of the generating unit 112 based on frequency reducing instruction change is 1, and adjusts the adjustable resistance in adjustable clock generation circuit
R1 so that adjustable clock occur circuit output correspond to the frequency reducing frequency for 1, clock signal T2 (frequency > T2 of T1 after frequency reducing
Frequency).Address generator 1131 in the check code comparing unit 113 repeats to give birth under the frequency of new clock signal T2
At address information and the first check code is read, and transfers to check code Comparison Circuit 1132 to be verified, and rejudge in clock
Under frequency provided by signal T2, consistent comparison result can be obtained.It so constantly reduces adjustable clock and circuit output occurs
Clock signal, until be verified.In this way, the starting protection device 11 can ensure that chip is powered on shaking interference, outer
Caused by portion's electromagnetic interference, temperature and humidity interference etc., under the conditions of high-frequency operation, the Sensitive Apparatus in chip can not be normal
The case where work.
As shown in figure 5, the present invention also provides a kind of starting protection methods of chip.Comprising there being the first school in the chip
The storage unit of code is tested, and as above any starting protection device.When chip powers on, the starting protection device fortune
Row, to execute the guard method.
In step sl, the starting protection device generates the clock signal of predeterminated frequency when powering on.
Specifically, the starting protection device generates clock signal according to preset maximum frequency after electrification reset, and
It is exported, to provide timing for other devices in the starting protection device.In addition to this, the starting protection device
The frequency of clock signal generated is adjustable.
In step s 2, the starting protection device compare the first check code that the storage unit is saved with it is preset
Second check code；If consistent, S3 is thened follow the steps, if inconsistent, thens follow the steps S4.
Specifically, the starting protection device generates in the corresponding storage unit when powering on and stores the first check code
Address information, and first check code is obtained using address information generated.
Here, the starting protection device generates the ground for storing the first check code in the corresponding storage unit when powering on
Location information, and the first check code corresponding to address information generated is read from the storage unit.The starting protection dress
Set by the way of hardware circuit whether verify two check codes consistent.
Specifically, the check code Comparison Circuit in the starting protection device may include multiple logical devices, to constitute
Judge the first check code and the whether consistent decision circuitry of the second check code.
For example, in the check code contrast circuit comprising corresponding everybody comparator of second check code and with each comparator
The connected XOR gate of output end, the reference level of the default corresponding second verification code bit of an input terminal of each comparator, separately
One input terminal receives the corresponding code bit of the first check code.When the check code contrast circuit receives the first check code, press
Level corresponding to each first verification code bit is compared with the reference level of corresponding second verification code bit according to the sequence of code bit
Compared with.When all input terminals of XOR gate are consistent, step S3 is executed；Conversely, executing step S4.
The frequency reducing instruction of the reset terminal and adjustable clock generating unit of the trigger that the check code Comparison Circuit is connected
Input terminal is connected with the output end of the XOR gate.
For example, the reset terminal high level is effective, frequency reducing command input low level is effective.When the check code compares electricity
Road output is for indicating verification correctly instruction, then the trigger is based on received useful signal, can timing described in reading
The frequency reducing frequency counted in clock generating unit, and the storage unit is written.At this point, the frequency reducing command input receives nothing
Imitate level.
Opposite, when the frequency reducing command input corresponds to the significant level of frequency reducing instruction, the adjustable clock occurs
Unit executes frequency redution operation.At this point, the reset terminal of the trigger receives inactive level.
It in a kind of preferred embodiment, is accidentally proved to be successful in order to prevent, cannot ensure that Sensitive Apparatus can operate in stabilization
Working environment under.The starting protection device includes the circuit of program process when being able to carry out following.
For this purpose, including multiple first check codes in the storage unit.The starting protection device is by the storage unit
Middle each first check code of storage is compared with corresponding default second check code, and when all comparison results are consistent, is held
Row step S3.
Specifically, the check code Comparison Circuit in the starting protection device can be according to the temporal order of current clock signal
Compare one by one；Alternatively, the check code Comparison Circuit is simultaneously by acquired multiple first check codes and preset each second school
Test the corresponding comparison of code.When all comparison results are consistent, step S3 is executed.
In another preferred embodiment, the starting protection device repeats the storage according to default number of repetition
The first check code and preset second check code stored in unit, and when all comparison results are consistent, execute step
S3。
Specifically, the starting protection device repeats relatively more described according to temporal order provided by current clock signal
First check code provided by address generator and preset second check code.When every time than it is more consistent when, be updated successfully number,
When number of success is consistent with number of repetition, S3 is thened follow the steps.
Due to the starting protection device CPU starting before run, then the starting protection device by comprising comparator,
The circuit constituted with hardware devices such as door, XOR gates, to realize the verification process of above-mentioned various modes.
In step s3, each working hardware in the starting protection device flip chip is believed according to the clock of current frequency
Number starting operation.
Specifically, storage unit, the CPU of the starting protection device into chip etc. export enabling signal, and will with work as
The relevant information (such as frequency reducing frequency) of preceding clock signal frequency is saved in storage unit.
In step s 4, the starting protection device reduces the frequency of generated clock signal, and re-execute the steps
S2, until comparison result is consistent.
Specifically, the adjustable clock generating unit in the starting protection device includes: counter circuit and adjustable clock
Circuit occurs.
The counter circuit is counted the frequency reducing frequency by the control of verification comparison circuit, and is based on the frequency reducing frequency tune
Adjustable resistance in circuit occurs for the whole adjustable clock, so that its output reduces the clock signal after frequency.
The circuit unit that circuit is constructed based on RC circuit theory occurs for the adjustable clock, including: adjustable resistance.
The controlled end of the adjustable resistance is connect with the counter circuit, to adjust itself resistance value.The adjustable resistance is also powering on
When reset to preset resistive value, to allow the adjustable clock that the clock signal that circuit exports predeterminated frequency when powering on occurs.Its
In, the predeterminated frequency is the workable highest frequency of the chip.For example, the adjustable clock generating unit when powering on
Export the clock signal that predeterminated frequency is 50MHz.
The counter circuit gradually adjusts adjustable resistance according to the step-length of preset adjustable resistance resistance value, to reduce frequency
Rate.
For example, be preset in the counter circuit resistance value step-length be a, the every resistance value step-length a of counter circuit,
The adjustable resistance that the adjustable clock occurs in circuit just corresponds to increase/reduction resistance value a.It is designed according to actual circuit, adjustable electric
The change for hindering resistance value will make the frequency of the exported sinusoidal signal of RC circuit by corresponding reduction, by the shaping to sinusoidal signal,
Circuit occurs for the adjustable clock by the clock signal after exporting frequency reducing.
Preferably, with reference to Fig. 2, it includes: comparator, concatenated resistance R0 and adjustable resistance that circuit, which occurs, for the adjustable clock
The cascade several switching groups of R1, controlled end, the ground capacity of corresponding switching group quantity, Shaping Module.
Negative input end connection reference voltage, the positive input terminal of the comparator access between resistance R0 and R1, the comparison
The output end of device is grounded by resistance R0 and R1, while being also connected with the input terminal of each switching group, the signal output of each switching group
End connects corresponding ground capacity.Wherein, the signal output end of the controlled end connection previous stage switching group of rear stage switching group, most
The input terminal of the signal output end connection Shaping Module of rear stage switching group.Meanwhile the controlled end of first order switching group also with it is whole
The input terminal of shape module is connected.
The course of work of above-mentioned starting protection device is exemplified below:
Timing as shown in Figure 4, when powering on, each hardware device in chip resets, wherein adjustable clock generating unit
It resets and exports clock signal T1 according to preset highest frequency, and initializing the frequency reducing frequency is 0, current clock signal T1's
In the case of, check code comparing unit generates the address information of the first check code in storage unit, and current clock signal T1's
In several clock cycle, compare the first check code and preset second check code.
If consistent comparison result can be obtained under the frequency of current clock signal T1, can assert in chip as deposited
The Sensitive Apparatuses such as storage unit, CPU can be run under the working frequency of current clock signal T1.Based on this, the check code ratio
The frequency reducing frequency recorded in adjustable clock generating unit storage unit is transported to unit to be saved and start the sensors such as CPU
Part, Sensitive Apparatus is based on the frequency of current clock signal T1, or directly uses clock signal T1 as work clock, or
Frequency multiplication/frequency dividing is carried out on the basis of the clock signal T1, obtains its work clock.
If consistent comparison result cannot be obtained under the frequency of current clock signal T1, can assert in chip as deposited
The Sensitive Apparatuses such as storage unit, CPU can be unable to operate normally under the working frequency of current clock signal T1.It is described based on this
Check code Comparison Circuit is instructed to coupled adjustable clock generating unit output frequency reducing, the adjustable clock generating unit base
The frequency reducing frequency that change is instructed in the frequency reducing is 1, and adjusts adjustable resistance R1, so that adjustable clock occurs, circuit output is corresponding to drop
Again and again time for 1, clock signal T2 (frequency > T2 frequency of T1) after frequency reducing.The check code comparing unit is when new
Under the frequency of clock signal T2, repeatedly generates address information and read the first check code, and verified, to rejudge in clock
Under frequency provided by signal T2, consistent comparison result can be obtained.It so constantly reduces adjustable clock and circuit output occurs
Clock signal, until be verified.In this way, the starting protection device can ensure that chip is powered on shaking interference, outside
Caused by electromagnetic interference, temperature and humidity interference etc., under the conditions of high-frequency operation, the Sensitive Apparatus in chip can not normal work
The case where making.
In conclusion the starting protection device and method of chip of the invention, chip, passes through Sensitive Apparatus in the chips
It is verified before starting work using frequency of the part number circuit to clock signal, and present clock is believed according to verification result
Number frequency be adjusted, the present invention is by way of reducing chip operation clock frequency, it is ensured that the system stability of chip has
The CPU that effect occurs when chip being prevented to run mispronounces information, program run-time error, resets repeatedly and the vicious circles such as restarts；In addition,
By the way of gradually frequency reducing, clock frequency as high as possible can be provided for chip, it is ensured that the working efficiency of chip；In addition,
It is accidentally proved to be successful in order to prevent, and the clock frequency for being not suitable for working environment is provided for Sensitive Apparatus, the present invention also uses more
The mode of secondary verifying, it is ensured that the trouble free service demand of whole system in any condition.So the present invention effectively overcomes
Various shortcoming in the prior art and have high industrial utilization value.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.It is any ripe
The personage for knowing this technology all without departing from the spirit and scope of the present invention, carries out modifications and changes to above-described embodiment.Cause
This, institute is complete without departing from the spirit and technical ideas disclosed in the present invention by those of ordinary skill in the art such as
At all equivalent modifications or change, should be covered by the claims of the present invention.
Claims (7)
1. a kind of starting protection device of chip characterized by comprising
There is the storage unit of the first check code；
Adjustable clock generating unit refers to for exporting the clock signal of predeterminated frequency after the power-up, and according to the received frequency reducing of institute
Enable the frequency for reducing exported clock signal；
The check code comparing unit being connected with the adjustable clock generating unit and storage unit, for comparing the storage unit
The first check code and preset second check code saved, if unanimously, each working hardware in flip chip is according to current
The clock start signal of frequency is run, if inconsistent, Xiang Suoshu adjustable clock generating unit sends the frequency reducing instruction；
It wherein, include multiple first check codes in the storage unit；Corresponding, the check code comparing unit is also used to ground
First check code provided by the generator of location is compared with corresponding default second check code, and is one in all comparison results
When cause, output is for indicating verification correctly instruction；
Or the check code comparing unit is also used to according to default number of repetition, repetition compares provided by address generator the
One check code and preset second check code, and when all comparison results are consistent, output is for indicating that verification is correct
Instruction.
2. the starting protection device of chip according to claim 1, which is characterized in that the adjustable clock generating unit packet
Include: circuit occurs for counter circuit and the adjustable clock comprising adjustable resistance；
The counter circuit is used for based on the received frequency reducing instruction count frequency reducing frequency of institute, and is adjusted based on the frequency reducing frequency
The adjustable resistance.
3. the starting protection device of chip according to claim 2, which is characterized in that circuit packet occurs for the adjustable clock
Include: comparator, concatenated resistance R0 and the cascade several switching groups of adjustable resistance R1, controlled end correspond to connecing for switching group quantity
Ground capacitor, Shaping Module；
Negative input end connection reference voltage, the positive input terminal of the comparator access between resistance R0 and R1, the comparator
Output end is grounded by resistance R0 and R1, while being also connected with the input terminal of each switching group, and the signal output end of each switching group connects
Connect corresponding ground capacity；Wherein, the signal output end of the controlled end connection previous stage switching group of rear stage switching group, last
The input terminal of the signal output end connection Shaping Module of grade switching group；Meanwhile the controlled end of first order switching group also with sizing die
The input terminal of block is connected.
4. the starting protection device of chip according to claim 1, which is characterized in that the check code comparing unit packet
It includes:
The address generator being connected with the storage unit is stored for being generated in the corresponding storage unit when powering on
The address information of first check code, and first check code is obtained using address information generated；
The check code Comparison Circuit being connected with the address generator and adjustable clock generating unit, for the address will to be come from
First check code of generator is compared with preset second check code, if unanimously, output is for indicating that verification is correct
Instruction records information relevant to clock signal frequency adjusted if inconsistent, and to the adjustable clock generating unit
Send the frequency reducing instruction；
The trigger being connected with the check code Comparison Circuit, for received for indicating verification correctly instruction based on institute,
It triggers the check code Comparison Circuit relevant information of presently described clock signal is saved in the storage unit, and indicates
Each working hardware is run according to the clock start signal of current frequency.
5. a kind of chip characterized by comprising
Starting protection device as described in any in claim 1-4.
6. a kind of starting protection method of chip, wherein special comprising there being the storage unit of the first check code in the chip
Sign is, comprising:
The clock signal of predeterminated frequency is generated when powering on；
Compare the first check code and preset second check code that the storage unit is saved；
If consistent, each working hardware in flip chip is run according to the clock start signal of current frequency；
If inconsistent, the frequency of generated clock signal is reduced, compares two check codes again, until comparison result is consistent
Until；
Wherein, first check code is multiple；It is corresponding, it is described compare the first check code that the storage unit is saved with
The mode of preset second check code includes:
Each first check code will be stored in the storage unit to be compared with corresponding default second check code, and in all ratios
When relatively result is consistent, output is for indicating verification correctly instruction；
Or the mode for comparing the first check code and preset second check code that the storage unit is saved includes:
According to default number of repetition, the first check code more stored in the storage unit and preset second verification are repeated
Code, and when all comparison results are consistent, output is for indicating verification correctly instruction.
7. the starting protection method of chip according to claim 6, which is characterized in that described to compare the storage unit institute
The mode of the first check code and preset second check code saved includes:
The address information for storing the first check code in the corresponding storage unit is generated when powering on, and utilizes address generated
First check code described in acquisition of information；
It is compared by the first acquired check code, with preset second check code.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000312.3A CN106919857B (en) | 2015-12-28 | 2015-12-28 | Chip, and starting protection device and method of chip |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201511000312.3A CN106919857B (en) | 2015-12-28 | 2015-12-28 | Chip, and starting protection device and method of chip |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106919857A CN106919857A (en) | 2017-07-04 |
| CN106919857B true CN106919857B (en) | 2019-11-12 |
Family
ID=59455915
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201511000312.3A Active CN106919857B (en) | 2015-12-28 | 2015-12-28 | Chip, and starting protection device and method of chip |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106919857B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111274196B (en) * | 2018-12-05 | 2023-08-22 | 锐迪科（重庆）微电子科技有限公司 | Start control device and method |
| CN113032791A (en) * | 2021-04-01 | 2021-06-25 | 深圳市纽创信安科技开发有限公司 | IP core, IP core management method and chip |
| CN113065173A (en) * | 2021-04-22 | 2021-07-02 | 西安电掣风云智能科技有限公司 | Encryption method and device for protecting processor embedded algorithm and storage medium |
| CN113176965A (en) * | 2021-04-25 | 2021-07-27 | 山东英信计算机技术有限公司 | Board burning prevention method, system and medium based on VR configuration CRC check |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055486A (en) * | 2010-12-29 | 2011-05-11 | 启东金凤凰科技发展有限公司 | Application of low-density check code in wireless data communication |
| CN102445916A (en) * | 2011-09-15 | 2012-05-09 | 福建星网锐捷网络有限公司 | Method and system of programmable controller and clock frequency control |
| CN103268459A (en) * | 2012-08-01 | 2013-08-28 | 天地融科技股份有限公司 | Electronic device with secure character library, and electronic equipment with electronic device |
-
2015
- 2015-12-28 CN CN201511000312.3A patent/CN106919857B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102055486A (en) * | 2010-12-29 | 2011-05-11 | 启东金凤凰科技发展有限公司 | Application of low-density check code in wireless data communication |
| CN102445916A (en) * | 2011-09-15 | 2012-05-09 | 福建星网锐捷网络有限公司 | Method and system of programmable controller and clock frequency control |
| CN103268459A (en) * | 2012-08-01 | 2013-08-28 | 天地融科技股份有限公司 | Electronic device with secure character library, and electronic equipment with electronic device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN106919857A (en) | 2017-07-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN106919857B (en) | Chip, and starting protection device and method of chip | |
| CN108363640B (en) | Data verification method and device and computer readable storage medium | |
| CN110334007A (en) | A kind of functional interface calls verification method and device, electronic equipment and storage medium | |
| CN104424031A (en) | Working frequency control method and device for processor | |
| CN104134459A (en) | Non-volatile memory (NVM) with variable verify operations | |
| US10001524B2 (en) | Semiconductor integrated circuit and test method thereof | |
| CN112133352A (en) | Programmable peak power management | |
| WO2017112339A1 (en) | Serial i/o functional tester | |
| CN109240130B (en) | Programmable pin level control circuit | |
| CN108021413B (en) | FPGA (field programmable Gate array) online upgrading method and device | |
| CN203338067U (en) | Circuit structure controlled by programming by OTP storage element in embedded system | |
| CN103890713B (en) | Device and method for managing the register information in processing system | |
| US10627841B2 (en) | Reference voltage generation circuit with reduced process variation on the reference voltage | |
| CN103947115B (en) | Frequency locking ring based on oscillator | |
| CN109933479B (en) | Fault simulation and emulation method and related equipment | |
| CN108074601B (en) | Memory device with input circuit and operation method of memory device | |
| CN115425951A (en) | Test mode control circuit of chip | |
| CN208654778U (en) | A kind of OTA upgrading circuit | |
| JP6638732B2 (en) | Control system and control method | |
| CN111093247B (en) | Discrete network access method, system, medium and device suitable for narrow-band Internet of things terminal device | |
| US20120297228A1 (en) | Data recorder for harsh environments | |
| JP6062795B2 (en) | Semiconductor device | |
| CN110232278A (en) | Frequency-reducing time-sharing A2 Trojan horse detection method and device based on composite ring oscillator | |
| CN113238767A (en) | Interface multiplexing method, air conditioner external unit and readable storage medium | |
| CN109844688B (en) | System on chip, electronic device including the same, and driving method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |