CN106886242A - A kind of low-dropout linear voltage-regulating circuit - Google Patents

A kind of low-dropout linear voltage-regulating circuit Download PDF

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Publication number
CN106886242A
CN106886242A CN201710283124.9A CN201710283124A CN106886242A CN 106886242 A CN106886242 A CN 106886242A CN 201710283124 A CN201710283124 A CN 201710283124A CN 106886242 A CN106886242 A CN 106886242A
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CN
China
Prior art keywords
nmos tube
pmos
connects
grid
source
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Application number
CN201710283124.9A
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Chinese (zh)
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CN106886242B (en
Inventor
方健
陈智昕
刘振国
冯磊
王科竣
方舟
胡梦莹
林巨征
张波
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University of Electronic Science and Technology of China
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University of Electronic Science and Technology of China
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Priority to CN201710283124.9A priority Critical patent/CN106886242B/en
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Publication of CN106886242B publication Critical patent/CN106886242B/en
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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices

Abstract

The invention belongs to technical field of integrated circuits, a kind of low-dropout linear voltage-regulating circuit is particularly related to.Relative to common LDO, the feedback loop constituted with the second PMOS MP2, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 7th NMOS tube MN7, the 8th NMOS tube MN8 is employed in the solution of the present invention so that feedback arrangement is simple, easy of integration.

Description

A kind of low-dropout linear voltage-regulating circuit
Technical field
The invention belongs to technical field of integrated circuits, a kind of low-dropout linear voltage-regulating circuit is particularly related to.
Background technology
With the progress and the development of human society of science, energy problem becomes to become increasingly conspicuous.How energy is preferably carried out Source control is increasingly becoming the discussion focus of society.In ic power management domain, LDO (i.e. low pressure difference linear voltage regulator) Because of its conversion efficiency higher, the advantage such as relatively low cost and better simply circuit structure and be widely used.Traditional LDO (as shown in Figure 1) structure includes amplifier structure so that circuit is complex in structure.So, structure is simpler, be more easy to collection Into the concern that gradually causes of LDO circuit.
The content of the invention
It is complex the invention aims to solve the problems, such as existing LDO structures, it is proposed that easily to collect in a kind of piece Into low-dropout linear voltage-regulating circuit.
The technical scheme is that：As shown in Fig. 2 a kind of low-dropout linear voltage-regulating circuit, it is characterised in that described low Pressure difference linear voltage-stabilizing circuit is by the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, One NMOS tube MN1, the second NMOS tube MN2, the 3rd NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS Pipe MN6, the 7th NMOS tube MN7, the 8th NMOS tube MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11 and the first electric capacity C1 is constituted；Wherein,
The source electrode of the first PMOS MP1 connects power supply, and the grid of the first PMOS MP1 is enable control end；
The source electrode of the second PMOS MP2 connects power supply, and its grid connects the drain electrode of the first PMOS MP1；
The source electrode of the 3rd PMOS MP3 connects power supply, and its grid connects the drain electrode of the 4th PMOS MP4, the 3rd PMOS MP3's Drain electrode connects the tie point of the second PMOS MP2 grids and the first PMOS MP1 drain electrodes；
The drain electrode of the 4th PMOS MP4 connects power supply, its grid and drain interconnection；
The drain and gate of the first NMOS tube MN1 connects the first reference voltage source, and the grid of the second NMOS tube MN2 and drain electrode connect The source electrode of the first NMOS tube MN1, the grid of the 3rd NMOS tube MN3 and drain electrode connect the source electrode of the second NMOS tube MN2, the 3rd NMOS tube The source ground of MN3；
The grid of the 4th NMOS tube MN4 and drain electrode connect the drain electrode of the second PMOS MP2, the grid of the 5th NMOS tube MN5 and Drain electrode connects the source electrode of the 4th NMOS tube MN4, and the grid of the 6th NMOS tube MN6 connects the source electrode of the second NMOS tube MN2, the 6th NMOS tube The drain electrode of MN6 connects the source electrode of the 5th NMOS tube MN5, the source ground of the 6th NMOS tube MN6；
The drain electrode of the 7th NMOS tube MN7 connects the drain electrode of the 3rd PMOS MP3, and the grid of the 7th NMOS tube MN7 connects the first base Reference voltage source；
8th NMOS tube MN8's misses the source electrode for meeting the 7th NMOS tube MN7, and the grid of the 8th NMOS tube MN8 connects the second base Reference voltage source, its source electrode connects the source electrode of the 5th NMOS tube MN5；
The drain electrode of the 9th NMOS tube MN9 connects the drain electrode of the 4th PMOS MP4, and the grid of the 9th NMOS tube MN9 connects the first base Reference voltage source；
Tenth NMOS tube MN10's misses the source electrode for meeting the 9th NMOS tube MN9, and the grid of the tenth NMOS tube MN10 connects second Reference voltage source；
11st NMOS tube MN11's misses the source electrode for meeting the tenth NMOS tube MN10, and the grid of the 11st NMOS tube MN11 connects The source electrode of the second NMOS tube MN2, the source ground of the 11st NMOS tube MN11；
One the second PMOS MP2 of termination drain electrodes of the first electric capacity C1, the tie point of the 4th NMOS tube MN4 drain and gates, The 5th NMOS tube MN5 source electrodes of another termination, the 6th NMOS tube MN6 drain electrodes, the tie point of the 8th NMOS tube MN8 source electrodes；
The tie point of the second PMOS MP2 drain electrodes, the 4th NMOS tube MN4 drain and gates and the first electric capacity C1 is low voltage difference Linear voltage-stabilizing circuit output end.
The beneficial effects of the invention are as follows：Employed relative to common LDO, in the solution of the present invention with the second PMOS The negative feedback loop that MP2, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 7th NMOS tube MN7, the 8th NMOS tube MN8 are constituted Road so that feedback arrangement is simple, easy of integration.
Brief description of the drawings
Fig. 1 is tradition LDO schematic diagrames；
Fig. 2 is LDO structural representations of the invention.
Specific embodiment
The present invention is described in detail below in conjunction with the accompanying drawings.
Fig. 2 show LDO structural representations of the invention.
Operation principle of the invention is：
When Enable Pin EN is abnormal (Enable Pin is low level), the first PMOS MP1 is opened so that the second PMOS MP2 is turned off, and exports low level signal.
When Enable Pin EN is normal (Enable Pin be high level), flow through the first NMOS tube MN1, the second NMOS tube MN2 and The electric current I1 of the 3rd NMOS tube MN3, this electric current can be mirrored onto the 6th NMOS tube MN6 and produce electric current I4 and the 11st NMOS tube MN11 produces electric current I2, because the 6th NMOS tube MN6 breadth length ratios are the twices of the 3rd NMOS tube MN3 breadth length ratios, so
Electric current I4 is equal to I1.Because the 11st NMOS tube MN11 breadth length ratios are equal to the 3rd NMOS tube MN3 breadth length ratios, so
Electric current I2 is equal to I1.Electric current I2 is mirrored to the 3rd PMOS MP3 and produces electric current I3 again by the 4th PMOS MP4, Because the ratio between breadth length ratio of the 3rd PMOS MP3 and the 4th PMOS MP4 is 1:1, so
Electric current I3 is equal to I2.Electric current I3 flows through the 7th NMOS tube MN7 and the 8th NMOS tube MN8 again passes through the 6th NMOS tube MN6.So
I4=2I1=2I2=2I3
I4=I5+I3
I1=I2=I3=I5
Because the electric current I5 for flowing through the 4th NMOS tube MN4 and the 5th NMOS tube MN5 is equal to electric current I1 so that output terminal potential Equal to the current potential of benchmark 1.First electric capacity C1 is compensating electric capacity, plays a part of feed-forward capacitance and miller-compensated electric capacity.
If output terminal potential slightly has rising, VDSReduce so that I5 reduces.Due to
I4=I5+I3=2I1
So I3 increases, feedback causes that the grid potential of the second PMOS MP2 reduces, so that increase electric current I5, it is final defeated Go out terminal potential drop to it is equal with the power supply potential of benchmark 1.
If output terminal potential is declined slightly, then VDSIncrease so that I5 increases.Can similarly obtain, I3 reduces, feedback causes the The grid potential increase of two PMOS MP2, so as to reduce electric current I5, final output terminal potential drops to and the power supply potential of benchmark 1 It is equal.
In summary it can be seen, the technological merit of low-dropout linear voltage-regulating circuit proposed by the invention：Relative to traditional LDO, structure of the invention is simpler, easy of integration, it is not necessary to the device such as divider resistance, error amplifier and structure.

Claims (1)

1. a kind of low-dropout linear voltage-regulating circuit, it is characterised in that the low-dropout linear voltage-regulating circuit is by the first PMOS MP1, the second PMOS MP2, the 3rd PMOS MP3, the 4th PMOS MP4, the first NMOS tube MN1, the second NMOS tube MN2, Three NMOS tube MN3, the 4th NMOS tube MN4, the 5th NMOS tube MN5, the 6th NMOS tube MN6, the 7th NMOS tube MN7, the 8th NMOS Pipe MN8, the 9th NMOS tube MN9, the tenth NMOS tube MN10, the 11st NMOS tube MN11 and the first electric capacity C1 are constituted；Wherein,
The source electrode of the first PMOS MP1 connects power supply, and the grid of the first PMOS MP1 is enable control end；
The source electrode of the second PMOS MP2 connects power supply, and its grid connects the drain electrode of the first PMOS MP1；
The source electrode of the 3rd PMOS MP3 connects power supply, and its grid connects the drain electrode of the 4th PMOS MP4, the drain electrode of the 3rd PMOS MP3 Connect the tie point of the second PMOS MP2 grids and the first PMOS MP1 drain electrodes；
The drain electrode of the 4th PMOS MP4 connects power supply, its grid and drain interconnection；
The drain and gate of the first NMOS tube MN1 connects the first reference voltage source, and the grid of the second NMOS tube MN2 and drain electrode connect first The source electrode of NMOS tube MN1, the grid of the 3rd NMOS tube MN3 and drain electrode connect the source electrode of the second NMOS tube MN2, the 3rd NMOS tube MN3 Source ground；
The grid of the 4th NMOS tube MN4 and drain electrode connect the drain electrode of the second PMOS MP2, the grid of the 5th NMOS tube MN5 and drain electrode The source electrode of the 4th NMOS tube MN4 is connect, the grid of the 6th NMOS tube MN6 connects the source electrode of the second NMOS tube MN2, the 6th NMOS tube MN6 Drain electrode connect the source electrode of the 5th NMOS tube MN5, the source ground of the 6th NMOS tube MN6；
The drain electrode of the 7th NMOS tube MN7 connects the drain electrode of the 3rd PMOS MP3, and the grid of the 7th NMOS tube MN7 connects the first benchmark electricity Potential source；
8th NMOS tube MN8's misses the source electrode for meeting the 7th NMOS tube MN7, and the grid of the 8th NMOS tube MN8 connects the second benchmark electricity Potential source, its source electrode connects the source electrode of the 5th NMOS tube MN5；
The drain electrode of the 9th NMOS tube MN9 connects the drain electrode of the 4th PMOS MP4, and the grid of the 9th NMOS tube MN9 connects the first benchmark electricity Potential source；
Tenth NMOS tube MN10's misses the source electrode for meeting the 9th NMOS tube MN9, and the grid of the tenth NMOS tube MN10 connects the second benchmark Voltage source；
11st NMOS tube MN11's misses the source electrode for meeting the tenth NMOS tube MN10, and the grid of the 11st NMOS tube MN11 connects second The source electrode of NMOS tube MN2, the source ground of the 11st NMOS tube MN11；
One the second PMOS MP2 of termination drain electrodes of the first electric capacity C1, the tie point of the 4th NMOS tube MN4 drain and gates, it is another Terminate the 5th NMOS tube MN5 source electrodes, the 6th NMOS tube MN6 drain electrodes, the tie point of the 8th NMOS tube MN8 source electrodes；
The tie point of the second PMOS MP2 drain electrodes, the 4th NMOS tube MN4 drain and gates and the first electric capacity C1 is low pressure difference linearity Circuit output end of pressure-stabilizing.
CN201710283124.9A 2017-04-26 2017-04-26 A kind of low-dropout linear voltage-regulating circuit Expired - Fee Related CN106886242B (en)

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CN201710283124.9A CN106886242B (en) 2017-04-26 2017-04-26 A kind of low-dropout linear voltage-regulating circuit

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010004258A (en) * 2008-06-19 2010-01-07 Toshiba Corp Negative feedback amplifier
CN102906660A (en) * 2010-04-29 2013-01-30 高通股份有限公司 On-chip low voltage capacitor-less low dropout regulator with q-control
CN103412602A (en) * 2013-08-27 2013-11-27 吴小刚 Non-capacitive low-dropout linear voltage regulator
CN103472881A (en) * 2013-09-25 2013-12-25 上海质尊溯源电子科技有限公司 Ultralow-power consumption, high-performance and low-dropout linear voltage regulator
US20140176098A1 (en) * 2012-12-21 2014-06-26 Advanced Micro Devices, Inc. Feed-forward compensation for low-dropout voltage regulator
CN204496328U (en) * 2015-03-10 2015-07-22 遵义师范学院 A kind of transient response being applied to LDO in full sheet improves circuit

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010004258A (en) * 2008-06-19 2010-01-07 Toshiba Corp Negative feedback amplifier
CN102906660A (en) * 2010-04-29 2013-01-30 高通股份有限公司 On-chip low voltage capacitor-less low dropout regulator with q-control
US20140176098A1 (en) * 2012-12-21 2014-06-26 Advanced Micro Devices, Inc. Feed-forward compensation for low-dropout voltage regulator
CN103412602A (en) * 2013-08-27 2013-11-27 吴小刚 Non-capacitive low-dropout linear voltage regulator
CN103472881A (en) * 2013-09-25 2013-12-25 上海质尊溯源电子科技有限公司 Ultralow-power consumption, high-performance and low-dropout linear voltage regulator
CN204496328U (en) * 2015-03-10 2015-07-22 遵义师范学院 A kind of transient response being applied to LDO in full sheet improves circuit

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