CN106876348A - Chip-packaging structure and its manufacture method - Google Patents
Chip-packaging structure and its manufacture method Download PDFInfo
- Publication number
- CN106876348A CN106876348A CN201710130012.XA CN201710130012A CN106876348A CN 106876348 A CN106876348 A CN 106876348A CN 201710130012 A CN201710130012 A CN 201710130012A CN 106876348 A CN106876348 A CN 106876348A
- Authority
- CN
- China
- Prior art keywords
- chip
- fin
- packaging structure
- fixed block
- groove
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/64—Heat extraction or cooling elements
- H01L33/642—Heat extraction or cooling elements characterized by the shape
Abstract
The invention discloses chip-packaging structure, the chip-packaging structure includes：Metal substrate (4) and fin (7), the side of the metal substrate (4) is provided with multiple grooves (5), the fixed block (6) of multiple metal materials being engaged with the groove (5) is provided with the fin (7), the fixed block (6) corresponds and is fixed in the groove (5).The chip-packaging structure overcomes the excessive problem of the thermal resistance that chip encapsulation technology in the prior art is brought.
Description
Technical field
The present invention relates to the invention belongs to technical field of semiconductors, in particular it relates to chip-packaging structure and its manufacturer
Method.
Background technology
In recent years, with the development in an all-round way of semiconductor technology, high power semi-conductor Packaging Industry also constantly weeding out the old and bring forth the new,
Competition.Heat is often one of most critical part of encapsulation technology.In great power LED, the encapsulation of IGBT IGCTs
Device, thermal resistance problem has badly influenced the reliability of device.Therefore, the thermal resistance of high-power chip encapsulation is solved the problems, such as, is
One of bottleneck of encapsulation technology.
Between past 10 years, the current requirements of semiconductor devices are increasing always, at the same time, current switching rate requirement
Also there is sizable raising, this requires that semiconductor devices has alap conducting resistance.With entering for semiconductor technology
Step, encapsulation technology is increasingly becoming the major obstacle of performance boost.The encapsulation of semiconductor devices not only plays protection chip and enhancing
The effect of heat conductivility, but also be the effect for linking up the chip internal world and the bridge and specification general utility functions of external circuit.
The Main Function of encapsulation is for chip provides physical protection and realizes being electrically connected, while realizing semiconductor devices or integrated circuit
Profile standardization, normalization.Because chip must be isolated from the outside, to prevent the impurity in air to the corrosion of chip circuit
Electric property is caused to decline, protection chip surface and connecting lead wire etc. make chip at aspects such as electric or ermal physics from outer
Power infringement and the influence of external environment condition；Make the thermal coefficient of expansion of chip and framework or the thermal coefficient of expansion of substrate by encapsulation simultaneously
Match, can thus alleviate the stress and the generation because chip generates heat produced due to the change of the external environment conditions such as heat
Stress, so as to can prevent wafer damage from failing.
Therefore it provides one kind can effectively improve semiconductor packages radiating efficiency, thermal resistance is low, current capacity is high,
It is urgent need to resolve of the present invention so as to prevent wafer damage failure, the chip-packaging structure of increased thermal conductivity energy and its manufacture method
Problem.
The content of the invention
For above-mentioned technical problem, the purpose of the present invention is the thermal resistance for overcoming chip encapsulation technology in the prior art to be brought
Excessive problem, so that providing one kind can effectively improve semiconductor packages radiating efficiency, thermal resistance is low, current capacity
Height, so as to prevent wafer damage failure, the chip-packaging structure of increased thermal conductivity energy and its manufacture method.
To achieve these goals, the invention provides a kind of chip-packaging structure, the chip-packaging structure includes：Gold
Category substrate and fin, the side of the metal substrate is provided with multiple grooves, be provided with the fin it is multiple with it is described
The fixed block of the metal material of fit depressions, the fixed block is corresponded and is fixed in the groove.
Preferably, the chip-packaging structure includes fin, and multiple fins are arranged on the radiating with being respectively separated
The one side relative with the fixed block on piece.
Preferably, the connected mode between the groove and the fixed block is welding.
Preferably, the outer surface of the fixed block is provided with multiple projections.
Preferably, one side relative with the groove on the metal substrate is respectively arranged with positive pole circuit, negative pole circuit
And LED chip.
Preferably, the chip-packaging structure manufacture is comprised the following steps：Step 1, is set in the binding face of metal substrate
Positive pole circuit and negative pole circuit；Step 2, multiple grooves are machined into the unbundling face of the metal substrate；Step 3,
The one side of fin sets multiple fixed blocks with the fit depressions；Step 4, by LED chip bundled encapsulation in the gold
Belong to the binding region of substrate；Step 5, the groove is inserted and fixed by the fixed block on fin.
Preferably, the chip packaging method also includes：Step 6, it is relative with the fixed block on the fin
Simultaneously interval setting multiple fins.
Preferably, welded together by low-melting-point metal between fixed block and the groove described in the step 5.
According to above-mentioned technical proposal, the chip-packaging structure that the present invention is provided on the metal substrate by setting radiating
Piece sheds to the heat that it is produced, wherein for thus increasing heat radiation effect, the radiating surface of the metal substrate is set into multiple
Groove, so as to increase effective area of dissipation of the metal substrate, is provided with multiple with the recess on the fin
The fixed block of the metal material of conjunction, i.e., when described fixed block is fixed in the groove, the outer surface of the fixed block with it is described
The inwall of groove is bonded to each other.The chip-packaging structure that the present invention is provided overcomes chip encapsulation technology institute band in the prior art
The excessive problem of next thermal resistance.
Other features and advantages of the present invention will be described in detail in subsequent specific embodiment part.
Brief description of the drawings
Accompanying drawing is, for providing a further understanding of the present invention, and to constitute the part of specification, with following tool
Body implementation method is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings：
Fig. 1 is the structural representation of the chip-packaging structure provided under a kind of preferred embodiment of the invention.
Description of reference numerals
The LED chip of 1 positive pole circuit 2
The metal substrate of 3 negative pole circuit 4
The fixed block of 5 groove 6
The fin of 7 fin 8
Specific embodiment
Specific embodiment of the invention is described in detail below in conjunction with accompanying drawing.It should be appreciated that this place is retouched
The specific embodiment stated is merely to illustrate and explain the present invention, and is not intended to limit the invention.
In the present invention, in the case where opposite explanation is not made, " upper and lower, inside and outside " etc. is included in the noun of locality in term
Only represent orientation of the term under normal service condition, or be skilled artisan understands that be commonly called as, and be not construed as it is right
The limitation of the term.
As shown in figure 1, the invention provides a kind of chip-packaging structure, the chip-packaging structure includes：Metal substrate 4
With fin 7, the side of the metal substrate 4 is provided with multiple grooves 5, is provided with the fin 7 multiple recessed with described
The fixed block 6 of the metal material that groove 5 is engaged, the fixed block 6 is corresponded and is fixed in the groove 5.
According to above-mentioned technical proposal, the chip-packaging structure that the present invention is provided is dissipated by being set on the metal substrate 4
Backing 7 sheds to the heat that it is produced, wherein for thus increasing heat radiation effect, the radiating surface of the metal substrate 4 is set
Multiple grooves 5, so as to increase effective area of dissipation of the metal substrate 4, are provided with multiple recessed with described on the fin 7
The fixed block 6 of the metal material that groove 5 is engaged, i.e., when described fixed block 6 is fixed in the groove 5, the fixed block 6 it is outer
Surface is bonded to each other with the inwall of the groove 5.The chip-packaging structure that the present invention is provided overcomes prior art chips
The excessive problem of thermal resistance that encapsulation technology is brought.
In order to further increase the radiating effect of the fin 7 in the present invention, in a kind of preferred implementation of the invention
In mode, the chip-packaging structure include fin 8, multiple fins 8 be arranged on being respectively separated on the fin 7 with
The relative one side of the fixed block 6, the fin 8 can effectively disperse the heat absorbed in the fin 7, so as to protect
Hold the radiating effect of the fin 7.
It is of the invention it is a kind of preferred embodiment in, the connected mode between the groove 5 and the fixed block 6 is
Welding, welding connecting mode not only fixation, and welding material are metal, its thermal conductivity, from without described in influence
Heat transfer between metal substrate 4 and the fin 7, is conducive to the radiating of the metal substrate 4.
It is of the invention it is a kind of preferred embodiment in, the outer surface of the fixed block 6 is provided with multiple projections, described
Projection can increase the frictional force between the fixed block 6 and the groove, can cause that the fixed block 6 is fixed more
It is firm, prevent the fin from coming off.
It is of the invention it is a kind of preferred embodiment in, the one side relative with the groove 5 point on the metal substrate 4
Positive pole circuit 1, negative pole circuit 3 and LED chip 2 are not provided with.
The present invention also provides a kind of making method for chip encapsulation structure, and the chip-packaging structure manufacture includes following step
Suddenly：Step 1, positive pole circuit 1 and negative pole circuit 3 are set in the binding face of metal substrate 4；Step 2, in the metal substrate 4
Unbundling face is machined into multiple grooves 5；Step 3, sets in the one side of fin 7 and multiple is engaged with the groove 5
Fixed block 6；Step 4, by the bundled encapsulation of LED chip 2 the metal substrate 4 binding region；Step 5, by fin 7
Fixed block 6 is inserted and fixed the groove 5.
By being provided with multiple grooves 5 in the chip-packaging structure of above step making in the present invention, the groove 5 is effective
Increase the area of dissipation of the metal substrate 4, the fin 7 typically only uses metal, the fin 7 to be fixed on described
It is that the metal substrate 4 is effectively radiated on metal substrate 4, prevents wafer damage from failing.
It is of the invention it is a kind of preferred embodiment in, the chip packaging method also include step 6, in the radiating
One side interval setting multiple fin 8 relative with the fixed block 6 on piece 7, the fin 8 effectively increases the fin
Heat-sinking capability.
It is of the invention it is a kind of preferred embodiment in, described in the step 5 between fixed block 6 and the groove 5
Welded together by low-melting-point metal, welding connecting mode not only fixation, and welding material is metal, its thermal conductivity
Might as well, from without the heat transfer between the influence metal substrate 4 and the fin 7, be conducive to dissipating for the metal substrate 4
Heat.
The preferred embodiment of the present invention is described in detail above in association with accompanying drawing, but, the present invention is not limited to above-mentioned reality
The detail in mode is applied, in range of the technology design of the invention, various letters can be carried out to technical scheme
Monotropic type, these simple variants belong to protection scope of the present invention.
It is further to note that each particular technique feature described in above-mentioned specific embodiment, in not lance
In the case of shield, can be combined by any suitable means, in order to avoid unnecessary repetition, the present invention to it is various can
The combination of energy is no longer separately illustrated.
Additionally, can also be combined between a variety of implementation methods of the invention, as long as it is without prejudice to originally
The thought of invention, it should equally be considered as content disclosed in this invention.
Claims (8)
1. a kind of chip-packaging structure, it is characterised in that the chip-packaging structure includes：Metal substrate (4) and fin
(7), the side of the metal substrate (4) is provided with multiple grooves (5), is provided with the fin (7) multiple recessed with described
The fixed block (6) of the metal material that groove (5) is engaged, the fixed block (6) corresponds and is fixed in the groove (5).
2. chip-packaging structure according to claim 1, it is characterised in that the chip-packaging structure includes fin (8),
Multiple fins (8) are arranged on one side relative with the fixed block (6) on the fin (7) with being respectively separated.
3. chip-packaging structure according to claim 2, it is characterised in that the groove (5) and the fixed block (6) it
Between connected mode for welding.
4. chip-packaging structure according to claim 3, it is characterised in that the outer surface of the fixed block (6) is provided with
It is multiple raised.
5. chip-packaging structure according to claim 1, it is characterised in that with the groove on the metal substrate (4)
(5) relative one side is respectively arranged with positive pole circuit (1), negative pole circuit (3) and LED chip (2).
6. a kind of making method for chip encapsulation structure, it is characterised in that the chip-packaging structure manufacture is comprised the following steps：
Step 1, positive pole circuit (1) and negative pole circuit (3) are set in the binding face of metal substrate (4)；
Step 2, multiple grooves (5) are machined into the unbundling face of the metal substrate (4)；
Step 3, multiple fixed blocks (6) being engaged with the groove (5) are set in the one side of fin (7)；
Step 4, by LED chip (2) bundled encapsulation the metal substrate (4) binding region；
Step 5, the groove (5) is inserted and fixed by the fixed block (6) on fin (7).
7. making method for chip encapsulation structure according to claim 6, it is characterised in that the chip packaging method is also wrapped
Include：Step 6, relative with the fixed block (6) one side interval setting multiple fin (8) on the fin (7).
8. making method for chip encapsulation structure according to claim 6, it is characterised in that fixed described in the step 5
Welded together by low-melting-point metal between block (6) and the groove (5).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710130012.XA CN106876348A (en) | 2017-03-07 | 2017-03-07 | Chip-packaging structure and its manufacture method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710130012.XA CN106876348A (en) | 2017-03-07 | 2017-03-07 | Chip-packaging structure and its manufacture method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106876348A true CN106876348A (en) | 2017-06-20 |
Family
ID=59169757
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710130012.XA Pending CN106876348A (en) | 2017-03-07 | 2017-03-07 | Chip-packaging structure and its manufacture method |
Country Status (1)
| Country | Link |
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| CN (1) | CN106876348A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107768326A (en) * | 2017-10-12 | 2018-03-06 | 中国科学院微电子研究所 | A kind of silicon carbide power device encapsulating structure |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202288A (en) * | 1990-06-01 | 1993-04-13 | Robert Bosch Gmbh | Method of manufacturing an electronic circuit component incorporating a heat sink |
| US5444909A (en) * | 1993-12-29 | 1995-08-29 | Intel Corporation | Method of making a drop-in heat sink |
| US6081027A (en) * | 1998-05-21 | 2000-06-27 | Micron Technology, Inc. | Integrated heat sink |
| CN102047414A (en) * | 2008-06-12 | 2011-05-04 | 三菱电机株式会社 | Power semiconductor circuit device and method for manufacturing the same |
| CN106170855A (en) * | 2013-12-05 | 2016-11-30 | 三菱电机株式会社 | Power semiconductor device |
-
2017
- 2017-03-07 CN CN201710130012.XA patent/CN106876348A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5202288A (en) * | 1990-06-01 | 1993-04-13 | Robert Bosch Gmbh | Method of manufacturing an electronic circuit component incorporating a heat sink |
| US5444909A (en) * | 1993-12-29 | 1995-08-29 | Intel Corporation | Method of making a drop-in heat sink |
| US6081027A (en) * | 1998-05-21 | 2000-06-27 | Micron Technology, Inc. | Integrated heat sink |
| CN102047414A (en) * | 2008-06-12 | 2011-05-04 | 三菱电机株式会社 | Power semiconductor circuit device and method for manufacturing the same |
| CN106170855A (en) * | 2013-12-05 | 2016-11-30 | 三菱电机株式会社 | Power semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107768326A (en) * | 2017-10-12 | 2018-03-06 | 中国科学院微电子研究所 | A kind of silicon carbide power device encapsulating structure |
| CN107768326B (en) * | 2017-10-12 | 2019-09-27 | 中国科学院微电子研究所 | A kind of silicon carbide power device encapsulating structure |
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| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170620 |
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| RJ01 | Rejection of invention patent application after publication |