CN106874236B - UART protocol same-frame-frequency asynchronous receiving and forwarding system - Google Patents
UART protocol same-frame-frequency asynchronous receiving and forwarding system Download PDFInfo
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Abstract
The invention belongs to the technical field of communication, and discloses a UART protocol same-frame-frequency asynchronous receiving and forwarding system.A data bit and a receiving preparation mark are generated after external asynchronous serial data are transmitted through a UART interface, and are transmitted into a receiving control module to generate RAM1 and RAM2 read-write control signals, clock signals and the like, and the data are selected, stored and finally output through selecting the control signals. The invention can realize the forwarding communication under the condition that the receiving frame rate is the same as the sending frame rate in the asynchronous transmission system, and realize the control of the memory through the ping-pong operation, thereby solving the problem that the data can not be effectively received and stored in the data frame period caused by the consistency of the data frame rate of the receiving system and the asynchronous serial data frame rate, and realizing the 100 percent effective reception of the UART protocol same-frame frequency asynchronous receiving forwarding data through the system.
Description
Technical Field
The invention belongs to the technical field of communication, and particularly relates to a UART protocol same-frame frequency asynchronous receiving and forwarding system.
Background
Asynchronous communication means that two communication parties do not need clock signals to carry out synchronization, but transmit data one bit by one bit according to a well-agreed baud rate, wherein the data comprises a start bit (a start mark for transmitting data), a data bit, a check bit (checking whether data transmission is correct or not) and an end bit (a mark for finishing data transmission). However, when the data frame rate of the receiving system is the same as the asynchronous serial data frame rate, appropriate processing is necessary for accurately and efficiently receiving the data frame data transmitted serially and asynchronously.
In summary, the problems of the prior art are as follows:
because the frame rate of the data to be received and forwarded is the same as that of the data of the sender, the correct receiving and forwarding of the data cannot be guaranteed by directly adopting the existing UART protocol, and therefore the data must be processed.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides a UART protocol same-frame-frequency asynchronous receiving and forwarding system.
The invention is realized in this way, a UART protocol same frame frequency asynchronous receiving and forwarding system, comprising: the UART module, the ping-pong receiving control module Read _ UART _ to _ RAM, the storage control module MUX _ cmd _ RAM12_ signals, the RAM1 module, the RAM2 module, the selection control module generate _ flag _ sel and the 1-out-of-2 module MUX _ cmd _ to _ RS422_ frame;
the UART module is connected with the ping-pong receiving control module Read _ UART _ to _ RAM and is used for outputting 8-bit data bits according to a UART data transmission format and generating a receiving preparation control signal rxrdy after asynchronous serial data Rx passes through the UART interface module;
the ping-pong receiving control module Read _ UART _ to _ RAM is connected with the storage control module MUX _ cmd _ RAM12_ signals, and is used for carrying out frequency reduction processing on the clock frequency of 50Hz, and the two clock frequencies are respectively processed into two clock frequencies of 25Hz, namely Data _ end1 and Data _ end 2; also for generating clocks and addresses for RAM including WRAM _ CLK1, WRAM _ CLK2, and WRAM _ A [5..0 ]; and is also used for merging the received DATA transmitted by the UART module into 16-bit RAM _ DATA [15..0 ];
the storage control module MUX _ cmd _ RAM12_ signals is respectively connected with the RAM1 module and the RAM2 module, and is used for receiving signals WRAM _ CLK1, WRAM _ CLK2, WRAM _ A [15..0], Data _ end1 and Data _ end2 generated by the ping-pong receiving control module Read _ UART _ to _ RAM and an externally input Read RAM address rd _ RAM _ add; after processing, the generated cmd _ clk1 and cmd1_ add [4..0] outputs control the clock and address of the RAM1, and the generated cmd _ clk2 and cmd2_ add [4..0] outputs control the clock and address of the RAM 2;
the RAM1 module is connected with the 1-from-2 module MUX _ cmd _ to _ RS422_ frame, and is used for receiving cmd _ clk1 clock signals and cmd1_ add [4..0] address signals of the MUX _ cmd _ RAM12_ signs, and outputting data cmd _ RAM1_ data [15..0] written into the RAM after processing;
the RAM2 module is connected with the 1-from-2 module MUX _ cmd _ to _ RS422_ frame, and is used for receiving cmd2_ clk2 write clock signals and cmd2_ add [4..0] write address signals of the MUX _ cmd _ RAM12_ signs, and outputting data cmd _ RAM2_ data [15..0] written into the RAM after processing;
the selection control module generate _ flag _ sel is connected with the 1-from-2 module MUX _ cmd _ to _ RS422_ frame, and is used for receiving Data _ end1 and Data _ end2 signals and an external acquisition control input signal adc _ end generated by the storage control module MUX _ cmd _ RAM12_ signs and generating an output selection control signal flag _ sel signal;
the 2-to-1 module MUX _ cmd _ to _ RS422_ frame is connected with the selection control module generate _ flag _ sel, and is used for receiving cmd _ RAM1_ data [15..0] output by the RAM1 module, cmd _ RAM2_ data [15..0] output by the RAM2 module and a flag _ sel signal output by the selection control module flag _ sel and finally outputting an sdata [15..0] signal.
Further, the 8-bit data bits output by the UART module respectively include a start bit, a 5-bit data bit, a check bit, and a stop bit.
Further, the input end of the RAM1 module also receives Data _ end1 generated by the ping-pong receiving control module Read _ UART _ to _ RAM and generated 16 bits of Data RAM _ Data [15..0] to be written into the RAM 1; the RAM2 module input also receives Data _ end2 generated by the ping-pong receive control module Read _ UART _ to _ RAM and the generated 16-bit Data RAM _ Data [15..0] to be written into the RAM 2.
Further, the selection control module generate _ flag _ sel generates a selection signal flag _ sel to selectively output the data of the 1-from-2 module MUX _ cmd _ to _ RS422_ frame; the specific selection is as follows: when flag _ sel is low, the data of the RAM1 is output; flag _ sel is high, the data of RAM2 is output.
Further, the Read/write operation of the RAM1 is performed under the combined action of the enable signal Data _ end1 generated by the ping-pong type reception control module Read _ UART _ to _ RAM, the address cmd1_ add [4..0] generated by the memory control module MUX _ cmd _ RAM12_ signs, and the Data RAM _ Data [15..0] output by the ping-pong type reception control module Read _ UART _ to _ RAM.
Further, the Read/write operation of the RAM2 is performed under the combined action of the enable signal Data _ end2 generated by the ping-pong type reception control module Read _ UART _ to _ RAM, the address cmd2_ add [4..0] generated by the memory control module MUX _ cmd _ RAM12_ signs, and the Data RAM _ Data [15..0] output by the ping-pong type reception control module Read _ UART _ to _ RAM.
Further, the write enable Data _ end1 or Data _ end2 is a low write RAM and a high read RAM; in the addresses cmd1_ add [4..0] or cmd2_ add [4..0] generated by the memory control module MUX _ cmd _ RAM12_ signals, the addresses are written when Data _ end1 is low, and the addresses are read when Data _ end1 is high; the address is written when Data _ end2 is low and read when Data _ end2 is high.
The method for selecting the generation time sequence of the control module generate _ flag _ sel comprises the following steps: marking the 50Hz signal, starting the marking from the 1 st pulse continuously and backwards, generating Data _ end1 by the odd-numbered pulse, and generating Data _ end2 by the even-numbered sequence number when the rising edge Data _ end1 of the next odd-numbered pulse, namely the 3 rd pulse, becomes low again; data _ end1 and Data _ end2 are used as enabling signals of the RAM1 and the RAM2 to control the read-write operation of the RAM; then Data _ end1 and Data _ end2 are anded; and then, acquiring a sel signal by using the rising edge of the adc _ end to obtain the flag _ sel.
Another objective of the present invention is to provide a method for selecting a generation timing of a control module generate _ flag _ sel, the method comprising: marking 50Hz signal, starting from the 1 st pulse to the back, the odd-numbered pulse is used to generate Data _ end1, and the Data _ end1 becomes low again at the rising edge of the next odd-numbered pulse, namely the 3 rd pulse, and the even-numbered sequence number generates Data _ end 2; the Data _ end1 and the Data _ end2 are used as write enable signals of the RAM1 and the RAM2 to control the read-write operation of the RAM; then Data _ end1 and Data _ end2 are anded; and then, acquiring a sel signal by using the rising edge of the adc _ end to obtain the flag _ sel.
The invention has the advantages and positive effects that:
the invention can realize the forwarding communication under the condition that the receiving frame rate is the same as the sending frame rate in the asynchronous transmission system, and realize the control of the memory through the ping-pong operation, thereby solving the problem that the data can not be effectively received and stored in the data frame period caused by the consistency of the frame rate of the receiving end and the frame rate of the asynchronous serial data; the system can realize 100% effective receiving of the UART protocol synchronous and asynchronous receiving and forwarding data.
Drawings
Fig. 1 is a schematic diagram of a UART protocol synchronous frame rate asynchronous receiving and forwarding system according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a ping-pong receiving control module Read _ UART _ to _ RAM according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a memory control module MUX _ cmd _ RAM12_ signals according to an embodiment of the invention;
FIG. 4 is a block diagram of a RAM1 according to an embodiment of the present invention;
FIG. 5 is a block diagram of a RAM2 according to an embodiment of the present invention;
FIG. 6 is a diagram of a selection control module flag _ sel according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a 1-out-of-2 module provided in an embodiment of the present invention;
fig. 8 is a timing diagram of the generation of the selection control module flag _ sel according to the embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The following detailed description of the principles of the invention is provided in connection with the accompanying drawings.
As shown in fig. 1, in the UART protocol and frame rate asynchronous receiving and forwarding system according to the embodiment of the present invention, after the asynchronous serial data Rx passes through the UART interface, 8-bit data bits are output according to the UART data transmission format and a receiving preparation control signal rxrdy is generated. In the present system, these 8 bits include a start bit, a data bit (5 bits), a check bit, and a stop bit, respectively. Then, in the Read _ UART _ to _ RAM module, the 50Hz clock frequency is down-converted into two 25Hz clock frequencies, Data _ end1 and Data _ end2 as shown in the figure, respectively, and the clock and address for writing to the RAM, WRAM _ CLK1, WRAM _ CLK2 and WRAM _ a [5..0] as shown in fig. 2, are generated in the module, and the received Data is combined into 16 bits, RAM _ Data [15..0] as shown in fig. 2.
Then, the clock and address of the control RAM1 and the RAM2 are respectively output from the memory control module MUX _ cmd _ RAM12_ signs, i.e., fig. 3, that is, in the RAM1, as shown in fig. 4, the cmd _ clk1, cmd1_ add [4..0] generated from the memory control module MUX _ cmd _ RAM12_ signs and the Data _ end1 and RAM _ Data [15..0] generated from fig. 2 are respectively the clock, address, enable and Data to be written into the RAM1 of the RAM1, and finally the Data cmd _ RAM1_ Data [15..0] written into the RAM is output. Similarly, the same applies to the RAM2 as shown in FIG. 5, and the cmd _ RAM2_ data [15..0] is finally output.
And then, generating a selection signal flag _ sel by using a selection control module generate _ flag _ sel, and selectively outputting the data of the MUX _ cmd _ to _ RS422_ frame of the 1-from-2 module by using the selection signal flag _ sel.
The application of the principles of the present invention will now be described in further detail with reference to specific embodiments.
In the UART protocol and frame frequency asynchronous receiving and forwarding system provided by the embodiment of the invention, an asynchronous serial Data frame outputs 8-bit Data bits according to the Data transmission format of the UART communication protocol after passing through a UART interface and generates a receiving preparation signal rxrdy, then the asynchronous serial Data frame passes through a Read _ UART _ to _ RAM module to generate clocks WRAM _ CLK1, WRAM _ CLK2 and an address WRAM _ A [15..0] for controlling the RAM1 and the RAM2, and Data _ DATA [15..0] for enabling Data _ end1, Data _ end2 and Data RAM _ DATA [15..0] written into the RAM1 and the RAM 2.
The signals WRAM _ CLK1, WRAM _ CLK2, WRAM _ A [15..0], Data _ end1, Data _ end2 generated in FIG. 2, in addition to the externally input read RAM address rd _ RAM _ add, pass through MUX _ cmd _ RAM12_ signs module and output the clock and address respectively controlling RAM1 and RAM 2.
Read and write operations of the RAM1 are performed by the enable signal Data _ end1 (write RAM at low and read RAM at high) generated in fig. 2, the address cmd1_ add [4..0] (whether the read address or the write address depends on the high or low of the Data _ end 1) generated in fig. 3, and the RAM _ DA TA [15..0 ].
Read and write operations of the RAM2 are performed by the enable signal Data _ end2 (write RAM at low and read RAM at high) generated in fig. 2, the address cmd2_ add [4..0] (whether the read address or the write address depends on the high or low of the Data _ end 2) generated in fig. 3, and the RAM _ DA TA [15..0 ].
In fig. 6, the Data _ end1, Data _ end2, and acquisition control signal adc _ end of the system are used as input signals, and an output selection control signal flag _ sel is generated (see fig. 8 for details of generation).
The selection control signal flag _ sel generated in fig. 6 is used as the selection signal for the 1-out-of-2 module MUX _ cmd _ to _ RS422_ frame of fig. 7. When flag _ sel is low, the data of the RAM1 is output; flag _ sel is high, the data of RAM2 is output.
As shown in fig. 8, the method of flag _ sel generation timing: the 50Hz signal is labeled beginning after the 1 st pulse, the odd numbered pulses are used to generate Data _ end1, and Data _ end1 goes low again at the rising edge of the next odd numbered pulse, i.e., the 3 rd pulse, and the even numbered pulses generate Data _ end2, as is the principle. Since one cycle is 20ms, it takes about 12.2ms to receive asynchronous serial Data through calculation, namely UART reception shown in the figure, that is, only less than 8ms is left to store Data, and there is a possibility that the Data is not completely stored in RAM when the next cycle arrives, therefore, the 50Hz signal is subjected to frequency division processing and is respectively divided into two 25Hz signals Data _ end1 and Data _ end2, so that the time for writing RAM becomes less than 28ms, and all Data can be written into RAM before the next clock cycle arrives certainly. The read and write operations of the RAM are controlled using Data _ end1 and Data _ end2 as write enables for RAM1 and RAM 2. Data _ end1 and Data _ end2 are then ANDed, the result is the sel signal shown in FIG. 8, and then the sel signal is collected by using the rising edge of adc _ end, so that flag _ sel is obtained.
In the invention, the asynchronous serial frame rate is f, each frame comprises 64 bytes, and the adc _ end acquisition control signal rate is f. In this system, f is 50Hz and the asynchronous serial data bit rate is 57600 bps.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A UART protocol frame-rate asynchronous receiving and forwarding system, comprising: the UART module, the ping-pong receiving control module Read _ UART _ to _ RAM, the storage control module MUX _ cmd _ RAM12_ signals, the RAM1 module, the RAM2 module, the selection control module generate _ flag _ sel and the 1-out-of-2 module MUX _ cmd _ to _ RS422_ frame;
the UART module is connected with the ping-pong receiving control module Read _ UART _ to _ RAM and is used for outputting 8-bit data bits according to a UART data transmission format and generating a receiving preparation control signal rxrdy after asynchronous serial data Rx passes through the UART interface module;
the ping-pong receiving control module Read _ UART _ to _ RAM is connected with the storage control module MUX _ cmd _ RAM12_ signals, and is used for carrying out frequency reduction processing on the clock frequency of 50Hz, and the two clock frequencies are respectively processed into two clock frequencies of 25Hz, namely Data _ end1 and Data _ end 2; also for generating clocks and addresses for RAM including WRAM _ CLK1, WRAM _ CLK2, and WRAM _ A [5..0 ]; and is also used for merging the received DATA transmitted by the UART module into 16-bit RAM _ DATA [15..0 ];
the storage control module MUX _ cmd _ RAM12_ signals is respectively connected with the RAM1 module and the RAM2 module, and is used for receiving signals WRAM _ CLK1, WRAM _ CLK2, WRAM _ A [15..0], Data _ end1 and Data _ end2 generated by the ping-pong receiving control module Read _ UART _ to _ RAM and an externally input Read RAM address rd _ RAM _ add; after processing, the generated cmd _ clk1 and cmd1_ add [4..0] outputs control the clock and address of the RAM1, and the generated cmd _ clk2 and cmd2_ add [4..0] outputs control the clock and address of the RAM 2;
the RAM1 module is connected with the 1-from-2 module MUX _ cmd _ to _ RS422_ frame, and is used for receiving cmd _ clk1 clock signals and cmd1_ add [4..0] address signals of the MUX _ cmd _ RAM12_ signs, and outputting data cmd _ RAM1_ data [15..0] written into the RAM after processing;
the RAM2 module is connected with the 1-from-2 module MUX _ cmd _ to _ RS422_ frame, and is used for receiving cmd2_ clk2 write clock signals and cmd2_ add [4..0] write address signals of the MUX _ cmd _ RAM12_ signs, and outputting data cmd _ RAM2_ data [15..0] written into the RAM after processing;
the selection control module generate _ flag _ sel is connected with the 1-from-2 module MUX _ cmd _ to _ RS422_ frame, and is used for receiving Data _ end1 and Data _ end2 signals and an external acquisition control input signal adc _ end generated by the storage control module MUX _ cmd _ RAM12_ signs and generating an output selection control signal flag _ sel signal;
the 2-to-1 module MUX _ cmd _ to _ RS422_ frame is connected with the selection control module generate _ flag _ sel, and is used for receiving cmd _ RAM1_ data [15..0] output by the RAM1 module, cmd _ RAM2_ data [15..0] output by the RAM2 module and a flag _ sel signal output by the selection control module flag _ sel and finally outputting an sdata [15..0] signal.
2. The UART protocol asynchronous receiver-transmitter system with frame rate as claimed in claim 1, wherein the 8-bit data bits outputted from the UART module respectively include a start bit, a 5-bit data bit, a check bit and a stop bit.
3. The UART protocol asynchronous receiving and forwarding system with same frame rate as claimed in claim 1, wherein the input terminal of the RAM1 module also receives Data _ end1 generated by the ping-pong receiving control module Read _ UART _ to _ RAM and the generated 16 bits of Data RAM _ DATA [15..0] to be written into the RAM 1; the RAM2 module input also receives Data _ end2 generated by the ping-pong receive control module Read _ UART _ to _ RAM and the generated 16-bit Data RAM _ Data [15..0] to be written into the RAM 2.
4. The UART protocol asynchronous receiving and forwarding system with the same frame rate as in claim 1, wherein the selection control module generate _ flag _ sel generates a selection signal flag _ sel to selectively output the data of the 1-out-of-2 module MUX _ cmd _ to _ RS422_ frame; the specific selection is as follows: when flag _ sel is low, the data of the RAM1 is output; flag _ sel is high, the data of RAM2 is output.
5. The UART protocol asynchronous with frame rate receiving and forwarding system according to claim 1,
the Read-write operation of the RAM1 is performed under the combined action of an enable signal Data _ end1 generated by the ping-pong receiving control module Read _ UART _ to _ RAM, an address cmd1_ add [4..0] generated by the memory control module MUX _ cmd _ RAM12_ signs and a Data RAM _ DATA [15..0] output by the ping-pong receiving control module Read _ UART _ to _ RAM.
6. The UART protocol asynchronous with frame rate receiving and forwarding system according to claim 1,
the Read-write operation of the RAM2 is performed under the combined action of an enable signal Data _ end2 generated by the ping-pong receiving control module Read _ UART _ to _ RAM, an address cmd2_ add [4..0] generated by the memory control module MUX _ cmd _ RAM12_ signs and a Data RAM _ DATA [15..0] output by the ping-pong receiving control module Read _ UART _ to _ RAM.
7. The UART protocol co-frame rate asynchronous receiving and forwarding system as claimed in any of claims 5-6, wherein the write enable Data _ end1 or Data _ end2 is a low-time write RAM and a high-time read RAM; in the addresses cmd1_ add [4..0] or cmd2_ add [4..0] generated by the memory control module MUX _ cmd _ RAM12_ signals, the addresses are written when Data _ end1 is low, and the addresses are read when Data _ end1 is high; the address is written when Data _ end2 is low and read when Data _ end2 is high.
8. The UART protocol asynchronous receiving and forwarding system with same frame rate as in claim 1, wherein the method for selecting the generation timing of the control module generate _ flag _ sel is as follows: marking the 50Hz signal, starting the marking from the 1 st pulse continuously and backwards, generating Data _ end1 by the odd-numbered pulse, and generating Data _ end2 by the even-numbered sequence number when the rising edge Data _ end1 of the next odd-numbered pulse, namely the 3 rd pulse, becomes low again; data _ end1 and Data _ end2 are used as enabling signals of the RAM1 and the RAM2 to control the read-write operation of the RAM; then Data _ end1 and Data _ end2 are anded; and then, acquiring a sel signal by using the rising edge of the adc _ end to obtain the flag _ sel.
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| US5390019A (en) * | 1992-07-17 | 1995-02-14 | Honeywell Inc. | Laser gyro built in test method and apparatus |
| KR100736405B1 (en) * | 2005-09-28 | 2007-07-09 | 삼성전자주식회사 | Semiconductor for performing direct memory access without FIFO and method for processing data thereof |
| CN203376909U (en) * | 2013-01-05 | 2014-01-01 | 北京工业大学 | Novel microcomputer principle and interface experiment system based on FPGA |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5390019A (en) * | 1992-07-17 | 1995-02-14 | Honeywell Inc. | Laser gyro built in test method and apparatus |
| KR100736405B1 (en) * | 2005-09-28 | 2007-07-09 | 삼성전자주식회사 | Semiconductor for performing direct memory access without FIFO and method for processing data thereof |
| CN203376909U (en) * | 2013-01-05 | 2014-01-01 | 北京工业大学 | Novel microcomputer principle and interface experiment system based on FPGA |
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