CN106865489A - The manufacture method of MEMS - Google Patents
The manufacture method of MEMS Download PDFInfo
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- CN106865489A CN106865489A CN201710079146.3A CN201710079146A CN106865489A CN 106865489 A CN106865489 A CN 106865489A CN 201710079146 A CN201710079146 A CN 201710079146A CN 106865489 A CN106865489 A CN 106865489A
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
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Abstract
The invention discloses a kind of manufacture method of MEMS, including step：Semiconductor substrate is provided, it includes cavity, the cavity is a part for MEMS, and the top of cavity has the capping layer for being arranged with through hole；Deposited oxide layer is closed to the through hole on capping layer on the capping layer；Before through hole closing is completely enclosed, to being ashed to the cavity by the through hole；Continue deposited oxide layer until the through hole is completely enclosed, by increasing ashing of the step to cavity during being sealed to the capping layer, so as to effectively eliminate the floccule defect produced in oxide deposition process, so as to improve the accuracy of device.
Description
Technical field
The present invention relates to technical field of semiconductors, more particularly to a kind of manufacture method of MEMS.
Background technology
MEMS (Micro-Electro-Mechanical Systems, MEMS) is a kind of integrability production,
Integrate the microdevice or system of micro mechanism, microsensor, micro actuator and signal transacting and control circuit.
It is as the development of semiconductor integrated circuit Micrometer-Nanometer Processing Technology and ultraprecise mechanical manufacturing technology gets up.Using
The microelectronic component of MEMS technology is in Aeronautics and Astronautics, environmental monitoring, biomedicine and all necks that almost people are touched
There is very wide application prospect in domain.
The manufacture method of existing MEMS usually forms patterned layer and sacrifice layer, Ran Hou on a semiconductor substrate
Dielectric layer being formed thereon, the micro mechanical structure of the suspension of MEMS being made of the dielectric layer, sacrifice layer is removed, then will
MEMS is sealed.
The schematic flow sheet of a kind of existing MEMS preparation method as shown in Figure 1, basic step includes：Step
S101, offer Semiconductor substrate, the Semiconductor substrate is the base semiconductor structure of MEMS.Step S102, described
The surface of Semiconductor substrate forms the first sacrifice layer, and the material of first sacrifice layer is amorphous carbon, according in MEMS
The bulk of pressure cavity, selects the thickness of first sacrifice layer.Step S103, etch first sacrifice layer and form the
One groove.Step S104, first sacrificial layer surface cover to be formed first medium layer.Step S105, image conversion are simultaneously etched
First medium layer, step S106, on first medium layer outputs through hole, step S107, the first sacrifice layer of removal, and will pressure
Power cavities seals.
But there is cotton-shaped defect in the closed cavity in existing MEMS preparation method.
The content of the invention
It is an object of the present invention to provide a kind of manufacture method of MEMS, cotton-shaped scarce in above-mentioned cavity to avoid
Fall into.
In order to solve the above technical problems, the present invention provides a kind of manufacture method of MEMS, including step：
Semiconductor substrate is provided, it includes cavity, and the cavity is a part for MEMS, and the top of cavity has
It is arranged with the capping layer of through hole；
Deposited oxide layer is closed to the through hole on capping layer on the capping layer；
Before through hole closing is completely enclosed, to being ashed to the cavity by the through hole；
Continue deposited oxide layer until the through hole is completely enclosed.
Preferably, it is the circular hole of 0.35 μm of diameter to form the capping layer as described before through hole.
Preferably, the material of the oxide skin(coating) is silica.
Preferably, it is in oxide layer thicknessesWhen the cavity is ashed.
Preferably, the ashing is to utilize fluorine base gas.
Preferably, the gross thickness of the oxide skin(coating) is
Preferably, the fluorine base gas is HF, CF4、C4F8、CHF3In one or more.
Preferably, the fluorine base gas in the cineration technics is fluoro plasma.
Preferably, the technological temperature of the cineration technics is less than 200 DEG C.
Compared with prior art, the manufacture method of the MEMS that the present invention is provided, is carried out by the capping layer
Increase ashing of the step to cavity during sealing, thus effectively eliminate in oxide deposition process produce it is cotton-shaped
Thing defect, so as to improve the accuracy of device.
Brief description of the drawings
Fig. 1 is the structural representation of MEMS in the prior art；
Fig. 2 is the manufacture method flow chart of MEMS in one embodiment of the invention；
Fig. 3~Fig. 5 is the structural representation of the manufacture method of MEMS in one embodiment of the invention.
Specific embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings to the present invention
Specific embodiment be described in detail.
Elaborate detail in order to fully understand the present invention in the following description.But the present invention can with it is various not
It is same as other manner described here to implement, those skilled in the art can do class in the case of without prejudice to intension of the present invention
Like popularization.Therefore the present invention is not limited by following public specific embodiment.
Fig. 2 is the manufacture method flow chart of MEMS of the invention；Fig. 3 to Fig. 5 is one embodiment of the invention
The structural representation of the manufacture method of MEMS.The manufacture method of MEMS of the invention is entered with reference to Fig. 2 to Fig. 5
Row is described in detail.
As shown in Fig. 2 the manufacture method of MEMS of the invention includes step：
S10：The first semiconductor substrate is provided, it includes cavity, the cavity is a part for MEMS, the top of cavity
Portion has the capping layer for being arranged with through hole；
S11：Deposited oxide layer is closed to the through hole on capping layer on the capping layer；
S12：Before through hole closing is completely enclosed, to being ashed to the cavity by the through hole；
S13：Continue deposited oxide layer until the through hole is completely enclosed.
Step S10 is first carried out, as shown in figure 3, first semiconductor substrate 30 includes monocrystalline silicon in the present embodiment
Wafer 30a, forms silica epitaxial layer 31 on the wafer 30a, the first medium layer on oxidation silicon epitaxy layer 31
32, the second dielectric layer 33 on first medium layer 32, the first medium layer 32, second dielectric layer 33 is in the silica
A groove is surrounded on epitaxial layer 31, in second dielectric layer 33 and cover the groove with through hole 34a capping layers 34,
Oxidation silicon epitaxy layer 31, the first medium layer 32, second dielectric layer 33 and capping layer 34 surround a cavity 35, in the sky
Chamber 35 is a part for MEMS.
In the present embodiment, MOS circuits (not shown) are formed with silicon epitaxy layer 31 is aoxidized, for example drive circuit or
Control circuit.Metal interconnecting layer (not shown) and bottom electrode plate (not shown) are also formed with silicon epitaxy layer 31 is aoxidized.Institute
Metal interconnecting layer is stated for being electrically connected with the micro mechanical structure of MEMS described in the present embodiment；The bottom electrode plate is used as driving
Layer, positioned at the surface region of the first semiconductor substrate 30.
In the present embodiment, first semiconductor substrate can be formed using following methods：
Patterned layer and the sacrifice layer being embedded in patterned layer are formed on semiconductor crystal wafer with oxidation silicon epitaxy layer 31.Specifically
, as shown in figure 3, sacrifice layer (being located in the cavity 35, not shown) is formed on oxidation silicon epitaxy layer 31 surface, it is described
Sacrifice layer is used for the lower space of the first semiconductor substrate for forming suspension, cantilever of its thickness not less than the micro mechanical structure for suspending
Reclinate stroke.In the present embodiment, the material of the sacrifice layer is amorphous carbon, is formed using chemical vapor deposition.So
Afterwards, the sacrifice layer is etched, groove is formed.The etching can be plasma etching, and although amorphous carbon be difficult to and other things
Matter produces chemical reaction, but because property is loose, therefore be easier to dry with physical bombardment effect by plasma etching etc.
Method etching technics is removed.Specifically, photoresist mask is formed in sacrificial layer surface using photoetching process, it is recessed needed for being formed
Groove.The bottom portion of groove exposes oxidation silicon epitaxy layer 31, and alignment metal interconnecting layer, in order to make mutual with metal in groove
The contact hole that even layer is connected.Sacrifice layer is divided into independent square region by the groove, and in the square region, sacrifice
Bottom electrode plate described in the bottom alignment of layer.
Then, as shown in figure 3, forming first medium layer 32 on the surface of above-mentioned oxidation silicon epitaxy layer 31 and sacrifice layer,
The first medium layer 32 is filled in groove, is also covered in the first sacrificial layer surface.The material of the first medium layer 32 can
Think the conventional semiconductor medium material such as silica or silicon nitride, formed using chemical vapor deposition method.Then, using change
Mechanical lapping is learned, the thinning first medium layer 32 is until expose the surface of sacrifice layer.When the first medium layer of sacrificial layer surface
After 32 have been ground, first medium layer 32 only retains the part in former groove, and the top surface of first medium layer 32 with
Sacrifice layer flush.The first medium layer 32 is patterned layer, and material can be the silicon compounds such as silica.
Then, the film layer for making the micro mechanical structure for suspending is formed on first sacrifice layer and first medium layer 32,
Method for example with chemical vapor deposition (CVD) forms germanium silicon in first medium layer 32 and the first sacrificial layer surface
Layer.Then the graphical germanium silicon layer forms micro mechanical structure (cantilever), and exposes the surface of the sacrifice layer of part first simultaneously.
Then, form the second sacrifice layer in semicon-ductor structure surface obtained above (in the cavity 35, not shown).
Second sacrifice layer is used to making the upper space of cantilever, therefore is at least covered in the first sacrifice layer and micro mechanical structure layer
Surface, its thickness is not less than the stroke that the cantilever is bent upwards.In the present embodiment, material and the formation of second sacrifice layer
Method is identical with the first sacrifice layer, and is connected with each other.
As shown in figure 3, etching second sacrifice layer forms the second groove (not shown).The second bottom portion of groove alignment
First medium layer 32, and expose micro mechanical structure layer.Second sacrifice layer is also divided into square region by second groove, and preceding
State the first sacrifice layer corresponding.The etching equally can be plasma etching.
As shown in figure 3, covering to form second dielectric layer 33 on the surface of the second sacrifice layer, the second dielectric layer 33 is also filled out
Fill in the second groove, its material and formation process can be identical with first medium layer 32.
As shown in figure 3, using cmp, the thinning second dielectric layer 33 is until expose the table of the second sacrifice layer
Face.After the second dielectric layer 33 of the second sacrificial layer surface has been ground, the second dielectric layer 33 only retains former second groove
Interior part, and the top surface of second dielectric layer 33 and the second sacrifice layer flush.
As shown in figure 3, electric pole plate (not shown) and capping layer 34 are sequentially formed on the surface of second sacrifice layer,
For example silicon dioxide layer or other silicon compound layers can be formed using the method for CVD.The electric pole plate and micro mechanical structure
Layer and bottom electrode plate are corresponding, and layer is driven as second.The bottom electrode plate forms drive with electric pole plate in MEMS
Electromotive field, acts in the electric field force of micro mechanical structure layer.
As shown in figure 3, etching the capping layer 34 forms through hole 34a, the second sacrifice is exposed in the bottom of the through hole 34a
Layer；Then the second sacrifice layer and the first sacrifice layer are removed by the through hole 34a, in the present embodiment, the through hole is straight
0.3 μm -0.4 μm of footpath, such as 0.35 μm of circular hole.
Specifically, to being passed through oxygen in through hole 34a, and cineration technics can be carried out being removed the second sacrifice layer in the present embodiment
And first sacrifice layer, just form the upper space and lower space of micro mechanical structure layer (i.e. cantilever).Now the cantilever is only
There is the one end being connected with first medium layer 32 and second dielectric layer 33 to be fixed, and the other end is then suspended in above-mentioned space,
Flexure operation up or down can be carried out.
Then, step S11 is performed, as shown in figure 4, deposited oxide layer is to the through hole on capping layer on the capping layer
34a is closed.
As shown in figure 4, using chemical vapor deposition method, forming the covering through hole 34a's on the surface of capping layer 34
Oxide skin(coating) 37, the oxide skin(coating) 37 is easy to block the through hole 34a on capping layer 34 in forming process.When above-mentioned logical
After hole 34a is blocked, the upper space and lower space just constitute the closing space for accommodating cantilever.
But inventor has found, in current manufacture craft, the through hole 34a closings of oxide skin(coating) 37 pairs are being formed
During, on the semiconductor substrate of the bottom of cavity 35, floccule defect can be produced, and the performance of device is influenceed, therefore send out
After person of good sense's research, the forming process of capping layer is improved, below step was increased before capping layer completely encloses the through hole.
Then, step S12 is performed, as shown in figure 4, before through hole closing is completely enclosed, to by the through hole
The cavity 35 is ashed.It is preferred in the present embodiment, be in oxidated layer thicknessFor exampleWhen the cavity is ashed.Specifically, it is possible to use fluorine base gas is ashed, it is also possible to
The mixing of low discharge oxygen is ashed, and the fluorine base gas is HF, CF4、C4F8、CHF3In one or more.In this implementation
In example, specifically, by the use of HF as plasma, the pressure range in etching reaction chamber is employed for 6mtorr~8mtorr,
It is 5sccm~20sccm to the podzolic gas range of flow being passed through in etching reaction chamber, ashing time scope is：20~40s, temperature
Preferred less than 200 DEG C low temperature dry ashings are spent, so may insure that polymer residue can be obtained from the unclosed through hole 34a
Thoroughly removal.
Then, step S13 is performed, as shown in figure 5, continue deposited oxide layer 37, until the through hole 34a is sealed completely
Close.Preferably, the material of the oxide skin(coating) is silica.The gross thickness of the oxide skin(coating) is
For example
Although the present invention is disclosed as above with preferred embodiment, the present invention is not limited to this.Any art technology
Personnel, without departing from the spirit and scope of the present invention, can make various changes or modifications, therefore protection scope of the present invention should
It is defined when by claim limited range.
Claims (10)
1. a kind of manufacture method of MEMS, it is characterised in that including step：
Semiconductor substrate is provided, it includes cavity, the cavity is a part for MEMS, and the top of cavity has arrangement
There is the capping layer of through hole；
Deposited oxide layer is closed to the through hole on capping layer on the capping layer；
Before through hole closing is completely enclosed, to being ashed to the cavity by the through hole；
Continue deposited oxide layer until the through hole is completely enclosed.
2. the manufacture method of MEMS as claimed in claim 1, it is characterised in that the material of the oxide skin(coating) is dioxy
SiClx.
3. the manufacture method of MEMS as claimed in claim 2, it is characterised in that form the capping layer as described before and lead to
Hole is the circular hole of 0.3 μm -0.4 μm of diameter.
4. the manufacture method of MEMS as claimed in claim 3, it is characterised in that be in the oxide layer thicknessesWhen the cavity is ashed.
5. the manufacture method of MEMS as claimed in claim 2, it is characterised in that the gross thickness of the oxide skin(coating) is
6. the manufacture method of MEMS as claimed in claim 2, it is characterised in that the ashing is to utilize fluorine base gas.
7. the manufacture method of MEMS as claimed in claim 6, it is characterised in that the fluorine base gas be HF, CF4,
One or more in C4F8, CHF3.
8. the manufacture method of MEMS as claimed in claim 7, it is characterised in that the fluorine base gas in the cineration technics
It is fluoro plasma.
9. the manufacture method of MEMS as claimed in claim 2, it is characterised in that the technological temperature of the cineration technics is low
In 200 DEG C.
10. the manufacture method of MEMS as claimed in claim 9, it is characterised in that the cineration step, etching reaction chamber
In pressure range be 6mtorr~8mtorr, to the podzolic gas range of flow being passed through in etching reaction chamber be 5sccm~
20sccm, ashing time scope is：20~40s.
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| CN201710079146.3A CN106865489B (en) | 2017-02-14 | 2017-02-14 | The manufacturing method of MEMS device |
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| CN201710079146.3A CN106865489B (en) | 2017-02-14 | 2017-02-14 | The manufacturing method of MEMS device |
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| CN106865489B CN106865489B (en) | 2019-01-18 |
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| US20150266718A1 (en) * | 2012-08-22 | 2015-09-24 | Wispry, Inc. | Semiconductor structures provided within a cavity and related design structures |
| US20150307345A1 (en) * | 2014-04-28 | 2015-10-29 | Kabushiki Kaisha Toshiba | Electronic device and manufacturing method of the same |
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2017
- 2017-02-14 CN CN201710079146.3A patent/CN106865489B/en active Active
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040126953A1 (en) * | 2002-10-23 | 2004-07-01 | Cheung Kin P. | Processes for hermetically packaging wafer level microscopic structures |
| JP2005123561A (en) * | 2003-09-25 | 2005-05-12 | Kyocera Corp | Sealing structure of micro electronic mechanical system, sealing method therefor, and micro electronic mechanical system |
| CN101492149A (en) * | 2008-01-25 | 2009-07-29 | 株式会社东芝 | Electrical device |
| US20110053321A1 (en) * | 2009-08-31 | 2011-03-03 | Shanghai Lexvu Opto Microelectronics Technology Co., Ltd | Method of fabricating and encapsulating mems devices |
| CN102408093A (en) * | 2011-10-21 | 2012-04-11 | 上海先进半导体制造股份有限公司 | Manufacturing method of isolated cavity |
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| US20150266718A1 (en) * | 2012-08-22 | 2015-09-24 | Wispry, Inc. | Semiconductor structures provided within a cavity and related design structures |
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