CN108002342B - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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CN108002342B
CN108002342B CN201610933794.6A CN201610933794A CN108002342B CN 108002342 B CN108002342 B CN 108002342B CN 201610933794 A CN201610933794 A CN 201610933794A CN 108002342 B CN108002342 B CN 108002342B
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layer
substrate
etching
protective layer
opening
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CN108002342A (en
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张建华
汪新学
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00134—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems comprising flexible or deformable structures
    • B81C1/00158—Diaphragms, membranes
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81B—MICROSTRUCTURAL DEVICES OR SYSTEMS, e.g. MICROMECHANICAL DEVICES
    • B81B3/00—Devices comprising flexible or deformable elements, e.g. comprising elastic tongues or membranes
    • B81B3/0018—Structures acting upon the moving or flexible element for transforming energy into mechanical movement or vice versa, i.e. actuators, sensors, generators
    • B81B3/0021—Transducers for transforming electrical into mechanical energy or vice versa

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Chemical & Material Sciences (AREA)
  • Analytical Chemistry (AREA)
  • Computer Hardware Design (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, comprising the following steps: providing a base, wherein the base comprises a semiconductor substrate, a dielectric layer formed on the semiconductor substrate and a vibration film layer formed on the dielectric layer; forming a protective layer on the substrate, wherein an opening for exposing the surface of the substrate is formed in the protective layer; depositing a covering layer covering the substrate and the protective layer, wherein the material of the covering layer is the same as that of the protective layer; and etching the covering layer to form a gap wall at the corner of the opening. Compared with the prior art, the manufacturing method of the semiconductor device can avoid the generation of silicon nitride residues in the opening of the protective layer in the process of etching silicon nitride.

Description

Semiconductor device and manufacturing method thereof
Technical Field
The present invention relates to a semiconductor manufacturing process, and more particularly, to a semiconductor device and a method of manufacturing the same.
Background
With the continuous development of semiconductor technology, smart phones, integrated CMOS and micro-electro-mechanical systems (MEMS) devices are increasingly becoming the most mainstream and advanced technology in the market of sensor-like products, and with the updating of technology, the development direction of such transmission sensor products is smaller scale, high quality electrical performance and lower loss. Among them, Micro Electro Mechanical Systems (MEMS) have significant advantages in terms of volume, power consumption, weight, and price, and various sensors, such as pressure sensors, acceleration sensors, inertial sensors, and others, have been developed so far.
The traditional pressure sensor has the limitations of larger size, more complex manufacturing process, inconvenient operation and the like. MEMS (Micro-Electro-Mechanical Systems) technology is widely used in the fabrication of pressure sensors. The pressure sensor manufactured by the MEMS technology has the advantages of microminiaturization, batch manufacturing, low cost, high precision and the like, and the pressure sensor and the control circuit can be integrated on the same substrate, so that weak output signals of the sensor can be amplified nearby, the external electromagnetic interference is avoided, and the reliability of transmission signals is improved.
The MEMS chip in the pressure sensor needs to be packaged after completion. That is, circuit pins on the chip are wired to external connections for connection to other devices. Ball bumps are typically formed in some areas of the device to replace the leads and silicon nitride for support or isolation is formed in other areas. In order to avoid damaging the device surface in the process of etching the silicon nitride, a protective layer is required to be formed on the device surface, and an opening for forming a bump is formed in the protective layer. When the silicon nitride is etched, residues are easily formed at the corners of the opening, which affects the performance of the device.
Therefore, it is necessary to provide a semiconductor device and a method for manufacturing the same to solve the above problems.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a base, wherein the base comprises a semiconductor substrate, a dielectric layer formed on the semiconductor substrate and a vibration film layer formed on the dielectric layer;
forming a protective layer on the substrate, wherein an opening for exposing the surface of the substrate is formed in the protective layer;
depositing a covering layer covering the substrate and the protective layer, wherein the material of the covering layer is the same as that of the protective layer;
and etching the covering layer to form a gap wall at the corner of the opening.
Illustratively, the step of performing a wet etching process to remove the dielectric layer is further included after the step of etching the capping layer.
Illustratively, the wet etching step further removes the protective layer and the spacer.
Illustratively, the dielectric layer is made of the same material as the cover layer and the protective layer.
Illustratively, the dielectric layer, the cover layer and the protective layer are oxide layers.
Illustratively, a first opening is formed in the protective layer on the first region of the substrate and a second opening is formed in the protective layer on the second region of the substrate.
Illustratively, the step of performing etching to form a through hole in the substrate below the second opening is further included after forming the spacer at the corner of the opening.
Illustratively, the method further comprises the steps of depositing a silicon nitride layer in the through hole and the protective layer and the substrate, and performing etching to remove the silicon nitride layer in the first region.
Illustratively, the covering layer is a plasma enhanced oxide layer deposited by taking tetraethoxysilane as a raw material.
Illustratively, the capping layer has a thickness of 2500-.
Illustratively, the method for etching the cap layer is dry etching, and the etching gas comprises CF 4Ar and CHF 3。
Illustratively, the method for etching the protective layer is dry etching, and the etching gas comprises CF 4Ar and CHF 3。
The invention also provides a semiconductor device which is characterized by being manufactured by the method.
Compared with the prior art, the manufacturing method of the semiconductor device can avoid the generation of silicon nitride residues in the opening of the protective layer in the process of etching silicon nitride.
Drawings
The following drawings of the invention are included to provide a further understanding of the invention. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.
In the drawings:
FIGS. 1 a-1 d are cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device according to the prior art;
fig. 2 is a schematic flow chart of a method of manufacturing a semiconductor device of an embodiment of the present invention;
fig. 3 a-3 f are cross-sectional views of structures formed at steps associated with a method of fabricating a semiconductor device in an embodiment of the present invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the present invention. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the invention.
It is to be understood that the present invention may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Like reference numerals refer to like elements throughout.
It will be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it can be directly on, adjacent to, connected or coupled to the other elements or layers or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to" or "directly coupled to" other elements or layers, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.
Spatial relational terms such as "under," "below," "under," "above," "over," and the like may be used herein for convenience in describing the relationship of one element or feature to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, then elements or features described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "under" can encompass both an orientation of above and below. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatial descriptors used herein interpreted accordingly.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.
As shown in fig. 1a to 1d, a method for manufacturing a semiconductor device in the prior art includes: depositing a protective layer 104 on a substrate comprising a semiconductor substrate 101, a dielectric layer 102 and a vibration film layer 103, and etching the protective layer 104 to form an opening, as shown in fig. 1 a; then, forming a patterned photoresist layer 105 on the protection layer, and etching the substrate with the patterned photoresist layer as a mask to form a through hole, as shown in fig. 1 b; next, a silicon nitride layer 106 is deposited in the via hole and on the protection layer, as shown in fig. 1 c; next, a patterned photoresist layer 107 is formed on the silicon nitride layer 106, and the silicon nitride layer 106 is etched using the patterned photoresist layer 107 as a mask. During the etching process of the silicon nitride layer, residues 108 are easily formed on the side walls of the openings, and silicon nitride particles are formed on the residues 108 during the BOE (buffer oxide etch) process and are attached to the vibrating film layer through the etching solution to block the through holes on the vibrating film, thereby affecting the performance of the device. If the etching time is increased to avoid the silicon nitride residue, the underlying substrate is easily damaged.
Aiming at the defects of the prior art, the invention provides a manufacturing method of a semiconductor device, which comprises the following steps:
providing a base, wherein the base comprises a semiconductor substrate, a dielectric layer formed on the semiconductor substrate and a vibration film layer formed on the dielectric layer; forming a protective layer on the substrate, wherein an opening for exposing the surface of the substrate is formed in the protective layer;
depositing a covering layer covering the substrate and the protective layer, wherein the material of the covering layer is the same as that of the protective layer;
and etching the covering layer to form a gap wall at the corner of the opening.
And performing wet etching after the covering layer is etched to remove the dielectric layer. And the wet etching step also removes the protective layer and the gap wall.
The material of the dielectric layer is the same as that of the covering layer and the protective layer. The dielectric layer, the covering layer and the protective layer are all oxide layers.
A first opening is formed in the protective layer on the first region of the substrate and a second opening is formed in the protective layer on the second region of the substrate. And forming a gap wall at the corner of the opening, and then performing etching to form a through hole in the substrate below the second opening. The method also comprises the steps of depositing a silicon nitride layer in the through hole, the protective layer and the substrate, and etching to remove the silicon nitride layer in the first area.
The covering layer is a plasma enhanced oxide layer deposited by taking tetraethoxysilane as a raw material. The thickness of the covering layer is 2500-. The method for etching the covering layer is dry etching, and etching gas comprises CF 4Ar and CHF 3。
The method for etching the protective layer is dry etching, and the etching gas comprises CF 4Ar and CHF 3。
Compared with the prior art, the manufacturing method of the semiconductor device can avoid the generation of silicon nitride residues in the opening of the protective layer in the process of etching silicon nitride.
In the following description, for purposes of explanation, specific details are set forth in order to provide a thorough understanding of the present invention. The following detailed description of the preferred embodiments of the invention, however, the invention is capable of other embodiments in addition to those detailed.
[ exemplary embodiment one ]
A method for manufacturing a semiconductor device according to an embodiment of the present invention will be described in detail with reference to fig. 2 and 3a to 3 f.
First, step 201 is executed to provide a base 300, where the base includes a semiconductor substrate 301, a dielectric layer 302 formed on the semiconductor substrate 301, and a vibration film layer 303 formed on the dielectric layer 302, as shown in fig. 3 a.
Specifically, the semiconductor substrate 301 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In the present embodiment, the semiconductor substrate is a silicon substrate. A CMOS device and various MEMS elements, which are necessary components of the MEMS sensor, can be formed on the semiconductor substrate 301. Preferably, the thickness of the semiconductor substrate is 725 um. The dielectric layer 302 is made of silicon oxide or other feasible materials and is formed by chemical vapor deposition, and has the functions of isolation and support. Preferably, the thickness of the dielectric layer is 30000 angstroms. The diaphragm layer 303 is made of silicon or polysilicon, and functions to directly convert pressure into an electrical energy signal. In this embodiment, the thickness of the vibration film layer 303 is preferably 30000 angstroms. The deposition method of the vibration film layer 303 in the present invention may be one of Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD) and epitaxial growth formed by a Chemical Vapor Deposition (CVD) method, a Physical Vapor Deposition (PVD) method, an Atomic Layer Deposition (ALD) method, or the like.
Next, step 202 is performed to form a protection layer 304 on the substrate, wherein a first opening 305 is formed in the protection layer on the first region of the substrate, and a second opening 306 is formed in the protection layer on the second region of the substrate. The first opening 305 is a location where a bump is formed and the second region of the substrate is a location where a silicon nitride layer is formed. The thickness of the protective layer 304 is 5500-6500 angstroms, preferably 6000 angstroms. A layer of protective material is first deposited on the substrate 300. the material of the protective layer 304 may be polyimide, silicon dioxide, other insulating polymers, oxides (e.g., silicon nitride, silicon oxynitride), or carbides (e.g., silicon carbide, silicon oxycarbide). In this embodiment, the passivation layer 304 is an oxide. Next, the protective layer is etched to form a first opening 305 and a second opening 306. The etching method is dry etching, the etching gas used in the etching process comprises fluorine-containing gas, and the fluorine-containing gas is gas with high fluorine content, preferably CF 4And CHF 3A gas. Ar gas is also used as an isolation gas in the etching process. Illustratively, the RF power range is 1500-1900W, the pressure range is 130-210 mTorr, the bias power range is 90-110W, and the flow rate of the etching gas is 20-45 sccm.
Next, step 203 is performed, as shown in fig. 3b, a capping layer 307 is deposited covering the substrate and the protective layer, wherein the material of the capping layer 307 is the same as that of the protective layer 304. Preferably, the material of the dielectric layer 302 is the same as that of the capping layer 307 and the protection layer 304, and the dielectric layer 302, the capping layer 307 and the protection layer 304 are both oxide layers.
Illustratively, a plasma enhanced oxide layer is deposited as a capping layer 307 from Tetraethylorthosilicate (TEOS), wherein the thickness of the capping layer 307 is 2500-. Specifically, precursors including TEOS, oxygen and inert gases such as helium, argon, etc. are supplied into a chamber containing the device, and a silicon dioxide capping layer covering the substrate and the protective layer is deposited by a plasma enhanced chemical vapor deposition method at a temperature between 200-350 ℃. Because the TEOS has high surface mobility, the TEOS has good step coverage rate, and can avoid the generation of low-density areas or cavities.
Next, step 204 is performed to etch the capping layer 307 to form a spacer 308 at the corner of the opening, as shown in fig. 3 c. Specifically, the etching is non-pattern etching, the etching method is dry etching, etching gas used in the etching process comprises fluorine-containing gas, and the fluorine-containing gas is gas with high fluorine content, preferably CF 4And CHF 3A gas. Ar gas is also used as an isolation gas in the etching process. Illustratively, the RF power range is 1500-1900W, the pressure range is 130-210 mTorr, the bias power range is 90-110W, and the flow rate of the etching gas is 20-45 sccm. In this embodiment, the thickness of the passivation layer 304 is reduced to 5000 angstroms by performing the present step.
Next, step 205 is performed, as shown in fig. 3d, etching is performed to form a via in the substrate under the second opening. First, a patterned mask layer 309 is formed on the device surface. The window of the patterned mask layer 309 defines the location of the via, which is located inside the second opening 306. The patterned mask layer 309 may be any suitable mask material known to those skilled in the art, including but not limited to a photoresist material or a hard mask material, and in this embodiment, the mask layer 309 is a photoresist. Illustratively, a photoresist layer is spin-coated on the substrate and the protective layer, and the photoresist is patterned through photolithography processes such as exposure and development, so that the window defines the position of the through hole. And then, etching is carried out by taking the photoresist layer as a mask so as to form a through hole in the substrate. The etching method is anisotropic dry etching, such as plasma dry etching or reactive ion etching. Thereafter, the photoresist layer may be removed using conventional processes such as oxygen plasma ashing.
Next, step 206 is performed, as shown in fig. 3e, a silicon nitride layer 310 is deposited in the via hole and on the protective layer and the substrate. The deposition method may employ any suitable process technique known to those skilled in the art, such as one of Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), Atomic Layer Deposition (ALD), Low Pressure Chemical Vapor Deposition (LPCVD), Laser Ablation Deposition (LAD), and Selective Epitaxial Growth (SEG), which in this embodiment is chemical vapor deposition. The deposited silicon nitride layer 310 has a thickness of 9000-11000 angstroms, preferably 10000 angstroms. The silicon nitride layer fills the through hole and covers the protective layer and the surface of the substrate.
Next, step 207 is performed to perform etching to remove the silicon nitride layer in the first region, as shown in fig. 3 f. First, a patterned mask layer 309 is formed on the device surface. The patterned mask layer covers the silicon nitride layer 310 over the second region of the substrate. The patterned masking layer 311 may be any suitable masking material known to those skilled in the art, including but not limited to a photoresist material or a hard mask material, and in the present embodiment, the masking layer 311 is a photoresist. And then, etching is carried out by taking the photoresist layer as a mask, and the silicon nitride layer on the first region of the substrate is removed. The etching method is anisotropic dry etching, such as plasma dry etching or reactive ion etching. Illustratively, the etching gas used in etching the silicon nitride layer includes a fluorine-containing gas, such as CF 4、CHF 3、SF 6And the like. Under the etching condition using the fluorine-containing gas, fluorine reacts with silicon nitride to generate volatile substances to be discharged, and the silicon nitride layer has a high etching rate. Ar gas may be used as a barrier gas during the etching of the layer. Since the first opening 305 has a corner formed with a spacer 308, the silicon nitride layer 310 is etchedSilicon nitride residues are not formed at the corners. Thereafter, the photoresist layer may be removed using conventional processes such as oxygen plasma ashing. In this embodiment, the etching process in this step also makes the protective layer of the first region level with the upper edge of the spacer 308.
After the steps are performed, a bump is further formed in the first opening, and wet etching is performed to remove the dielectric layer 302, so that the vibration film layer 303 is released. Since the material of the dielectric layer 302 is the same as that of the capping layer 307 and the protection layer 304, and both are oxide layers, the wet etching step also removes the protection layer 304 and the spacer 308 at the same time without generating particles formed by SiN residues, thereby improving the performance of the device.
To this end, the process steps performed by the method according to the first exemplary embodiment of the present invention are completed. It is understood that the method for manufacturing a semiconductor device of the present embodiment includes not only the above steps, but also other steps as needed before, during or after the above steps, which are included in the scope of the method for manufacturing the semiconductor device.
Compared with the prior art, the manufacturing method of the semiconductor device can avoid the generation of silicon nitride residues in the opening of the protective layer in the process of etching silicon nitride.
[ second exemplary embodiment ]
Referring to fig. 3f, there is shown a schematic cross-sectional view of a semiconductor device obtained according to the manufacturing method provided by the present invention. The semiconductor device includes: the base 300 comprises a semiconductor substrate 301, a dielectric layer 302 formed on the semiconductor substrate 301, and a vibration film layer 303 formed on the dielectric layer 302; a protection layer 304 formed on the substrate, wherein an opening exposing the substrate surface is formed in the protection layer 304, a spacer 308 is formed at a corner of the opening, and the material of the spacer 308 is the same as that of the protection layer 304.
Specifically, the base 300 includes a semiconductor substrate 301, a dielectric layer 302, and a vibration film layer 303. The semiconductor substrate 301 may be at least one of the following materials: silicon, silicon-on-insulator (SOI), silicon-on-insulator (SSOI), silicon-on-insulator-silicon-germanium (S-SiGeOI), silicon-on-insulator-silicon-germanium (SiGeOI), and germanium-on-insulator (GeOI), among others. In the present embodiment, the semiconductor substrate is a silicon substrate. A CMOS device and various MEMS elements, which are necessary components of the MEMS sensor, can be formed on the semiconductor substrate 301. Preferably, the thickness of the semiconductor substrate is 725 um. The dielectric layer 302 is made of silicon oxide or other feasible materials and is formed by chemical vapor deposition, and has the functions of isolation and support. Preferably, the thickness of the dielectric layer is 30000 angstroms. The vibration film layer 303 is made of silicon or polysilicon, and preferably, the thickness of the vibration film layer 303 is 30000 angstroms.
A protective layer 304 is formed on the substrate, and an opening exposing the surface of the substrate is formed in the protective layer 304. Specifically, a first opening 305 is formed in the passivation layer on the first region of the substrate, a second opening 306 is formed in the passivation layer on the second region of the substrate, the first opening 305 is a position for forming a bump, and the second region of the substrate is a position for forming a silicon nitride layer. The protective layer 304 may be polyimide, silicon dioxide, other insulating polymers, oxides (e.g., silicon nitride, silicon oxynitride), or carbides (e.g., silicon carbide, silicon oxycarbide). The thickness of the passivation layer 304 is 4500-. In this embodiment, the passivation layer 304 is an oxide. A gapped wall 308 is formed at the corners of the first and second openings of the protective layer. Specifically, a capping layer is first formed on the substrate and the protective layer, the material of the capping layer is the same as that of the protective layer, the capping layer is a plasma enhanced oxide layer deposited by using tetraethyl orthosilicate (TEOS) as a raw material, and the thickness of the capping layer 307 is 2500-. The capping layer is then etched to form spacers 308 at the corners of the opening.
A through hole is formed in the second region of the substrate. The through-hole is formed in the substrate below the second opening 306. A silicon nitride layer 310 is formed in the via and on the second region of the substrate. Illustratively, the silicon nitride layer over the substrate has a thickness of 10000 angstroms.
Compared with the prior art, the semiconductor device provided by the invention has no silicon nitride residues in the opening of the protective layer.
The present invention has been illustrated by the above embodiments, but it should be understood that the above embodiments are for illustrative and descriptive purposes only and are not intended to limit the invention to the scope of the described embodiments. Furthermore, it will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, and that many variations and modifications may be made in accordance with the teachings of the present invention, which variations and modifications are within the scope of the present invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (10)

1. A method of manufacturing a semiconductor device, comprising:
providing a base, wherein the base comprises a semiconductor substrate, a dielectric layer formed on the semiconductor substrate and a vibration film layer formed on the dielectric layer;
forming a protective layer on the substrate, wherein an opening exposing the surface of the substrate is formed in the protective layer, a first opening is formed in the protective layer on a first region of the substrate, and a second opening is formed in the protective layer on a second region of the substrate;
depositing a covering layer covering the substrate and the protective layer, wherein the material of the covering layer is the same as that of the protective layer;
etching the covering layer to form a gap wall at the corner of the opening;
etching is carried out to form a through hole in the substrate below the second opening;
depositing a silicon nitride layer in the through hole and on the protective layer and the substrate; and
and etching is carried out to remove the silicon nitride layer in the first region.
2. The method of claim 1, further comprising the step of performing a wet etch to remove the dielectric layer after etching the capping layer.
3. The method of claim 2, wherein the wet etching step further removes the protective layer and the spacer.
4. The method of claim 1, wherein the dielectric layer is the same material as the capping layer and the protective layer.
5. The method of claim 4, wherein the dielectric layer, the capping layer, and the protective layer are oxide layers.
6. The method of claim 5, wherein the capping layer is a plasma enhanced oxide layer deposited from tetraethylorthosilicate.
7. The method as claimed in claim 1, wherein the capping layer has a thickness of 2500-3500 angstroms.
8. The method of claim 1, wherein the cap layer is etched by a dry etch process using an etching gas comprising CF 4Ar and CHF 3。
9. The method of claim 1, wherein the protective layer is etched using a dry etch process and the etching gas comprises CF 4Ar and CHF 3。
10. A semiconductor device, characterized in that it is manufactured using the method of any of claims 1-9.
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CN102173377A (en) * 2011-03-15 2011-09-07 上海集成电路研发中心有限公司 Semiconductor device and manufacturing method thereof
CN103337456A (en) * 2013-06-27 2013-10-02 上海华力微电子有限公司 Method for improving breakdown voltage of capacitor
CN104617033A (en) * 2013-11-05 2015-05-13 中芯国际集成电路制造(上海)有限公司 Wafer level packaging method

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Publication number Priority date Publication date Assignee Title
JPWO2003015183A1 (en) * 2001-08-01 2004-12-02 三菱電機株式会社 Method for manufacturing thin film structure

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102173377A (en) * 2011-03-15 2011-09-07 上海集成电路研发中心有限公司 Semiconductor device and manufacturing method thereof
CN103337456A (en) * 2013-06-27 2013-10-02 上海华力微电子有限公司 Method for improving breakdown voltage of capacitor
CN104617033A (en) * 2013-11-05 2015-05-13 中芯国际集成电路制造(上海)有限公司 Wafer level packaging method

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