CN117208841A - Method for forming MEMS sensor structure - Google Patents

Abstract

The application discloses a method for forming a MEMS sensor structure, which can avoid the problem that the use effect of a device is affected by pollution of a first cavity of a packaging wafer. The application provides a method for forming a MEMS sensor structure, which comprises the following steps: providing a first wafer having opposite first and second surfaces; forming a barrier layer on a first surface of the first wafer; providing a capping wafer, wherein a first cavity is formed on the surface of the capping wafer; bonding the capping wafer with the barrier layer to seal the first cavity; performing first etching on the first wafer from the second surface to form a boss, wherein the boss comprises an upper table top and a lower table top; performing second etching on the first wafer, and forming an initial groove penetrating through the first wafer on the lower table top; and etching the barrier layer at the bottom of the initial groove to form a groove, wherein the groove is positioned above the first cavity and communicated with the first cavity, and the first wafer part separated from the groove is formed into a suspension structure and/or an interdigital structure of the functional layer.

Description

Method for forming MEMS sensor structure

Technical Field

The application relates to the field of MEMS sensor structure preparation, in particular to a method for forming an MEMS sensor structure.

Background

MEMS sensors are novel sensors fabricated using microelectronics and micromachining techniques. The intelligent power supply device has the characteristics of small volume, light weight, low cost, low power consumption, high reliability, high technical added value, suitability for batch production, easy integration, realization of intellectualization and the like. The MEMS sensor includes: pressure sensors, thermal sensors, mechanical sensors, chemical sensors, magnetic sensors, radiation sensors, electrical sensors, etc.

The gyroscope MEMS sensor structure is a high and new technology product, has various advantages of small volume, low power consumption and the like, has wide application prospect in the civil consumption field and the modern national defense field, and has low cost. The gyroscopic MEMS sensor structure requires the use of the interdigital structure to detect changes in orientation. In these embodiments, each comb may act as a comb electrode that moves upon application of a force perpendicular to the length of the comb electrode and causes a change in capacitance between the comb electrode and the fixed electrode, thereby obtaining an electrical parameter that can be detected by the dedicated circuitry.

The MEMS sensor also includes an angular velocity meter, an accelerometer, a flow meter, a magnetic MEMS sensor, a gas MEMS sensor, and the like.

Before using the MEMS sensor structure, the MEMS sensor structure needs to be packaged to protect the MEMS sensor structure and to facilitate the application of the MEMS sensor structure.

The method for forming the MEMS sensor structure commonly used in the prior art includes covering the first surface of the first wafer with a capping wafer, where the first surface of the first wafer may form functional devices, and a surface of the capping wafer opposite to the first wafer is usually also provided with a first cavity for implementing heat insulation and the like on the first wafer.

In the prior art, in the MEMS sensor structure, undesirable impurities often occur in the first cavity between the first wafer and the capping wafer, which affects the use effect of the device.

There is a need to propose an optimal design to avoid or alleviate the above-mentioned problems.

Disclosure of Invention

In view of this, the present application provides a method for forming a MEMS sensor structure, which can avoid or alleviate the problem that undesirable impurities occur in the first cavity of the package wafer, and affect the use effect of the device.

The application provides a method for forming a MEMS sensor structure, which comprises the following steps: providing a first wafer for forming a functional layer of the MEMS sensor, the first wafer having opposite first and second surfaces; forming a barrier layer on a first surface of the first wafer; providing a cover wafer, wherein a first cavity is formed on the surface of the cover wafer; bonding the capping wafer with a barrier layer to seal the first cavity; performing first etching on the first wafer from the second surface to form a boss, wherein the boss comprises an upper table top and a lower table top; performing second etching on the first wafer from the second surface, and forming an initial groove penetrating through the first wafer on a lower table top; etching the barrier layer at the bottom of the initial groove to form one or more grooves, wherein the grooves are positioned above the first cavity and communicated with the first cavity, and the first wafer part separated from the grooves is formed into a suspension structure and/or an interdigital structure of the functional layer; and providing a third wafer, wherein a control circuit is arranged in the third wafer, bonding a boss of the first wafer and the third wafer to form a second cavity, and the projection parts or all of the first cavity and the second cavity on the surface of the third wafer are overlapped.

According to the method for forming the MEMS sensor structure, the blocking layer is arranged on the first surface of the first wafer and is at least distributed in the area, corresponding to the first cavity, of the first surface of the first wafer, so that in the process of forming the initial groove above the first wafer, the blocking layer can be blocked between the first cavity and the initial groove and used for blocking objects from entering the first cavity in the etching process, the problem that byproducts such as polymers and the like in the process of forming the initial groove on the first wafer and byproducts generated in the subsequent process flow enter the first cavity is avoided, and the performance of the formed sensor is improved.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart illustrating steps of a method for forming a MEMS sensor structure according to an embodiment.

FIGS. 2-12 are schematic structural diagrams of a method for forming a MEMS sensor structure in an embodiment.

Detailed Description

It has been found that after the capping wafer is disposed on the first surface of the first wafer, undesirable impurities often occur in the first cavity of the packaging wafer, which affect the final heat-insulating effect, and structures formed in the region of the first wafer opposite to the opening of the first cavity may also have poor morphological structures due to the influence of impurities, which affect the final sensing effect of the MEMS sensor structure.

It has been found that the above problem arises because, after the capping wafer is disposed on the first surface of the first wafer, patterning and etching are further required on the first wafer to form a functional layer of the device structure, where the structure of the functional layer includes forming a trench penetrating through the first cavity on the first wafer. Because the material of the first wafer is silicon, silicon polymers are easy to form in the process of etching the first wafer to form the grooves, and the grooves are communicated with the first cavity, so that the silicon polymers are difficult to remove when being adhered in the first cavity, and the quality of the first cavity is affected; at the same time, masking layers and the like are used in the processes, and the masking layers and the like are convenient to use, but additional removing operations are needed to remove, and the removing operations can lead undesired liquid, gas, solid and the like to enter a first cavity communicated with the groove, so that undesired objects appear in the first cavity, the heat insulation effect of the first cavity is influenced, the sensing precision of the MEMS sensor structure is influenced, and the like.

In order to solve the above problems, a MEMS sensor structure and a method of forming the same are proposed as follows.

The MEMS sensor structure and method of forming the same are further described below with reference to the drawings and examples.

Referring to fig. 1, a flow chart of steps of a method for forming a MEMS sensor structure according to an embodiment is shown.

In this embodiment, the forming method includes the steps of:

providing a first wafer 101, wherein the first wafer 101 is used for forming a functional layer of the MEMS sensor, and the first wafer 101 has a first surface 1011 and a second surface 1012 opposite to each other, and herein, reference may be made to fig. 2;

a barrier layer 102 is formed on the first surface 1011 of the first wafer 101, and herein, reference may be made to fig. 3, in which fig. 2 the device structure of the functional layers inside the first wafer 101 is not shown.

A capping wafer 103 is provided, and a first cavity 104 is formed on a surface of the capping wafer 103, as can be seen in fig. 4.

The capping wafer 103 is bonded to the barrier layer 102, sealing the first cavity 104, as can be seen in fig. 5.

Performing a first etching on the first wafer 101 from the second surface 1012 to form a boss 108, where the boss 108 includes an upper mesa and a lower mesa, as can be seen in fig. 7 herein;

performing a second etching on the first wafer 101 from the second surface 1012, and forming an initial trench 106 on a lower mesa through the first wafer 101, as can be seen in fig. 9;

etching the barrier layer 102 at the bottom of the initial trench 106 to form one or more trenches 107, where the trenches 107 are located above the first cavity 104 and are in communication with the first cavity 104, as can be seen in fig. 10, and the portion of the first wafer 101 separated by the trenches 107 is formed as a floating structure or an interdigital structure of the functional layer;

a third wafer 109 is provided, the third wafer 109 has a control circuit 140 therein, and the boss 108 of the first wafer 101 and the third wafer 109 are bonded to form a second cavity 130, and the projections of the first cavity 104 and the second cavity 130 on the surface of the third wafer 109 are partially or completely overlapped, which can be referred to herein as fig. 12.

According to the method for forming the MEMS sensor structure, the blocking layer 102 is arranged on the first surface 1011 of the first wafer 101, and the blocking layer 102 is at least distributed in the area of the first surface 1011 of the first wafer 101 corresponding to the first cavity 104, so that in the process of forming the initial groove 106 above the first wafer 101, the blocking layer 102 can be blocked between the first cavity 104 and the initial groove 106 and is used for blocking objects from entering the first cavity 104 in the etching process, thereby avoiding the problem that byproducts such as polymers and the like in the process of forming the initial groove 106 by etching the first wafer 101 and byproducts generated in the subsequent process flow enter the first cavity 104, and improving the performance of the formed sensor.

In some embodiments, the method further comprises the steps of: after forming the trench 107, the individual device structures formed by the first wafer 101 and the cap wafer 103 are cut and then integrated into the third wafer 109 for control.

In some embodiments, the third wafer 109 is a CMOS wafer.

In some other embodiments, the first wafer 101 and the capping wafer 103 may be integrated in a wafer state and then cut to form a single device structure after being integrated into a whole wafer where the third wafer 109 is located.

In some embodiments, the material of the first wafer 101 includes a semiconductor material, such as silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbide (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), or other III/V compound semiconductors, and may also be a double-sided polished silicon wafer (Double Side Polished Wafers, DSP), a ceramic substrate such as alumina, a quartz or glass substrate, or the like.

The first wafer 101 is used to form a functional layer of the MEMS sensor, and in some embodiments, the first wafer 101 is provided with corresponding device structures according to the functional role of the MEMS sensor structure, and the device structures are disposed on the first surface 1011 of the substrate or inside the substrate.

Taking a gyroscope as an example, the device structure comprises a mass block, a driving frame, a detecting frame, a plurality of elastic connecting beams, a driving electrode, a detecting electrode, a functional electrode and the like, wherein the connection relation among the components is not repeated here, and the driving electrode, the detecting electrode and the functional electrode are composed of a movable electrode and a fixed electrode. The whole structure of the gyroscope is a suspended movable structure except the boss 108 and the fixed electrode. The movable electrode and the fixed electrode are composed of interdigital electrodes, and grooves formed by subsequent etching are necessary items in the formation process of the suspended movable structure and the interdigital electrodes, so that the separation of the suspended movable structure or the interdigital separation of the interdigital electrodes is realized.

In some other embodiments, the MEMS sensor structure further comprises at least one of an angular velocity meter, an accelerometer, a flow meter, a magnetic MEMS sensor structure, a gas MEMS sensor structure.

The material of the capping wafer 103 includes a semiconductor material, such as silicon (Si), germanium (Ge), germanium silicon (SiGe), carbon Silicon (SiC), carbon germanium silicon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP) or other III/V compound semiconductors, and may also be a double-sided polished silicon wafer (Double Side Polished Wafers, DSP), or a ceramic substrate such as alumina, quartz or glass substrate.

The first cavity 104 is formed on the surface of the capping wafer 103 by at least one of the dry etching or the wet etching. Referring to fig. 4, a plurality of first cavities 104 are shown covering the surface of the wafer 103. Indeed, in some other embodiments, the number of first cavities 104 may be just one.

In this embodiment, the material of the cap wafer 103 is a semiconductor material, and can transmit infrared rays for detection related to the infrared rays. In other embodiments, the material of the capping wafer 103 may be an optical material, such as glass, a filter, a lens, or a polymer material, such as a dry film, a molding compound, or the like.

Referring to fig. 3, a barrier layer 102 is formed on a first surface 1011 of the first wafer 101.

In some embodiments, the material of the barrier layer 102 includes at least one of silicon oxide, silicon nitride, and TEOS, and may be selected as desired by one skilled in the art.

The process for forming the barrier layer 102 includes: physical vapor deposition processes, chemical vapor deposition processes, atomic layer deposition processes, and the like.

In some embodiments, the barrier layer 102 has a thickness of 0.3 microns to 3 microns, for example: 0.6 microns, 0.8 microns, 1.0 microns, 1.3 microns, 1.5 microns, 1.8 microns, 2 microns, or 2.5 microns, etc. To have a sufficient blocking effect while reducing the impact on device performance. The thickness of the barrier layer 102 is less than 0.3 micrometers, so that the corrosion resistance effect is insufficient; the barrier layer 102 has a thickness greater than 3 microns, which may affect the performance of the resulting device when the barrier layer 102 is positioned at the bottom of the subsequently formed suspended structures and/or interdigitated structures of the functional layer; meanwhile, the film layer is thicker, and the process cost is higher.

The thickness of the barrier layer 102 may also be selected reasonably according to the performance requirements of the MEMS sensor structure, so as to avoid affecting the performance of the device.

In this embodiment, since the first cavity 104 is sealed after the capping wafer 103 is bonded to the barrier layer 102, the barrier layer 102 may block between the first cavity 104 and the initial trench 106 in the subsequent process of forming the initial trench 106 on the second surface 1012 of the first wafer 101, so as to prevent objects from entering the first cavity 104 in the etching process, and avoid the problem that byproducts such as polymers in the process of forming the trench in the etching of the first wafer 101 and byproducts generated in materials or process flows used in the subsequent process flows enter the first cavity 104, thereby improving the performance of the formed sensor.

Referring to fig. 5, the capping wafer 103 is bonded to the barrier layer 102 to seal the first cavity 104.

The barrier layer 102 on the surface of the first wafer 101 seals the first cavity 104, so that the bonding between the first wafer 101 and the cap wafer 103 is realized by the barrier layer 102.

Based on the structure shown in fig. 5, after the bonding of the first wafer 101 and the capping wafer 103 is completed, the first wafer 101 may be thinned first, so that the finally formed device structure meets the thickness requirement of the MEMS sensor structure. After thinning, the resulting structure is shown in fig. 6.

Specifically, the first wafer 101 is thinned from the second surface 1012 of the first wafer 101, and the thickness of the thinned first wafer 101 meets the thickness requirement of the finally formed MEMS sensor structure. In some embodiments, after the first wafer 101 is inverted, the first wafer 101 is thinned down from the second surface 1012 of the first wafer 101 so that the thickness of the first wafer 101 meets the requirements.

After thinning, a subsequent structure is formed based on the thinned structure.

Referring to fig. 7, the first wafer 101 is first etched from the second surface 1012 to form a boss 108, where the boss 108 includes an upper mesa and a lower mesa.

The method comprises the following specific steps of: forming a first mask layer on a second surface 1012 of the first wafer 101; patterning the first mask layer to partially expose a second surface 1012 of the first wafer 101; the exposed areas on the second surface 1012 of the first wafer 101 are etched to a first depth in a direction perpendicular to the second surface 1012 of the first wafer 101 to form the lands 108.

The first depth is matched to the particular MEMS sensor structure to be formed.

After the formation of the mesa 108, a related step of removing the first mask layer is further included. In some embodiments, the first mask layer may also be removed along with a subsequently formed second mask layer 200.

The projection 108 does not overlap with the projection of the first cavity 104 on the surface of the first wafer 101, i.e. the projections of the projection 108 and the first cavity 104 on the surface of the first wafer 101 are offset from each other.

The boss 108 can provide space for the subsequent formation of the second cavity 130, and the boss 108 can serve as a supporting portion to provide support for components in the subsequently formed functional layer that need to be suspended. At the same time, the boss 108 also provides electrical connection for device structures within the functional layer.

In one embodiment, after forming the boss 108, before bonding the boss 108 of the first wafer 101 and the third wafer 109, the method further includes: a first interconnection layer 105 is formed on the upper mesa surface of the boss 108, and the first interconnection layer 105 is electrically connected to the functional layer in the first wafer 101.

The method for forming the first interconnection layer 105 includes: and forming a metal layer on the surface of the first wafer 101, and forming the first interconnection layer 105 in the process of etching to form the boss 108.

In other embodiments, the first interconnection layer 105 may be formed in the first wafer 101 in advance, after the first wafer 101 is thinned, the first interconnection layer 105 is exposed, and then the first wafer 101 is etched to form the first cavity 104.

In an embodiment, the first interconnect layer 105 is configured to electrically connect the functional layer to a control circuit 140 in a third wafer 109 provided later.

In some embodiments, the bump structure formed by the first interconnection layer 105 and the bump 108 may provide mechanical support for the device structure formed later, and provide an electrical connection point for the device structure in the first wafer 101 to connect to other controllers, such as a microcontroller, a single-chip microcomputer, etc., where the chip formed by the first wafer 101 and the cap wafer 103 may be connected to the conductive interconnection structure, such as a pad, of the other controllers through the first interconnection layer 105 formed by the upper mesa of the bump 108.

In practice, the upper mesa of the boss 108 may also be formed with metal pieces that are not electrically connected to the device structure, and these metal pieces may serve as metal connection keys for bonding with metal points of other devices when the first wafer 101 is assembled to the other devices.

In some embodiments, the material of the first interconnect layer 105 includes: germanium, aluminum, copper, gold, germanium or silver. In this embodiment, the material of the first interconnection layer 105 is germanium.

Referring to fig. 8 to 10, the first wafer 101 is subjected to a second etching from the second surface 1012, and an initial trench 106 penetrating the first wafer 101 is formed on the lower mesa; the barrier layer 102 at the bottom of the initial trench 106 is etched to form one or more trenches 107, the trenches 107 are located above the first cavity 104 and are communicated with the first cavity 104, and the first wafer 101 part separated by the trenches 107 is formed into a suspended structure or an interdigital structure of the functional layer.

Referring to fig. 8, a patterned second mask layer 200 is formed on the upper mesa and lower mesa surfaces of the mesa 108 to partially expose the lower mesa of the mesa 108.

The method for forming the second mask layer 200 includes: an initial second mask layer is formed on the upper mesa and the lower surface of the boss 108, and the initial second mask layer is subjected to patterning treatment, so that the lower mesa surface of a part of the boss 108 is exposed, and the patterned second mask layer 200 is formed.

The material of the second mask layer 200 includes a photosensitive material, and the photosensitive material includes: photoresist or other photosensitive organic film layer. And forming the initial second mask layer by adopting a spin coating process.

Next, the second mask layer 200 is used as a mask to etch the first wafer 101 and the barrier layer 102 down from the second surface 1012 to form the trench 107.

Referring to fig. 9, the step of etching the first wafer 101 to form the trench 106 by using the second mask layer 200 as a mask includes; etching the first wafer 101 by using the second mask layer 200 as a mask to form an initial trench 106; thereafter, the second mask layer 200 is removed, and a wet etching is performed to remove residues in the initial trench 106.

In some embodiments, the process of etching the first wafer 101 to form the initial trench 106 is an anisotropic dry etching process.

In some embodiments, the material of the second mask layer 200 includes photoresist, and the method for removing the second mask layer 200 includes: removing the second mask layer 200 by an ashing process; and removing the second mask layer 200 by adopting a photoresist removing solution, wherein the etching rate ratio of the photoresist removing solution to the second mask layer 200 and the barrier layer 102 is (100-300): (1-5).

In some embodiments, the ashing process may be implemented using a plasma generator. Removing the mask layer using an ashing process includes: providing a plasma atmosphere for the second mask layer 200, wherein the plasma atmosphere comprises at least one of oxygen plasma, hydrogen plasma or chlorine-containing gas plasma, and the second mask layer 200 is removed through the reaction of active ions in the plasma atmosphere and the second mask layer 200 and the bombardment of the second mask layer 200 by the plasma.

In some embodiments, the second mask layer 200 is removed by using a photoresist remover, and the etching rate ratio of the photoresist remover to the second mask layer 200 and the barrier layer 102 is (100-300): (1-5), so that the second mask layer 200 is removed by using the photoresist remover, the etching rate of the photoresist remover to the barrier layer 102 is slower, and the probability of the barrier layer 102 being etched through is small, so that the photoresist remover can be blocked by the barrier layer 102 and cannot enter the first cavity 104.

In some other embodiments, the ashing process and the photoresist stripping process may be combined to achieve a better mask layer removal.

In some other embodiments, in addition to the wet photoresist removing process of using a photoresist removing solution (e.g., a mixed acid solution) to soak the second mask layer 200 for a long time to dissolve and remove the second mask layer 200, the second mask layer 200 may be removed using other wet photoresist removing processes. For example, DHF (HF, H) ₂ O ₂ 、H ₂ O mixture) solution, and then performing a short time treatment of about 10s for about 1min for about the second mask layer 200descum) and finally performing a photoresist stripping treatment for about 60 minutes.

In these embodiments, since new gas or liquid is introduced when cleaning the second mask layer 200, the blocking layer 102 prevents the first cavity 104 from penetrating the initial trench 106, so as to avoid introducing new gas or liquid into the first cavity 104, and also prevent particles generated during cleaning the second mask layer 200 from falling into the first cavity 104.

When the first wafer 101 and the barrier layer 102 are etched to form the trench 107, the etching parameters used are etching parameters for etching silicon, however, since the first wafer 101 is a silicon-containing wafer, a silicon polymer is easily generated during the etching process. Therefore, after the wet photoresist removal, the wet etching process is continued on the bottom of the initial trench 106, so as to remove the polymer residue on the sidewall of the initial trench 106. The parameters and the solution of the wet etching treatment can be the same as those of wet photoresist removal, or different parameters and solutions can be adopted.

The wet etching treatment process at least comprises the following steps: the semiconductor substrate is treated with a DHF solution, which is flowed into the initial trench 106 and the polymer residue is removed. The treatment of the semiconductor substrate with the DHF solution includes two forms, the first form is a single-chip rotary spray DHF solution treatment form, and the treatment time is 10-60 minutes; the second is a groove type soaking treatment mode, and the soaking time is 30-120 minutes.

In the wet etching process, the barrier layer 102 is disposed at the bottom of the initial trench 106, so that the wet etching is easy to be difficult to enter the first cavity 104, and does not adversely affect the first cavity 104, thereby improving the performance of the first cavity 104.

Referring to fig. 10, after wet etching, the barrier layer 102 is etched with the initial trench 106 as a mask, and the trench 107 is formed by penetrating the barrier layer 102 until the first cavity 104 is exposed.

The trench 107 is located above the first cavity 104 and is in communication with the first cavity 104, and the portion of the first wafer 101 separated by the trench 107 is formed as a floating structure or an interdigital structure of the functional layer.

In some embodiments, the trench 107 may be applied in a semiconductor kinetic energy sensor, such as a gyroscopic MEMS sensor, or an angular velocity MEMS sensor, where the acceleration rate is typically measured and sensed using a plurality of thin sheets or interdigitated structures separated by the trench as a movable member.

In some embodiments, the MEMS sensor structure may be a gyroscopic MEMS sensor structure, where the first wafer 101 has a gyroscopic device structure formed therein, and an interdigital structure or a suspension structure is formed based on the grooves, including a plurality of comb teeth separated by grooves, for measuring a gyroscopic related kinetic parameter, and the suspension structure is used for providing support for a coriolis mass, or forming a spring structure.

In an embodiment, a plurality of comb teeth are formed in the exposed area of the lower surface of the boss 108, and the grooves 107 are located between each of the comb teeth, so as to separate each of the comb teeth, thereby forming an interdigital structure, herein referring to fig. 10, which may include a driving electrode, a detecting electrode, and a functional electrode, each of which is composed of a movable electrode and a fixed electrode.

In yet another embodiment, the grooves may also be used to form a floating structure that supports other devices, including a floating mass, a drive frame, or a spring structure. Except for anchor points and fixed electrodes in the whole structure of the gyroscope, the rest structures are suspended movable structures.

In this embodiment, the barrier layer 102 may act as a stop layer during formation of the interdigital structure, ensuring that the end topography of the interdigital structure is complete.

In some other embodiments, the MEMS sensor structure further comprises at least one of an angular velocity meter, an accelerometer, a flow meter, a magnetic MEMS sensor structure, a gas MEMS sensor structure. When the MEMS sensor structure is the angular velocity meter, the first wafer 101 is formed with an interdigital structure and/or a suspension structure based on the trench, and the specific shape of the interdigital structure and/or the suspension structure is matched with the specific requirement of the angular velocity meter.

In some embodiments, a hydrogen fluoride gas is used to remove the barrier layer 102 between the trench 107 and the first cavity 104. In these embodiments, the barrier layer 102 is at least one of a silicon oxide layer, a silicon nitride layer, or a TEOS layer, and the anisotropic dry etching method used in this case may etch the barrier layer 102 along the trench 107 without affecting the barrier layer 102 in areas other than the barrier layer 102 directly opposite the trench 106.

In some embodiments, the maximum dimension of the projection of the trench 107 on the first surface 1011 of the first wafer 101 is 5 microns. At this time, the material entering the first cavity 104 through the trench 107 is relatively difficult to exit through the trench 107, and thus other materials and the like are prevented from undesirably entering the first cavity 104 by the barrier layer 102 provided.

Referring to fig. 11, after the trench 107 is in communication with the first cavity 104, the remaining barrier layer 102 on top of the first cavity 104 is removed.

The barrier layer 102 remaining on top of the first cavity 104 is removed by an anisotropic dry etching process.

In some embodiments, when the residual barrier layer 102 on top of the first cavity 104 is removed directly by using the hydrogen fluoride gas, the removal effect is limited, and the barrier layer 102 located above the first cavity 104 but not below the trench 106 needs to be additionally planned at the design end.

In practice, the method employed in removing the barrier layer 102 may be determined based on the actual material structure of the barrier layer 102.

In some embodiments, the process of etching the barrier layer 102 and the process of removing the remaining barrier layer 102 on top of the first cavity 104 are combined, and the barrier layer 102 is removed by extending the etching time, or increasing the concentration of the hydrogen fluoride gas, etc., where the dry etching time is 2 minutes to 20 minutes, for example: 5 minutes, 8 minutes, 10 minutes, 13 minutes, 15 minutes, etc.

Referring to fig. 12, a third wafer 109 is provided, a control circuit 140 is provided in the third wafer 109, the boss 108 of the first wafer 101 and the third wafer 109 are bonded to form a second cavity 130, and the projections of the first cavity 104 and the second cavity 130 on the surface of the third wafer 109 are partially or completely overlapped.

A second interconnection layer 120 is formed on the surface of the third wafer 109, and the second interconnection layer 120 is electrically connected to the control circuit 140, so that the first wafer 101 and the third wafer 109 are bonded by bonding the first interconnection layer 105 and the second interconnection layer 120.

The second interconnect layer 120 may be a pad, and the materials of the second interconnect layer 120 include: aluminum, copper, gold, germanium or silver. In this embodiment, the material of the second interconnection layer is aluminum.

The third wafer 109 is also formed with pads (not shown) on its surface, which are electrically connected to the second interconnect layer 120 for connection to external circuitry.

A control circuit 140 may be formed in the third wafer 109, where the control circuit 140 includes functions of a driving circuit, a readout circuit, and the like, the control circuit 140 is formed by using corresponding electronic components formed by a CMOS manufacturing process and an isolation structure between adjacent electronic components, and the electronic components include at least one of a MOS transistor, a resistor, a diode, a capacitor, a memory, and the like, and the MOS transistor includes a gate structure and source and drain regions in a substrate located on both sides of the gate structure. Wherein the MOS transistor may include at least one of a PMOS transistor and an NMOS transistor; the isolation structures may be formed by a local field oxidation process or a Shallow Trench Isolation (STI) process; the interconnect layer is formed by BEOL process, and specifically includes an inter-metal dielectric (IMD) layer and a readout circuitry structure (not shown) located in the inter-metal dielectric layer, the readout circuitry structure being isolated by the inter-metal dielectric layer.

The readout circuit structure comprises a bottom contact plug in direct electrical contact with a corresponding terminal of the electronic element and a multi-layer metal interconnection structure in electrical connection with the bottom contact plug, wherein the multi-layer metal interconnection structure comprises a plurality of metal interconnection layers which are sequentially stacked, isolation is realized between adjacent metal interconnection layers through inter-metal dielectric layers, and electrical connection is realized in a local area through a conductive via (via) structure positioned in the inter-metal dielectric layers.

In some embodiments, after bonding the first wafer 101 to the third wafer 109, dicing is performed to form individual chips. In practice, the first wafer 101 may also be diced into individual chips before bonding the first wafer 101 to the third wafer 109, and then bonded to the third wafer 109.

In the embodiment shown in fig. 12, the first wafer 101 is electrically connected to a third wafer 109 through a metal sheet or a first interconnect layer 105 provided on the upper mesa, and the third wafer 109 may be a microcontroller, a single chip microcomputer, a programmable logic device, or the like.

According to the method for forming the MEMS sensor structure, the blocking layer 102 is arranged on the first surface 1011 of the first wafer 101, and the blocking layer 102 is at least distributed in the area of the first surface 1011 of the first wafer 101 corresponding to the first cavity 104, so that in the process of forming the initial groove 106 above the first wafer 101, the blocking layer 102 can be blocked between the first cavity 104 and the groove and used for blocking objects from entering the first cavity 104 in the etching process, thereby avoiding the problem that byproducts such as polymers and the like in the process of forming the initial groove 106 by etching the first wafer 101 and byproducts generated in the material or the process flow used in the follow-up process flow enter the first cavity 104, and improving the performance of the formed sensor.

The foregoing embodiments of the present application are not limited to the above embodiments, but are intended to be included within the scope of the present application as defined by the appended claims and their equivalents.

Claims (12)

1. A method of forming a MEMS sensor structure, comprising the steps of:

providing a first wafer for forming a functional layer of the MEMS sensor, the first wafer having opposite first and second surfaces;

forming a barrier layer on a first surface of the first wafer;

providing a cover wafer, wherein a first cavity is formed on the surface of the cover wafer;

bonding the capping wafer with a barrier layer to seal the first cavity;

performing first etching on the first wafer from the second surface to form a boss, wherein the boss comprises an upper table top and a lower table top;

performing second etching on the first wafer from the second surface, and forming an initial groove penetrating through the first wafer on a lower table top; etching a barrier layer at the bottom of the initial groove to form one or more grooves, wherein the grooves are positioned above the first cavity and communicated with the first cavity, and a first wafer part separated from the grooves is formed into a suspension structure and/or an interdigital structure of the functional layer;

and providing a third wafer, wherein a control circuit is arranged in the third wafer, bonding a boss of the first wafer and the third wafer to form a second cavity, and the projection parts or all of the first cavity and the second cavity on the surface of the third wafer are overlapped.

2. The method of forming a MEMS sensor structure of claim 1, wherein the trench is in communication with the first cavity, further comprising the steps of:

and removing the residual barrier layer at the top of the first cavity.

3. The method of forming a MEMS sensor structure according to claim 1 or 2, wherein the barrier layer is removed by an anisotropic dry etching process.

4. The method of forming a MEMS sensor structure of claim 1, wherein the method of forming the mesa comprises:

forming a first mask layer on the second surface of the first wafer;

patterning the first mask layer to partially expose a second surface of the first wafer;

and etching the exposed area on the second surface of the first wafer to a first depth along a direction perpendicular to the second surface of the first wafer to form a boss.

5. The method of forming a MEMS sensor structure of claim 1, wherein the second etching the first wafer from the second surface comprises: forming a patterned second mask layer on the surfaces of the upper table surface and the lower table surface of the boss so as to partially expose the lower table surface of the boss; and etching the first wafer and the barrier layer by taking the second mask layer as a mask so as to form the groove.

6. The method of claim 5, wherein etching the first wafer and the barrier layer to form the trench using the second mask layer as a mask comprises: etching the first wafer by taking the second mask layer as a mask to form an initial groove; then, removing the second mask layer, and performing wet etching to remove residues in the initial trench; and after wet etching, etching the barrier layer by taking the initial groove as a mask, and penetrating through the barrier layer until the first cavity is exposed so as to form the groove.

7. The method of forming a MEMS sensor structure of claim 6, wherein the material of the second mask layer comprises a photoresist layer, and the removing the second mask layer comprises:

removing the second mask layer by adopting an ashing process; and/or:

and removing the second mask layer by adopting a photoresist removing solution, wherein the etching rate ratio of the photoresist removing solution to the second mask layer and the barrier layer is (100-300) (1-5).

8. The method of forming a MEMS sensor structure of claim 1, after forming the mesa, prior to bonding the mesa of the first wafer to the third wafer, further comprising:

and forming a first interconnection layer on the surface of the upper table surface of the boss, wherein the first interconnection layer is electrically connected with the functional layer in the first wafer.

9. The method of claim 8, wherein the third wafer has a second interconnect layer formed on a surface thereof, the second interconnect layer being electrically connected to the control circuit, bonding the first interconnect layer to the second interconnect layer to bond the first wafer to the third wafer.

10. The method of claim 1, wherein the material of the barrier layer comprises at least one of silicon oxide, silicon nitride, and TEOS.

11. The method of forming a MEMS sensor structure of claim 1, wherein the barrier layer has a thickness of 0.3 microns to 3 microns.

12. The method of forming a MEMS sensor structure of claim 1, wherein the MEMS sensor structure comprises at least one of a gyroscope MEMS sensor structure, an angular velocity meter, an accelerometer, a flow meter, a magnetic MEMS sensor structure, a gas MEMS sensor structure.