JP2013206991A - Semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device manufacturing method which can planarize an inner wall of a vertical hole even when the vertical hole is formed by deeply digging a silicon substrate.SOLUTION: A semiconductor device manufacturing method according to a present embodiment comprises: a first process of forming a vertical hole in a silicon substrate by alternately and repeatedly performing a process of plasma etching a silicon substrate and a process of depositing a protection film on an inner wall of the etched part; and a second process of etching an inner wall of the vertical hole by reactive ion etching using an etching gas containing a Fgas.

Description

  The present invention relates to a method for manufacturing a semiconductor device having vertical holes called trenches or vias.

  A semiconductor device has electronic elements such as transistors, diodes, resistors, and capacitors formed on a semiconductor substrate. From a single electronic element to an integrated circuit (LSI) in which a large number of electronic elements are collectively formed. Various semiconductor devices are provided. Particularly in recent years, development of a three-dimensional mounting LSI in which two-dimensional LSI chips are stacked in the vertical direction has been advanced in order to reduce the size, multifunction, and speed of semiconductor devices.

  One of the key technologies for developing a three-dimensional mounting LSI is a mounting technology for electrically connecting stacked LSI chips. Conventionally, electrical connection between LSI chips has been performed by wire bonding using fine metal wires. On the other hand, in recent years, a mounting technology (hereinafter referred to as TSV technology) using a through-silicon via (TSV) has been proposed and is being developed.

  In the TSV technology, LSI chips are stacked, and circuit connections between LSI chips are made using silicon through electrodes (TSV) that are vertical wirings penetrating the LSI chips. This is a mounting technology, and it is expected that a multi-function LSI can be realized by mounting a plurality of different LSI chips and MEMS (Micro Electro Mechanical Systems) together.

  The process of realizing the TSV technology includes a process of forming a TSV on a silicon substrate on which an LSI chip is formed, and a process of bonding the LSI chip and connecting electric wiring in the LSI chip via the TSV. In the step of forming a TSV on a silicon substrate, a vertical hole structure called a trench or a via is formed on the silicon substrate, an insulating film that avoids interference between the silicon substrate and the TSV is formed on the inner wall, and then a conductor is filled.

  In forming trenches and vias in a silicon substrate, it is necessary to etch the silicon substrate to a depth on the order of several μm to several hundred μm. Etching methods for forming trenches and vias include wet etching processes using highly reactive chemicals such as TMAH (tetramethylammonium hydroxide) and KOH (potassium hydroxide), and ionizing gas with plasma. The dry etching process is roughly divided into radicals and etching.

  The wet etching process has a high throughput because batch processing for etching many wafers or chips at a time is possible. However, since the etching direction depends on the crystal orientation of silicon, there is a drawback that it is difficult to miniaturize the element. For example, it is known that when a silicon substrate having a surface crystal orientation of <100> is wet-etched with TMAH, the inner walls of trenches and vias are forward tapered with an angle of about 55 °. When the inner wall of the trench or via becomes tapered, the interval cannot be reduced, resulting in a problem that the LSI cannot be miniaturized or miniaturized.

  On the other hand, the dry etching process is a single wafer process for etching wafers one by one, but etching can be performed with little dependence on the crystal orientation of silicon. Further, in the dry etching process, by appropriately setting processing conditions, the shape of the inner wall of the trench or via can be freely changed, such as forward taper, reverse taper, or vertical.

  As a main method of forming trenches and vias by such a dry etching process, there is a reactive ion etching (RIE) process using inductively coupled plasma (ICP). In particular, there is a method called a Bosch process as a method for deeply digging a silicon substrate.

  The reactive ion etching process is a method of performing etching with ions and radicals, and is suitable for anisotropic etching and fine processing. Among them, the Bosch process is a plasma etching process in which holes are formed using an etching gas such as SF6 gas, and a plasma in which a fluorocarbon polymer is deposited as a protective film on the inner wall surface of the holes using a deposition gas such as C4F8 gas. This is a method of digging holes by a process of alternating deposition steps (alternating process), and is suitable for forming trenches and vias with a depth of about several hundreds of μm.

JP 2007-311584 A International Publication No. 2008/75715

  In the Bosch process, anisotropic etching of silicon is performed in a pseudo manner by repeating a process in which a protective film is deposited, a bottom protective film is removed, and an isotropic etching is performed in one cycle. For this reason, minute irregularities called scallops are formed on the inner walls of the trenches and vias. Since scallops formed on the inner walls of trenches and vias cause electric field concentration, the reliability of the semiconductor device is lowered. In addition, when silicon or metal is buried in trenches or vias formed using the Bosch process using CVD or the like, the scallop edge serves as the nucleus, and the film grows locally, so uniform film growth is possible. I can't hope.

  On the other hand, in reactive ion etching processes that are not alternating processes, scallops are not formed on the inner walls of trenches and vias, but when resist is used as a mask, the selectivity to the mask material cannot be increased, so several tens of μm Etching to form trenches and vias having the above depth is difficult.

  An object of the present invention is to provide a method of manufacturing a semiconductor device capable of flattening an inner wall of a vertical hole even when a vertical hole is formed by deeply digging a silicon substrate.

The present invention made to solve the above problems is a method for manufacturing a semiconductor device, wherein a vertical hole structure or a column structure is formed in a silicon substrate by a reactive ion etching process using an etching gas,
a) a first step of forming the vertical hole structure or the column structure in the silicon substrate by alternately repeating a step of plasma etching the silicon substrate and a step of depositing a protective film on the sidewall of the etched portion;
and b) a second step of flattening the side wall of the vertical hole structure or the columnar structure by etching using the etching gas containing F ₂ gas.
The first step described above is a so-called Bosch process, which is a process of digging a silicon substrate by an alternating process. In the case where the vertical hole structure is formed in the step of plasma etching the silicon substrate in the first step, a protective film is deposited on the inner sidewall of the vertical hole structure. Further, when forming a column structure, a protective film is deposited on the outer side wall of the column structure. That is, in any case, a protective film is deposited on the side wall of the etched portion.

In the above manufacturing method, the etching gas used in the second step is preferably F ₂ gas diluted with a rare gas, and particularly preferably F ₂ gas diluted with He gas.

  The method for manufacturing a semiconductor device according to the present invention combines both a Bosch process for digging a substrate by an alternating process and a reactive ion etching process that is not an alternating process, thereby enabling deep digging of a silicon substrate. The side wall of the vertical hole structure or the column structure formed in the silicon substrate can be flattened while being realized.

FIG. 6 is a process diagram of a first process of a method for manufacturing a semiconductor device according to an embodiment of the present invention. The schematic sectional drawing of the trench or via | veer obtained by the 1st process. The figure explaining a mode that a scallop is shaved at the 2nd process. The schematic sectional drawing of the trench or via | veer obtained by the 2nd process. The image which shows the structure of the trench obtained at the 1st process. The image which shows the structure of the trench of the specific example 1 of a 2nd process. The image which shows the structure of the trench of the specific example 2 of a 2nd process. The image which shows the structure of the trench of the specific example 3 of a 2nd process. The image which shows the structure of the trench of the specific example 4 of a 2nd process.

Hereinafter, embodiments of a method for manufacturing a semiconductor device according to the present invention will be described with reference to the drawings. In the following, an example in which trenches or vias having a vertical hole structure are formed in a silicon substrate by digging the silicon substrate will be described, but the present invention can also be applied to a method of forming a column structure in a silicon substrate.
The manufacturing method of the semiconductor device of this embodiment is roughly divided into a first step of forming a trench or a via in a silicon substrate and a second step of flattening the inner wall of the trench or via formed in the silicon substrate.

FIG. 1 is a process diagram of the first process. The first step consists of a dry etching process called a Bosch process. In the first step, the silicon substrate 102 having the patterned mask 101 is isotropically etched with an etching gas. Thereby, the part exposed from the mask 101 is etched (FIG. 1A).
Next, a protective film 103 is formed on the etched portion (FIG. 1B).
Subsequently, only the protective film 103 on the bottom surface of the etched portion is etched, and the silicon substrate 102 in that portion is exposed in the etching gas (FIG. 1C).
Thereafter, the silicon substrate 102 is isotropically etched again (FIG. 1D). Thereby, the vertical hole 100 is formed in the silicon substrate 102.

In the first step, the vertical hole 100 is gradually deepened by repeating the process shown in FIG. 1B to FIG. 1D for a plurality of cycles, so that the trenches and vias are formed in the silicon substrate. It is formed. FIG. 2 shows a schematic cross-sectional view of the trench or via formed in the first step (Bosch process).
In the first step, the anisotropic etching of silicon is performed in a pseudo manner by repeating the process of depositing the protective film, removing the protective film on the bottom surface, and isotropic etching for a plurality of periods. Small irregularities called scallops 202 are formed on the inner walls of the trenches and vias.

  FIG. 3 is a process diagram of the second process. In the second step, etching using an etching gas containing fluorine gas is performed using a reactive ion etching process using inductively coupled plasma, which is not an alternating process.

In a reactive ion etching apparatus using inductively coupled plasma, plasma can be formed at a low pressure. At a low pressure, the mean free path of etching molecules becomes long, so that etching gas molecules can reach the back of the fine pattern, and anisotropic etching of the silicon substrate 102 with respect to the opening diameter of the mask 101 becomes possible. For this reason, the scallops on the sidewalls of the trenches and vias are scraped off, and a silicon substrate 102 having trenches or vias without scallops as shown in FIG. 4 is obtained. Further, the corners of the opening 401 and the bottom 402 of the trench and via are rounded. In addition, the manufacturing method according to the present embodiment can round the corners of the trench or via opening 401 or scrape the scallop, so that the manufactured device can be prevented from being destroyed by electric field concentration. In addition, an insulating film can be uniformly formed on the inner wall of the vertical hole structure formed in the silicon substrate, or metal can be uniformly embedded.
As described above, the manufacturing method according to the present embodiment is characterized in that etching is performed by combining a Bosch process and a reactive ion etching process that is not an alternating process.

  In the manufacturing method according to the present embodiment, the material of the etching mask is not limited as long as it is only for removing scallops of trenches and vias. On the other hand, in addition to removing the scallop, in order to round the corner of the opening 401 of the trench or via, it is resistant in the Bosch process and is reactive ion etching using inductively coupled plasma. It is necessary to use a mask material having such resistance and thickness that the mask is removed by etching in the process. An example of such a mask material is a resist mask. Next, specific examples will be described.

[Preparation of resist mask]
As a substrate, a 2 cm square silicon substrate having a thickness of 525 μm was prepared. Application of the resist (trade name: Sumiresist PFI-38, manufactured by Sumitomo Chemical Co., Ltd.) was performed using a spin coater at 3200 rpm for 20 sec. Thereafter, prebaking was performed at 90 ° C. for 60 seconds, and exposure was performed using a line and space pattern reticle (photomask) with a stepper at 2300 J / m ² and 0.2 μm. Next, post exposure bake (PEB) is performed at 110 ° C. for 60 seconds, and development is performed for 60 seconds using NMD-W (2.38% tetramethylammonium hydroxide, manufactured by Tokyo Ohka Kogyo Co., Ltd.). Rinse with water for 2 min. Then, 120 degreeC and 5 minute post-baking were performed.

[Production of trench]
Etching by a Bosch process using a reactive ion etching apparatus (product name: RIE-800iPB, manufactured by Samco Co., Ltd.) using inductively coupled plasma to the silicon substrate on which the resist mask is formed. (1) Protective film A total of 80 cycles were performed as one cycle of three steps of deposition of (2) removal of the bottom protective film and (3) etching. The conditions for each step are as follows.
(1) Deposition of protective film ICP = 600W, BIAS = 10W, APC = 100%, C4F8 = 50 sccm, O2 = 5 sccm, Ar = 100 sccm
(2) Removal of bottom protective film ICP = 600 W, BIAS = 100 W, APC = 100%, SF6 = 100 sccm, O 2 = 5 sccm, Ar = 100 sccm
(3) Etching ICP = 600 W, BIAS = 100 W, APC = 100%, SF6 = 100 sccm, O 2 = 5 sccm, Ar = 100 sccm

  The trench structure obtained under the above conditions is shown in FIG.

Next, a second process using fluorine gas is performed with a reactive ion etching apparatus (product name: RIE-101iPH, manufactured by Samco Corporation) using inductively coupled plasma in the trench obtained by the Bosch process. Went for a minute. Specific examples 1 to 4 are shown below.
(Specific example 1)
The process conditions for the second step are as follows.
ICP = 100 W, BIAS = 100 W, Process Pressure = 0.5 Pa, F ₂ / He = 20 sccm.
The above F ₂ / He (etching gas) is a gas in which He and F ₂ are mixed at a ratio of 9: 1. The following specific examples 2 to 4 are the same.
The structure of the trench obtained under the above conditions is shown in FIG.

  From the comparison between FIG. 5 and FIG. 6, scallops (unevenness on the inner wall) that are often seen near the opening of the trench formed by the Bosch process are reduced by the reactive ion etching process of the second step, and the trench It can be seen that the tip shape of the opening is rounded.

(Specific example 2)
The process conditions for the second step are as follows.
ICP = 200 W, BIAS = 100 W, Process Pressure = 0.5 Pa, F ₂ / He = 20 sccm.
The trench structure obtained under the above conditions is shown in FIG.

From FIG. 5 to FIG. 7, it can be seen that in this second specific example, the scallop that was often seen near the opening of the trench formed by the Bosch process was reduced.
On the other hand, the opening of the trench had a mountain shape without roundness. In addition, the rounded shape disappeared at the bottom of the trench during the Bosch process and changed to a polygonal shape.
From the above, the depth and opening diameter of the trench after the reactive ion etching process are not significantly different from those in the case of the specific example 1, but the opening is made by slightly changing the process conditions of the reactive ion etching. It can be seen that the tip shape and bottom shape of the part can be controlled.

(Specific example 3)
The process conditions for the second step are as follows.
ICP = 100 W, BIAS = 100 W, Process Pressure = 4.0 Pa, F ₂ / He = 20 sccm.
The structure of the trench obtained under the above conditions is shown in FIG.

  From comparison between FIG. 6 and FIG. 7 and FIG. 8, it is understood that the etching depth and the opening diameter are increased by increasing Process Pressure. Moreover, it can confirm that the shape of an opening part is an acute angle mountain shape without roundness. In addition, like the specific example 2, the shape of the bottom of the trench has changed to a polygonal shape. That is, with respect to the shape of the bottom of the trench, the same phenomenon was obtained in Specific Example 2 in which ICP power was increased and Specific Example 3 in which Process Pressure was increased.

(Specific example 4)
The process conditions for the second step are as follows.
Etching was performed for 20 min under the conditions of ICP = 100 W, BIAS = 100 W, Process Pressure = 0.5 Pa, F ₂ / He = 19 sccm, and O ₂ = 1 sccm.
The structure of the trench obtained under the above conditions is shown in FIG.
From this, it can be seen that the etching depth dimension and the opening diameter are slightly increased. In addition, the etching shape is not significantly different from that at the end of the Bosch process at the bottom, but it can be confirmed that the opening is rounded and slightly rounded.

  As described above, according to the method of manufacturing a semiconductor device according to the present embodiment, the silicon substrate is deeply dug in the first step to form trenches and vias. At this time, the scallops formed on the inner walls of the trenches and vias are Since it can be scraped off in the process, a semiconductor device having trenches and vias with flat inner walls can be manufactured.

  In addition, this invention is not limited to an above-described Example. For example, in each of the above-described embodiments, various specific numerical values such as etching conditions, trench depth dimensions, opening diameters, and the like are listed, but all are not limited to the above numerical values, and can be freely selected according to the purpose Is possible.

100 ... Vertical hole 102 ... Silicon substrate 103 ... Protective film 202 ... Scallop

Claims (3)

In a method for manufacturing a semiconductor device, a vertical hole structure or a column structure is formed in a silicon substrate by a reactive ion etching process using an etching gas.
a) a first step of forming the vertical hole structure or the column structure in the silicon substrate by alternately repeating a step of plasma etching the silicon substrate and a step of depositing a protective film on the sidewall of the etched portion;
and b) a second step of flattening the side wall of the vertical hole structure or the columnar structure using an etching gas containing F ₂ gas to flatten the side wall. The method for manufacturing a semiconductor device according to claim 1, wherein the etching gas used in the second step is F ₂ gas diluted with a rare gas.   The method of manufacturing a semiconductor device according to claim 2, wherein the rare gas is He gas.