TWI780985B - Semiconductor structure and manufacturing method of the same - Google Patents

Abstract

A semiconductor structure and manufacturing method thereof are provided. The semiconductor structure includes a first substrate, a stack structure and at least one conductive connector. The stack structure is disposed on the first substrate. The stack structure includes a plurality of insulating layers and a plurality of conductive layers which is alternatively stacked with the plurality of insulating layers. The conductive layers have at least one dummy structure. The at least one conductive connector penetrates the first substrate and the plurality of insulating layers and the plurality of conductive layers in the stack structure. One end of the conductive connector is in contact with the dummy structure. A sidewall of the conductive connector has a concave-convex shape. The concave portions of the sidewall of the conductive connector correspond to the plurality of conductive layers. The convex portions of the sidewall of the conductive connector correspond to the plurality of insulating layers.

Description

Semiconductor structure and manufacturing method thereof

The present invention relates to a semiconductor technology, and in particular to a semiconductor structure and a manufacturing method thereof.

In general, three-dimensional integrated circuits (3D ICs) need to be electrically connected through through silicon vias (TSVs). TSVs can be divided into via first and midway drilling according to the manufacturing timing. via middle, via last or via after bonding process. TSVs are usually formed by plasma etching. However, during the plasma etching process, the exposed conductive layer tends to accumulate a large amount of charges on its surface and generate a large electric field, causing the antenna effect. This in turn leads to damage to the three-dimensional integrated circuit. For example, the gate oxide layer in the three-dimensional integrated circuit is broken down, which reduces the reliability of the three-dimensional integrated circuit. The via after bonding process is significantly damaged by plasma etching.

The invention provides a semiconductor structure with better reliability.

The invention provides a method for manufacturing a semiconductor structure, which can reduce the damage caused by plasma etching, and further improve the reliability of the semiconductor structure.

The semiconductor structure of the present invention includes a first substrate, a stack structure and at least one conductive connector. The stack structure is disposed on the first substrate, and includes a plurality of insulating layers and a plurality of conductive layers stacked alternately with the insulating layers. At least one of the plurality of conductive layers has a dummy structure. At least one conductive connection part runs through the first substrate and the plurality of insulating layers and the plurality of conductive layers in the stacked structure, and one end of the conductive connection part is in contact with the dummy structure. The sidewall of the conductive connector has a concave-convex shape, the recesses of the sidewall of the conductive connector correspond to the sidewalls of the plurality of conductive layers, and the protrusions of the sidewall of the conductive connector correspond to the sidewalls of the plurality of insulating layers.

In an embodiment of the present invention, the above-mentioned semiconductor structure further includes a second substrate disposed on a surface of the stack structure opposite to the first substrate.

In an embodiment of the present invention, the aforementioned dummy structure is floating.

In an embodiment of the present invention, the above-mentioned first substrate includes a first isolation structure, and the conductive connecting member penetrates through the first isolation structure.

In an embodiment of the present invention, the above-mentioned plurality of conductive layers include a plurality of openings, the positions of the plurality of openings correspond to each other, and the conductive connectors are disposed in the plurality of openings, wherein the sidewalls of the conductive connectors are in contact with the plurality of openings side walls are in contact.

In an embodiment of the present invention, the plurality of openings have different widths, and the widths of the plurality of openings that are farther away from the first substrate are smaller.

In an embodiment of the present invention, each of the above-mentioned openings includes circular openings, rectangular openings or groove-shaped openings.

In an embodiment of the present invention, more than two of the plurality of conductive layers have dummy structures.

A method for manufacturing a semiconductor structure of the present invention includes the following steps. A first three-dimensional semiconductor element is provided, and the first three-dimensional semiconductor element includes a first substrate and a first stack structure. The first stack structure is disposed on the first substrate, wherein the first stack structure includes a plurality of first insulating layers and a plurality of first conductive layers stacked alternately, and the plurality of first conductive layers has a plurality of first openings. A second three-dimensional semiconductor element is provided, and the second three-dimensional semiconductor element includes a second substrate and a second stack structure. The second stack structure is disposed on the second substrate, wherein the second stack structure includes a plurality of second insulating layers and a plurality of second conductive layers alternately stacked, wherein at least one of the plurality of second conductive layers has a dummy structure, and more The second conductive layer has a plurality of second openings. Afterwards, bonding the first three-dimensional semiconductor element and the second three-dimensional semiconductor element, wherein the positions of the plurality of second openings and the plurality of first openings are aligned with each other. Then, using the dummy structure as a stop layer, plasma etching is performed to form through the first substrate, a plurality of first insulating layers, a plurality of first openings, a plurality of a second insulating layer and a plurality of first through holes with second openings. Then, wet etching is performed to remove the first substrate, the plurality of first insulating layers and the plurality of second insulating layers in the first through hole until part of the plurality of first conductive layers and part of the plurality of second conductive layers are exposed , to form a second via. Then, a conductive connection member is formed in the second through hole to be electrically connected with the plurality of first conductive layers and the plurality of second conductive layers.

In yet another embodiment of the present invention, the step of performing the above wet etching includes over-etching a plurality of first insulating layers and a plurality of second insulating layers, so that the maximum width of the second via hole is greater than that of the plurality of first openings and the maximum width of the plurality of second openings.

In yet another embodiment of the present invention, the shape of the above-mentioned first through hole and the shape of the above-mentioned second through hole are columnar or tapered, respectively.

In yet another embodiment of the present invention, in the first three-dimensional semiconductor element, the widths of the plurality of first openings that are farther away from the first substrate are smaller, and in the second three-dimensional semiconductor element, the widths of the plurality of first openings that are closer to the second substrate The width of the second opening is smaller. During bonding of the first three-dimensional semiconductor element and the second three-dimensional semiconductor element, the widths of the plurality of first openings and the widths of the plurality of second openings are arranged such that the widths of the plurality of openings become smaller as they are farther away from the first substrate.

In yet another embodiment of the present invention, the plurality of first conductive layers and the plurality of second conductive layers are not exposed during the formation of the above-mentioned first through holes.

In yet another embodiment of the present invention, the step of performing the wet etching includes using a first etchant to remove the first substrate in the first through hole, and using a second etchant to remove a plurality of first substrates in the first through hole. An insulating layer and a plurality of second insulating layers.

In yet another embodiment of the present invention, before forming the conductive connection member in the second through hole, filling the second through hole with an organic planar layer, and the organic planar layer does not cover the sidewall of the first substrate. Afterwards, the part of the first substrate not covered by the organic planar layer is removed to form a third through hole, wherein the third through hole overlaps with the second through hole, and the width of the third through hole is larger than that of the second through hole. Then, a passivation layer is formed on the first substrate and the sidewall of the third through hole, and the surface of the organic planar layer is exposed. Then, the organic planar layer is removed to expose part of the dummy structure, part of the plurality of first conductive layers and part of the plurality of second conductive layers.

In yet another embodiment of the present invention, the step of forming the above-mentioned conductive connector in the second through hole includes conformally forming a barrier layer on the surface of the second through hole, and filling the second through hole with a conductive material Floor.

Another semiconductor structure manufacturing method of the present invention includes the following steps. A three-dimensional semiconductor element is provided on the carrier plate, and the three-dimensional semiconductor element includes a substrate and a stack structure. The substrate is set on the carrier board. The stack structure is disposed between the base plate and the carrier board. The stack structure includes a plurality of insulating layers and a plurality of conductive layers stacked alternately, wherein at least one of the plurality of conductive layers has a dummy structure, and the plurality of conductive layers has a plurality of openings. Then, using the dummy structure as a stop layer, plasma etching is performed to form first through holes penetrating the substrate, multiple insulating layers and multiple openings in the substrate and the stacked structure. Afterwards, wet etching is performed to remove the substrate and the plurality of insulating layers in the first through hole until a part of the plurality of conductive layers is exposed, so as to form the second through hole. Then, a conductive connection member is formed in the second through hole to be electrically connected with the plurality of conductive layers.

In another embodiment of the present invention, the step of performing the above wet etching includes over-etching the plurality of insulating layers, so that the maximum width of the second through hole is greater than the maximum width of the plurality of openings.

In another embodiment of the present invention, the shape of the above-mentioned first through hole and the shape of the above-mentioned second through hole are columnar or tapered, respectively.

In another embodiment of the present invention, in the above-mentioned three-dimensional semiconductor element, the widths of the plurality of openings are smaller the farther away from the substrate.

In another embodiment of the present invention, the plurality of conductive layers are not exposed during the formation of the first through hole.

In another embodiment of the present invention, the step of performing the wet etching includes removing the substrate in the first through hole with a first etchant, and removing a plurality of insulating layers in the first through hole with a second etchant. Floor.

In another embodiment of the present invention, before forming the conductive connectors in the second through hole, filling the second through hole with an organic planar layer may be further included, and the organic planar layer does not cover the sidewall of the substrate. Afterwards, a portion of the substrate not covered by the organic planar layer is removed to form a third through hole, wherein the third through hole overlaps the second through hole, and the width of the third through hole is greater than that of the second through hole. Then, a passivation layer is formed on the substrate and the sidewall of the third through hole, and the surface of the organic planar layer is exposed. Then, the organic planar layer is removed to expose part of the dummy structure and part of the plurality of conductive layers.

Based on the above, the semiconductor structure of the present invention forms the conductive connection member in contact with the dummy structure through plasma etching and wet etching. Since only the dummy structure of the via hole is exposed during the plasma etching process, the conductive layer is exposed through wet etching, so that the sidewall of the subsequently formed conductive connector has a concave-convex shape, and the sidewall of the conductive connector has a concave-convex shape. The recesses correspond to the side walls of the conductive layer, and the protrusions of the side walls of the conductive connectors correspond to the side walls of the insulating layer. In this way, the antenna effect can be avoided, and the damage to the semiconductor structure caused by the strong electric field accumulated in the conductive layer in the process of forming the via hole by plasma etching can be reduced, thereby improving the reliability of the semiconductor structure.

The following examples are listed and described in detail with the accompanying drawings, but the provided examples are not intended to limit the scope of the present invention. In addition, the drawings are for illustrative purposes only and are not drawn to original scale. In order to facilitate understanding, the same elements in the following description will be described with the same symbols.

In addition, terms such as "comprising", "including", and "having" used in the text are all open terms, which means "including but not limited to".

It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, and/or or parts thereof shall not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a "first element," "component," "region," "layer," or "section" discussed below could be termed a second element, component, region, layer or section without departing from the teachings herein.

In addition, the directional terms mentioned in the text, such as "up" and "down", are only used to refer to the directions of the drawings, and are not used to limit the present invention.

1A to 1J are schematic partial cross-sectional views of a manufacturing process of a semiconductor structure according to a first embodiment of the present invention.

Referring to FIG. 1A , a first three-dimensional semiconductor device 110 and a second three-dimensional semiconductor device 120 are provided. The first three-dimensional semiconductor device 110 includes a first substrate 112 and a first stack structure S11. The first substrate 112 may be a silicon substrate, and the first substrate 112 may include active devices or passive devices (not shown), but the present invention is not limited thereto. The first stack structure S11 is disposed on the first substrate 112 and includes a plurality of first insulating layers 114 and a plurality of first conductive layers 116 stacked alternately. Although a whole first insulating layer 114 is shown in FIG. 1A , it should be known that the first insulating layer 114 is multi-layered and stacked alternately with multi-layered first conductive layers 116 . The material of the plurality of first insulating layers 114 can be, for example, silicon dioxide, organic polymer material or other suitable insulating materials. The material of the plurality of first conductive layers 116 can be a metal material (such as copper, aluminum or other suitable metal) for use as a subsequent interconnection or a polysilicon material for use as a gate or other semiconductor elements. The plurality of first conductive layers 116 has a plurality of first openings OP1.

In this embodiment, the plurality of first openings OP1 have the same width and are aligned with each other, but the invention is not limited thereto. In other embodiments, the plurality of first openings OP1 may have different widths, for example, the widths of the plurality of first openings OP1 that are farther away from the first substrate 112 may be smaller.

In some embodiments, the first stack structure S11 further includes a first dielectric layer 118 disposed on the surface of the plurality of first insulating layers 114 opposite to the first substrate 112, which can benefit the subsequent first three-dimensional semiconductor element 110 and Bonding of the second three-dimensional semiconductor element 120 .

In some embodiments, the first substrate 112 includes a first isolation structure ST1 to isolate active regions in the first substrate 112 .

The second three-dimensional semiconductor device 120 includes a second substrate 122 and a second stack structure S12. The second substrate 122 may be a silicon substrate, and the second substrate 122 may include active elements or passive elements (not shown), but the present invention is not limited thereto. The second stack structure S12 is disposed on the second substrate 122 and includes a plurality of second insulating layers 124 and a plurality of second conductive layers 126 stacked alternately. Although a whole second insulating layer 124 is shown in FIG. 1A , it should be known that the second insulating layer 124 is multi-layered and stacked alternately with the multi-layer second conductive layer 126 . The material of the plurality of second insulating layers 124 can be, for example, silicon dioxide, organic polymer material or other suitable insulating materials. The plurality of second conductive layers 126 has a second opening OP2 and at least one dummy structure DM1 . The material of the plurality of second conductive layers 126 can be a metal material (such as copper, aluminum or other suitable metal) for use as a subsequent interconnection or polysilicon material for use as a gate or other semiconductor elements. The dummy structure DM1 can be the same mold layer as one of the plurality of second conductive layers 126 . For example, in this embodiment, the dummy structure DM1 and the second layer M2 in the plurality of second conductive layers 126 are the same mold layer, but the present invention is not limited thereto, and the dummy structure DM1 can be arranged in an appropriate in the film layer.

In some embodiments, the dummy structure DM1 is floating, and is not electrically connected to other second conductive layers 126 (eg, the first layer M1 , the second layer M2 , the third layer M3 ).

In this embodiment, although only one second opening OP2 is shown, it is not intended to limit the present invention. The number of second openings OP2 can be multiple, which can be arranged in a manner similar to the arrangement of multiple first openings OP1. in the plurality of second conductive layers 126 . The plurality of second openings OP2 may have the same width and be aligned with each other, but the invention is not limited thereto. In other embodiments, the plurality of second openings OP2 may have different widths, for example, the width of the plurality of second openings OP2 closer to the second substrate 122 may be smaller.

In some embodiments, the second stack structure S12 further includes a second dielectric layer 128 disposed on the surface of the plurality of second insulating layers 124 opposite to the second substrate 122, which can benefit the subsequent first three-dimensional semiconductor device 110 and Bonding of the second three-dimensional semiconductor element 120 .

In some embodiments, the second substrate 122 includes a second isolation structure ST2 to isolate the active region in the second substrate 122 .

It should be understood that the number and arrangement of the plurality of first insulating layers 114, the plurality of first conductive layers 116, the plurality of second insulating layers 124 and the plurality of second conductive layers 126 can be adjusted according to actual needs, and the present invention does not limit. The numbers of the first opening OP1 and the second opening OP2 can also be adjusted according to actual needs, and the present invention is not limited thereto.

Referring to FIG. 1B , the first three-dimensional semiconductor device 110 and the second three-dimensional semiconductor device 120 are bonded, wherein the positions of the second opening OP2 and the plurality of first openings OP1 are aligned with each other. For example, the positions of the second opening OP2 and the plurality of first openings OP1 are aligned with each other, and the first three-dimensional semiconductor element 110 and the second three-dimensional semiconductor element 110 are connected to each other through the first dielectric layer 118 and the second dielectric layer 128. Element 120 engages.

In one embodiment, during the period 120 of bonding the first three-dimensional semiconductor element 110 and the second three-dimensional semiconductor element, the widths of the plurality of first openings OP1 and the width of the second openings OP2 are the ones that are farther away from the first substrate 112. Small way to configure.

Please continue to refer to FIG. 1B , the first substrate 112 is thinned. For example, the first substrate 112 is thinned by grinding or chemical mechanical planarization or wet etching, but the invention is not limited thereto. In other embodiments, the first substrate 112 may not be subjected to a thinning process.

Referring to FIG. 1C , the dummy structure DM1 is used as a stop layer to perform plasma etching to form a plurality of first insulating layers penetrating the first substrate 112 and the first stack structure S11 and the second stack structure S12. 114 , a plurality of first openings OP1 , a plurality of second insulating layers 124 , and a first via V1 of the second opening OP2 . For example, the mask layer 130 is formed on the first substrate 112 first, and the mask layer 130 has a mask opening 130a. Afterwards, plasma etching is performed with the mask layer 130 as a mask and the dummy structure DM1 as a stop layer to form a first via hole V1. The first via hole V1 runs through the first substrate 112, the plurality of first insulating layers 114, the plurality of first openings OP1, the first dielectric layer 118 (if any), the second dielectric layer 128 (if any), a plurality of The second insulating layer 124 and the second opening OP2 expose the dummy structure DM1 , but do not expose the plurality of first conductive layers 116 and the plurality of second conductive layers 126 . That is to say, the width W3 of the first through hole V1 is smaller than the width W1 of the first openings OP1 and the width W2 of the second openings OP2 . During the plasma etching process, only the dummy structure DM1 is exposed, and no other first conductive layer 116 or second conductive layer 126 is exposed, so the occurrence of the antenna effect can be reduced, and the connection between the first three-dimensional semiconductor element 110 and the second three-dimensional semiconductor element 110 can be reduced. The risk of damage to the semiconductor device 120 is reduced, thereby improving its reliability.

In some embodiments, the shape of the first through hole V1 may be columnar or tapered, and the present invention is not limited thereto. In some embodiments, the first via hole V1 may also penetrate through the first isolation structure ST1.

Referring to FIG. 1D , wet etching is performed to remove the first substrate 112 , the plurality of first insulating layers 114 and the plurality of second insulating layers 124 in the first through hole V1 until part of the plurality of first conductive layers 116 are exposed. and some of the plurality of second conductive layers 126 to form the second via hole V2. The wet etching method is, for example, wet dip etching, which can remove the first substrate 112, the plurality of first insulating layers 114, and the plurality of second insulating layers 124 in the first through hole V1 through multiple wet dips. , the first dielectric layer 118 (if any) and the second dielectric layer 128 (if any), until part of the plurality of first conductive layers 116 and part of the plurality of second conductive layers 126 are exposed. For example, wet wetting can be performed twice, first using the first etchant to remove part of the first substrate 112 in the first through hole V1, and then using the second etchant to remove part of the plurality of first substrates 112 in the first through hole V1. An insulating layer 114, a portion of a plurality of second insulating layers 124, a portion of the first dielectric layer 118 (if present), and a portion of the second dielectric layer 128 (if present). The first etchant may include tetramethylammonium hydroxide (TMAH), ammonia (NH ₄ OH) or other etchant used for wet etching silicon. The second etchant may include hydrofluoric acid (HF) or other etchant used for wet etching silicon oxide.

In some embodiments, the plurality of first insulating layers 114, the plurality of second insulating layers 124, the first dielectric layer 118 (if present), and the second dielectric layer 128 (if present) are over-etched by wet etching. In order to make the maximum width W4 of the second through hole V2 larger than the width W1 of the plurality of first openings OP1 (shown in FIG. 1C ) and the width W2 of the second opening OP2 (shown in FIG. 1C ). In other embodiments, if the plurality of first openings OP1 and the plurality of second openings OP2 have different widths, the maximum width W4 of the second through hole V2 may be larger than the maximum width W1 of the plurality of first openings OP1 and the plurality of second openings OP1. The maximum width W2 of the second opening OP2.

In some embodiments, the shape of the second through hole V2 may be columnar or tapered, and the present invention is not limited thereto.

Referring to FIG. 1E , the mask layer 130 is removed, and the organic planar layer 140 is filled in the second via hole V2 , and the organic planar layer 140 does not cover the sidewall of the first substrate 112 . The organic planar layer 140 can be, for example, organic resin, photoresist or other suitable materials, and the invention is not limited thereto. The organic planarization layer 140 does not cover the first substrate 112 exposed in the second via hole V2, that is, the top surface of the organic planarization layer 140 may be substantially aligned with the top surface of the first isolation structure ST1 or slightly lower than the top surface of the first isolation structure ST1. The top surface of structure ST1 is isolated. In other embodiments, if the first substrate 112 does not include the first isolation structure ST1, the top surface of the organic planarization layer 140 may be substantially aligned with the top surfaces of the plurality of first insulating layers 114 or slightly lower than the top surfaces of the plurality of first insulating layers 114 . The top surface of layer 114.

Referring to FIG. 1F , a portion of the first substrate 112 not covered by the organic planar layer 140 is removed to form a third via hole V3 . For example, isotropic etching or anisotropic etching can be used to remove part of the first substrate 112 to form the third via hole V3. The third through hole V3 overlaps with the second through hole V2, and the width W5 of the third through hole V3 is greater than the width W4 of the second through hole V2 (shown in FIG. 1D ).

Referring to FIG. 1G and FIG. 1H , a passivation layer 150 is formed on the first substrate 112 and on the sidewall of the third via hole V3 , and exposes the surface of the organic planar layer 140 . For example, as shown in FIG. 1G , the passivation material layer 150a may be conformally formed on the first substrate 112 and in the third via hole V3 by using a deposition method. In one embodiment, the thickness of the passivation material layer 150a on the first substrate 112 is greater than the thickness of the passivation material layer 150a in the third via hole V3 through adjustment of deposition process parameters. Afterwards, as shown in FIG. 1H, part of the passivation material layer 150a is removed to expose the surface of the organic planar layer 140, and then the passivation layer 150 is formed to protect the first substrate 112, and make the first substrate 112 and the subsequent formation of the third substrate 112 The conductive material in the via hole V3 or formed on the first substrate 112 is electrically isolated. The method of removing part of the passivation material layer 150a may, for example, remove the passivation material layer 150a in the third via hole V3 by etching back, but the invention is not limited thereto. In other embodiments, part of the passivation material layer 150a can also be removed by lithographic etching, for example, a photoresist layer (not shown) is formed on the passivation material layer 150a to expose part of the passivation material layer 150a in the third via hole V3. ), and use the photoresist layer as a mask to etch the exposed passivation material layer 150a until the surface of the organic planarization layer 140 is exposed to form the passivation layer 150, and then remove the photoresist layer.

Referring to FIG. 1I , the organic planar layer 140 in the second via hole V2 is removed to expose part of the dummy structure DM1 , part of the plurality of first conductive layers 116 and part of the plurality of second conductive layers 126 . The organic planar layer 140 can be removed by ashing process, etching process or other suitable process, the present invention is not limited thereto.

Referring to FIG. 1J , conductive connectors 160 a are formed in the second via holes V2 (shown in FIG. 1I ) to be electrically connected to the plurality of first conductive layers 116 and the plurality of second conductive layers 126 . For example, the barrier layer 162 can be conformally formed on the surface of the second via hole V2, and the conductive material layer 164 can be formed on the barrier layer 162, so as to form a plurality of first conductive layers 116 and a plurality of second conductive layers. The conductive connector 160 a electrically connects the conductive layer 126 . In this way, the first three-dimensional semiconductor device 110 can be electrically connected to the second three-dimensional semiconductor device 120 through the conductive connecting member 160a. The material of the barrier layer 162 can be, for example, tantalum, tantalum nitride, titanium, titanium nitride or other suitable materials, and the material of the conductive material layer 164 can be, for example, copper, tungsten or other suitable conductive materials, and the present invention is not limited thereto. . The barrier layer 162 and the conductive material layer 164 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), wherein preferably, chemical vapor deposition (CVD) or Atomic layer deposition (ALD) can make the barrier layer 162 completely cover the surface of the second via hole V2 with uneven sidewalls, but the invention is not limited thereto.

In some embodiments, the barrier layer 162 and the conductive material layer 164 can also extend to the surface of the passivation layer 150 to serve as an interconnection structure. In some other embodiments, the barrier layer 162 and the conductive material layer 164 above the passivation layer 150 may also be removed in conjunction with chemical mechanical planarization, and then the fabrication of related interconnection structures may be continued. The interconnection structure can be manufactured by existing manufacturing processes, and will not be repeated here.

In this embodiment, the second via hole V2 shown in FIG. 1D is formed through plasma etching and wet etching. During the plasma etching process, only the dummy structure DM1 is exposed, and then through wet etching. A plurality of first conductive layers 116 and a plurality of second conductive layers 126 are exposed to be electrically connected to the subsequently formed conductive connectors 160a, so that the first conductive layers 116 and the second conductive layers 126 will not be subjected to long-term The plasma bombardment can avoid the antenna effect, reduce the damage of the semiconductor element caused by the strong electric field accumulated in the conductive layer in the process of forming the via hole by plasma etching, and improve the reliability of the semiconductor element.

After the above process, the fabrication of the semiconductor structure 100A of this embodiment can be substantially completed.

Therefore, the semiconductor structure 100A of FIG. 1J basically includes the first substrate 112 , the stack structure S1 and the conductive connector 160 a. The stack structure S1 is disposed on the first substrate 112 and includes a plurality of insulating layers DL and a plurality of conductive layers ML alternately stacked with the plurality of insulating layers DL. The plurality of insulating layers DL includes a plurality of first insulating layers 114 , a first dielectric layer 118 , a second dielectric layer 128 and a plurality of second insulating layers 124 . The multiple conductive layers ML include multiple first conductive layers 116 and multiple second conductive layers 126, wherein the multiple second conductive layers 126 have a dummy structure DM1, that is, at least one of the multiple conductive layers ML has Dummy structure DM1. The conductive connection part 160a penetrates through the first substrate 112 and the plurality of insulating layers DL and the plurality of conductive layers ML in the stack structure S1, and one end of the conductive connection part 160a is in contact with the dummy structure DM1. The sidewall of the conductive connector 160a has a concave-convex shape, the recesses SW1 of the sidewall of the conductive connector 160a may correspond to the sidewalls of the plurality of conductive layers ML, and the protrusions SW2 of the sidewall of the conductive connector 160a may correspond to the plurality of insulating layers DL. side wall.

In this embodiment, the shape of the conductive connecting member 160a is columnar, but the present invention is not limited thereto. In other embodiments, the shape of the conductive connecting member 160a may be tapered.

In one embodiment, the conductive layers ML include a plurality of openings OP, for example, a first opening OP1 and a second opening OP2 . The positions of the plurality of openings OP correspond to each other, and the conductive connectors 160a are disposed in the plurality of openings OP, wherein the sidewalls of the conductive connectors 160a are in contact with the sidewalls of the plurality of openings OP.

FIG. 2A is a schematic partial top view of the conductive layer ML in FIG. 1J . FIG. 2B is another partial top view of the conductive layer ML in FIG. 1J . FIG. 2C is another partial top view of the conductive layer ML in FIG. 1J . For clarity, FIG. 2A to FIG. 2C only show the conductive layer and its openings, so as to show the relationship between the conductive layer and its openings.

Referring to FIG. 1J and FIGS. 2A to 2C , each opening OP can be formed in a continuous conductive layer ML or formed by a discontinuous conductive layer ML. For example, as shown in FIGS. 2A and 2B , the opening OP may include a circular opening or a rectangular opening formed in the continuous conductive layer ML. Since the contact area between the continuous conductive layer ML and the conductive connecting member 160a is larger, the resistance can be reduced. In other embodiments, as shown in FIG. 2C , the opening OP can be formed by a discontinuous conductive layer ML, for example, the opening OP is a groove-like groove formed by the interval between the first part P1 and the second part P2 of the conductive layer ML. Opening, wherein the first part P1 is not in contact with the second part P2.

In one embodiment, the semiconductor structure 100A further includes a second substrate 122 disposed on the surface of the stack structure S1 opposite to the first substrate 112 . That is to say, the stack structure S1 is located between the first substrate 112 and the second substrate 122 .

In one embodiment, the first substrate 112 and the second substrate 122 may respectively include a first isolation structure ST1 and a second isolation structure ST2. The conductive connection member 160a may penetrate through the first isolation structure ST1.

In one embodiment, the dummy structure DM1 is floating.

Since the semiconductor structure 100A has a conductive connection piece 160a in contact with the dummy structure DM1, and the sidewall of the conductive connection piece 160a has a concave-convex shape, the recess SW1 of the sidewall of the conductive connection piece 160a can correspond to the sidewalls of a plurality of conductive layers ML, and the conductive connection The protrusion SW2 of the sidewall of the component 160a may correspond to the sidewalls of a plurality of insulating layers DL, which may have better reliability.

3 is a schematic partial cross-sectional view of a semiconductor structure according to a second embodiment of the present invention. The schematic cross-sectional view of FIG. 3 is roughly similar to the schematic cross-sectional view of FIG. 1J , so the same components recorded in the second embodiment and the first embodiment can refer to the above-mentioned related content, so the same configurations in the first and second embodiments, in This will not be repeated here.

In FIG. 3, the semiconductor structure 100A' of this embodiment is different from the first embodiment in that the conductive connector 160a' of the semiconductor structure 100A' is tapered, and the multiple openings OP of the multiple conductive layers ML have different The width of the plurality of openings OP is smaller the farther away from the first substrate 112 . Since the semiconductor structure 100A' has a conductive connector 160a' in contact with the dummy structure DM1, and the sidewall of the conductive connector 160a' has a concave-convex shape, the recess SW1' of the sidewall of the conductive connector 160a' may correspond to a plurality of conductive layers ML The sidewalls of the conductive connector 160a' may correspond to the sidewalls of a plurality of insulating layers DL, which may have better reliability.

FIG. 4 is a schematic partial cross-sectional view of a semiconductor structure according to a third embodiment of the present invention. The schematic cross-sectional view of FIG. 4 is roughly similar to the schematic cross-sectional view of FIG. 1J , so the same components recorded in the third embodiment and the first embodiment can refer to the above-mentioned related content, so the same configurations in the first and third embodiments, in This will not be repeated here.

In FIG. 4, the semiconductor structure 100B of this embodiment is different from the first embodiment in that the semiconductor structure 100B includes two conductive connectors 160a, 160b, and there are two dummy structures DM1, DM1, DM2 corresponds to the conductive connectors 160a, 160b, respectively. That is to say, the conductive connectors 160a, 160b penetrate through the first substrate 112 and the plurality of insulating layers DL and the plurality of conductive layers ML in the stack structure S1 respectively, and one end of the conductive connector 160a is in contact with the dummy structure DM1, and the conductive connectors One end of 160b is in contact with the dummy structure DM2. The dummy structures DM1 and DM2 may be located in the same film layer or different film layers, and the present invention is not limited thereto. The conductive connectors 160a and 160b can be completed together in the same manufacturing process, which can simplify the manufacturing process. FIG. 5 is a schematic partial cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention. The schematic cross-sectional view of Fig. 5 is roughly similar to the schematic cross-sectional view of Fig. 4, so the same components recorded in the fourth embodiment and the third embodiment can refer to the aforementioned related content, so the same configurations in the third and fourth embodiments, in This will not be repeated here.

In FIG. 5, the semiconductor structure 100C of this embodiment is different from the third embodiment in that the semiconductor structure 100C includes three conductive connectors 160a, 160b, 160c, and there are three dummy structures in the plurality of second conductive layers 126 DM1, DM2, DM3 correspond to the conductive connectors 160a, 160b, 160c, respectively. That is to say, the conductive connectors 160a, 160b, and 160c penetrate through the first substrate 112 and the plurality of insulating layers DL and the plurality of conductive layers ML in the stack structure S1 respectively, and one end of the conductive connector 160a is in contact with the dummy structure DM1 to conduct electricity. One end of the connection part 160b is in contact with the dummy structure DM2, and one end of the conductive connection part 160c is in contact with the dummy structure DM3. The dummy structures DM1 , DM2 , and DM3 may be located in the same film layer or different film layers, and the present invention is not limited thereto. The conductive connectors 160a, 160b, 160c can be completed together in the same manufacturing process, which can simplify the manufacturing process.

In one embodiment, the dummy structure DM3 can be located in the same film layer as the gate layers in the plurality of second conductive layers 126, that is, the dummy structure DM3 can be regarded as a dummy gate, but the present invention does not take this as a limit.

6A to 6H are partial cross-sectional schematic diagrams of a partial manufacturing process of a semiconductor structure according to a fifth embodiment of the present invention.

Referring to FIG. 6A , a three-dimensional semiconductor device 210 is provided on a carrier 201 . The carrier 201 can be made of silicon, glass, polymer or other suitable materials, and the present invention is not limited thereto, as long as the material can support the three-dimensional semiconductor element 210 formed on it and can withstand subsequent The process can be. The three-dimensional semiconductor device 210 includes a substrate 212 and a stack structure S2. The substrate 212 may be a silicon substrate, and is disposed on the carrier 201 . The substrate 212 may include active components or passive components, and the present invention is not limited thereto. The stack structure S2 is disposed between the substrate 212 and the carrier 201 , and includes a plurality of insulating layers 214 and a plurality of conductive layers 216 stacked alternately. Although a whole insulating layer 214 is shown in FIG. 6A , it should be understood that the insulating layer 214 is multi-layered and stacked alternately with the multi-layer conductive layer 216 . The material of the plurality of insulating layers 214 can be, for example, silicon dioxide, organic polymer material or other suitable insulating materials. The plurality of conductive layers 216 has a plurality of openings OP' and at least one dummy structure DM1'. The material of the plurality of conductive layers 216 can be a metal material (such as copper, aluminum or other suitable metal) for use as a subsequent interconnection or a polysilicon material for use as a gate or other semiconductor elements. The dummy structure DM1' can be the same mold layer as one of the conductive layers 216. For example, in this embodiment, the dummy structure DM1' is the same mold layer as the first layer M1' of the plurality of conductive layers 216, but the present invention is not limited thereto, and the dummy structure DM1' can be arranged in in the appropriate film layer. The dummy structure DM1' is floating, and it is not electrically connected to other conductive layers 216 (such as the first layer M1', the second layer M2', and the third layer M3').

In this embodiment, the openings OP' have the same width and are aligned with each other, but the invention is not limited thereto. In other embodiments, the openings OP' may have different widths. For example, the openings OP' farther away from the substrate 212 may have smaller widths.

In some embodiments, the stack structure S2 further includes a dielectric layer 218 disposed on a surface of the plurality of insulating layers 214 opposite to the substrate 212 . The three-dimensional semiconductor device 210 can be connected to the carrier 201 through the dielectric layer 218 .

In some embodiments, the substrate 212 includes an isolation structure ST1' to isolate the active regions in the substrate 212.

Please continue to refer to FIG. 6A, using the dummy structure DM1' as a stop layer, plasma etching is performed to form first through holes penetrating the substrate 212, the plurality of insulating layers 214 and the plurality of openings OP' in the substrate 212 and the stacked structure S2. V1'. For example, the mask layer 230 is formed on the substrate 212 first, and the mask layer 230 has a mask opening 230a. Afterwards, plasma etching is performed by using the mask layer 230 as a mask and using the dummy structure DM1' as a stop layer to form the first via hole V1'. The first via hole V1' penetrates through the substrate 212, the plurality of insulating layers 214 and the plurality of openings OP', and exposes the dummy structure DM1', but does not expose the plurality of conductive layers 216. That is, the width W2' of the first through hole V1' is smaller than the width W1' of the plurality of openings OP'. During the plasma etching process, only the dummy structure DM1' is exposed, and other conductive layers 216 are not exposed, so the occurrence of antenna effect can be reduced, the risk of damage to the three-dimensional semiconductor element 210 can be reduced, and the reliability thereof can be improved.

Moreover, in this embodiment, there is an isolation structure ST1' in the substrate 212, so the first via hole V1' can also penetrate through the isolation structure ST1'. That is to say, if there is no isolation structure ST1' in the substrate 212 or no isolation structure ST1' is provided at the position where the first via V1' is to be formed, the first via V1' will naturally not penetrate the isolation structure. In some embodiments, the shape of the first through hole V1' may be columnar or tapered, and the present invention is not limited thereto.

Referring to FIG. 6B , wet etching is performed to remove the substrate 212 and the plurality of insulating layers 214 in the first via hole V1 ′ until a portion of the plurality of conductive layers 216 is exposed, so as to form the second via hole V2 ′. The wet etching method is, for example, wet dip etching. The substrate 212 and the plurality of insulating layers 214 in the first via hole V1 ′ can be removed through multiple wet dips until a portion of the plurality of conductive layers 216 is exposed. For example, wet wetting can be performed twice, first using a first etchant to remove the substrate 212 in the first via V1', and then using a second etchant to remove the plurality of insulating layers 214 in the first via V1' . The first etchant may include tetramethylammonium hydroxide (TMAH), ammonia (NH ₄ OH) or other etchant used for wet etching silicon. The second etchant may include hydrofluoric acid (HF) or other etchant used for wet etching silicon oxide.

In some embodiments, the plurality of insulating layers 214 are over-etched through wet etching, so that the maximum width W3' of the second via hole V2' is greater than the width W1' of the plurality of openings OP' (shown in FIG. 6A ). In other embodiments, if the plurality of openings OP' have different widths, the maximum width W3' of the second through hole V2' may be greater than the maximum width W1' of the plurality of openings OP'.

In some embodiments, the shape of the second through hole V2' may be columnar or tapered, and the present invention is not limited thereto.

Referring to FIG. 6C , the mask layer 230 is removed, and an organic planar layer 240 is filled in the second via hole V2'. The organic planar layer 240 does not cover the sidewall of the substrate 212. Referring to FIG. The organic planar layer 240 can be, for example, organic resin, photoresist or other suitable materials, and the invention is not limited thereto. The organic planarization layer 240 does not cover the substrate 212 exposed in the second via hole V2', that is, the top surface of the organic planarization layer 240 may be substantially aligned with the top surface of the isolation structure ST1' or slightly lower than the isolation structure ST1'. top surface. In other embodiments, if the substrate 212 does not include the isolation structure ST1', the top surface of the organic planarization layer 240 may be substantially aligned with the top surfaces of the plurality of insulating layers 214 or slightly lower than the top surfaces of the plurality of insulating layers 214.

Referring to FIG. 6D, a part of the substrate 212 not covered by the organic planar layer 240 is removed to form a third via hole V3'. For example, isotropic etching or anisotropic etching can be used to remove part of the substrate 212 to form the third via hole V3'. The third through hole V3' overlaps the second through hole V2', and the width W4' of the third through hole V3' is greater than the width W3' of the second through hole V2' (shown in FIG. 5B ).

Referring to FIG. 6E and FIG. 6F , a passivation layer 250 is formed on the substrate 212 and the sidewall of the third via hole V3', and the surface of the organic planar layer 240 is exposed. For example, as shown in FIG. 6E , the passivation material layer 250a can be conformally formed on the substrate 212 and in the third via hole V3' by using a deposition method. In one embodiment, the thickness of the passivation material layer 250a on the substrate 212 is greater than the thickness of the passivation material layer 250a in the third via hole V3' through adjustment of deposition process parameters. Afterwards, as shown in FIG. 6F, part of the passivation material layer 250a is removed to expose the surface of the organic planar layer 240, thereby forming a passivation layer 250 to protect the substrate 212 and subsequently formed in the third via hole V3' or the substrate 212. isolated from conductive material. The method of removing part of the passivation material layer 250a may, for example, remove the passivation material layer 250a in the third via hole V3' by etching back, but the present invention is not limited thereto. In other embodiments, part of the passivation material layer 250a can also be removed by photolithographic etching, for example, a photoresist layer (not shown) is formed on the passivation material layer 250a to expose part of the passivation material layer 250a in the third via hole V3'. ), and use the photoresist layer as a mask to etch the exposed passivation material layer 250a until the surface of the organic planarization layer 240 is exposed to form the passivation layer 250, and then remove the photoresist layer.

Referring to FIG. 6G, the organic planar layer 240 in the second via hole V2' is removed to expose part of the dummy structure DM1' and part of the plurality of conductive layers 216. Referring to FIG. The organic planar layer 240 can be removed by ashing process, etching process or other suitable process, the invention is not limited thereto.

Referring to FIG. 6H , a conductive connector 260a is formed in the second via hole V2' (shown in FIG. 6G ) to be electrically connected to the plurality of conductive layers 216 . For example, the barrier layer 262 can be conformally formed on the surface of the second via hole V2 ′, and the conductive material layer 264 can be formed on the barrier layer 262 to form a conductive connection electrically connected to the plurality of conductive layers 216 Item 260a. The material of the barrier layer 262 can be, for example, tantalum, tantalum nitride, titanium, titanium nitride or other suitable materials, and the material of the conductive material layer 264 can be, for example, copper, tungsten or other suitable conductive materials, and the present invention is not limited thereto. . The barrier layer 262 and the conductive material layer 264 can be formed by physical vapor deposition (PVD), chemical vapor deposition (CVD) or atomic layer deposition (ALD), wherein preferably, chemical vapor deposition (CVD) or Atomic layer deposition (ALD) can make the barrier layer 262 completely cover the surface of the second via hole V2 ′ having uneven sidewalls, but the invention is not limited thereto.

In some embodiments, the barrier layer 262 and the conductive material layer 264 can also extend to the surface of the passivation layer 250 to serve as an interconnect structure. In some other embodiments, the barrier layer 162 and the conductive material layer 164 above the passivation layer 150 may also be removed in conjunction with chemical mechanical planarization, and then the fabrication of related interconnection structures may be continued. The interconnection structure can be manufactured by existing manufacturing processes, and will not be repeated here.

In this embodiment, the second via hole V2' is formed through plasma etching and wet etching. During the plasma etching process, only the dummy structure DM1' is exposed. The layer 216 is exposed to be electrically connected to the subsequently formed conductive connector 260a, thereby reducing the generation of the antenna effect and reducing the damage of the semiconductor structure caused by the strong electric field accumulated in the conductive layer in the process of forming the via hole by plasma etching. damage, thereby improving the reliability of the semiconductor structure.

After the above process, the fabrication of the semiconductor structure 200 of this embodiment can be substantially completed.

Therefore, the semiconductor structure 200 in FIG. 6H basically includes a substrate 212 (also referred to as a first substrate 212 ), a stack structure S2 and a conductive connector 260a. The stack structure S2 is disposed on the substrate 212, and includes a plurality of insulating layers DL' and a plurality of conductive layers ML' alternately stacked with the plurality of insulating layers DL'. The plurality of insulating layers DL' includes a plurality of insulating layers 214 and a dielectric layer 218 . The multiple conductive layers ML' include multiple conductive layers 216, wherein the multiple conductive layers 216 have a dummy structure DM1' therein, that is, at least one of the multiple conductive layers ML' has the dummy structure DM1'. The conductive connection 260a penetrates through the substrate 212 and the plurality of insulating layers DL' and the plurality of conductive layers ML' in the stack structure S2, and one end of the conductive connection 260a is in contact with the dummy structure DM1'. The sidewall of the conductive connector 260a has a concavo-convex shape, the recesses SW1" of the sidewall of the conductive connector 260a may correspond to the sidewalls of a plurality of conductive layers ML', and the protrusions SW2" of the sidewall of the conductive connector 260a may correspond to a plurality of insulating sidewall of layer DL'.

In this embodiment, the shape of the conductive connecting member 260a is columnar, but the present invention is not limited thereto. In other embodiments, the shape of the conductive connecting member 260a may be tapered. In one embodiment, the plurality of conductive layers ML' includes a plurality of openings OP', the positions of the plurality of openings OP' correspond to each other, and the conductive connectors 260a are disposed in the plurality of openings OP', wherein the conductive connectors 260a The sidewalls are in contact with sidewalls of the plurality of openings OP'. The opening OP' may include a circular opening, a rectangular opening, or a groove-like opening. The opening OP' is similar to the opening OP shown in FIG. 2A to FIG. 2C , which can be understood with reference to FIG. 2A to FIG. 2C and related paragraphs, and will not be repeated here.

In one embodiment, the plurality of openings OP' may have different widths, and the widths of the plurality of openings OP' that are farther away from the substrate 212 are smaller.

In one embodiment, the semiconductor structure 200 further includes a carrier 201 disposed on a surface of the stack structure S2 opposite to the substrate 212 . That is to say, the stack structure S2 is located between the substrate 212 and the carrier 201 .

In one embodiment, the substrate 212 may include an isolation structure ST1', and the conductive connection member 260a may penetrate through the isolation structure ST1'.

In one embodiment, the dummy structure DM1' is floating.

Since the semiconductor structure 200 has a conductive connector 260a in contact with the dummy structure DM1', and the portion of the sidewall SW1" of the conductive connector 260a in contact with each conductive layer ML' is smaller than the portion of the conductive connector 260a in contact with each insulating layer DL' The side wall SW2" is retracted, which can have better reliability.

To sum up, the semiconductor structure of the present invention forms the conductive connection member contacting the dummy structure through plasma etching and wet etching. Since only the dummy structure of the via hole is exposed during the plasma etching process, the conductive layer is exposed through wet etching, so that the portion of the sidewall of the subsequently formed conductive connection that contacts each conductive layer is thinner than the conductive connection. Portions of the sidewalls in contact with each insulating layer are set back. In this way, the generation of antenna effect can be reduced, and the damage to the semiconductor structure caused by the strong electric field accumulated in the conductive layer in the process of forming the via hole by plasma etching can be reduced, thereby improving the reliability of the semiconductor structure.

100A, 100A', 100B, 100C, 200: Semiconductor structure 110: The first three-dimensional semiconductor element 112: The first substrate 114: the first insulating layer 116: the first conductive layer 118: the first dielectric layer 120: The second three-dimensional semiconductor element 122: Second substrate 124: Second insulating layer 126: the second conductive layer 128: second dielectric layer 130, 230: mask layer 130a, 230a: curtain opening 140, 240: organic flat layer 150, 250: passivation layer 150a, 250a: passivation material layer 160a, 160a', 160b, 160c, 260a: conductive connectors 162, 262: barrier layer 164, 264: conductive material layer 201: carrier board 210: Three-dimensional semiconductor components 212: Substrate (first substrate) 214: insulating layer 216: conductive layer 218: Dielectric layer DL, DL': insulating layer DM1, DM1', DM2, DM3: dummy structures ML, ML': conductive layer M1, M1': the first layer M2, M2': the second floor M3, M3': the third floor OP, OP': opening OP1: first opening OP2: second opening P1: part one P2: Part Two S1, S2: stacked structure S11: The first stack structure S12: Second stack structure ST1': isolation structure ST1: The first isolation structure ST2: Second isolation structure SW1, SW2, SW1’, SW2’, SW1”, SW2”: side walls V1, V1': the first through hole V2, V2': the second through hole V3, V3': the third through hole W1, W2, W3, W4, W5, W1’, W2’, W3’, W4’: Width

1A to 1J are schematic partial cross-sectional views of a manufacturing process of a semiconductor structure according to a first embodiment of the present invention. FIG. 2A is a schematic partial top view of the conductive layer in FIG. 1J . FIG. 2B is another partial top view of the conductive layer in FIG. 1J . FIG. 2C is another partial top view of the conductive layer in FIG. 1J . 3 is a schematic partial cross-sectional view of a semiconductor structure according to a second embodiment of the present invention. FIG. 4 is a schematic partial cross-sectional view of a semiconductor structure according to a third embodiment of the present invention. FIG. 5 is a schematic partial cross-sectional view of a semiconductor structure according to a fourth embodiment of the present invention. 6A to 6H are partial cross-sectional schematic diagrams of a partial manufacturing process of a semiconductor structure according to a fifth embodiment of the present invention.

100A: Semiconductor Structure

112: The first substrate

114: the first insulating layer

116: the first conductive layer

118: the first dielectric layer

122: Second substrate

124: Second insulating layer

126: the second conductive layer

128: second dielectric layer

150: passivation layer

160a: Conductive connector

162: barrier layer

164: conductive material layer

DL: insulating layer

DM1: Dummy structure

ML: conductive layer

OP: opening

OP1: first opening

OP2: second opening

S1: stack structure

ST1: The first isolation structure

ST2: Second isolation structure

SW1, SW2: side wall

Claims (23)

A semiconductor structure comprising: first substrate; A stacked structure disposed on the first substrate, wherein the stacked structure includes: multiple layers of insulation; and a plurality of conductive layers alternately stacked with the plurality of insulating layers, wherein at least one of the plurality of conductive layers has a dummy structure; and at least one conductive connection piece, passing through the first substrate and the plurality of insulating layers and the plurality of conductive layers in the stacked structure, and one end of the conductive connection piece is in contact with the dummy structure, wherein the The side wall of the conductive connector has a concave-convex shape, the recesses of the side wall of the conductive connector correspond to the side walls of the plurality of conductive layers, and the protrusions of the side wall of the conductive connector correspond to the plurality of layers. side walls of an insulating layer. The semiconductor structure according to claim 1, further comprising a second substrate disposed on a surface of the stack structure opposite to the first substrate. The semiconductor structure of claim 1, wherein the dummy structure is floating. The semiconductor structure as claimed in claim 1, wherein the first substrate includes a first isolation structure, and the conductive connection member penetrates through the first isolation structure. The semiconductor structure according to claim 1, wherein the plurality of conductive layers include a plurality of openings, the positions of the plurality of openings correspond to each other, and the conductive connectors are disposed in the plurality of openings, wherein the plurality of openings The sidewalls of the conductive connectors are in contact with the sidewalls of the plurality of openings. The semiconductor structure as claimed in claim 5, wherein the plurality of openings have different widths, and the widths of the plurality of openings are smaller the farther away from the first substrate. The semiconductor structure as claimed in claim 5, wherein each of the openings comprises a circular opening, a rectangular opening or a trench opening. The semiconductor structure according to claim 1, wherein more than two of the plurality of conductive layers have the dummy structure. A method of fabricating a semiconductor structure, comprising: A first three-dimensional semiconductor element is provided, the first three-dimensional semiconductor element comprising: a first substrate; and The first stack structure is disposed on the first substrate, wherein the first stack structure includes a plurality of first insulating layers and a plurality of first conductive layers stacked alternately, wherein the plurality of first conductive layers have a plurality of a first opening; A second three-dimensional semiconductor element is provided, the second three-dimensional semiconductor element comprising: a second substrate; and The second stack structure is disposed on the second substrate, wherein the second stack structure includes a plurality of second insulating layers and a plurality of second conductive layers stacked alternately, wherein at least one of the plurality of second conductive layers one has a dummy structure, and the plurality of second conductive layers has a plurality of second openings; bonding the first three-dimensional semiconductor element and the second three-dimensional semiconductor element, wherein the positions of the plurality of second openings and the plurality of first openings are aligned with each other; Using the dummy structure as a stop layer, plasma etching is performed to form through the first substrate, the plurality of first stacked structures in the first substrate, the first stacked structure, and the second stacked structure. an insulating layer, the plurality of first openings, the plurality of second insulating layers, and the first through holes of the plurality of second openings; performing wet etching to remove the first substrate, the plurality of first insulating layers, and the plurality of second insulating layers in the first through hole until a part of the plurality of first conductive layers is exposed and a portion of the plurality of second conductive layers to form a second via hole; and A conductive connector is formed in the second through hole to be electrically connected to the plurality of first conductive layers and the plurality of second conductive layers. The method for manufacturing a semiconductor structure according to claim 9, wherein the step of performing the wet etching includes over-etching the plurality of first insulating layers and the plurality of second insulating layers, so that the second vias The maximum width of the hole is greater than the maximum width of the plurality of first openings and the maximum width of the plurality of second openings. The method for manufacturing a semiconductor structure as claimed in claim 10, wherein the shape of the first through hole and the shape of the second through hole are columnar or tapered, respectively. The method of manufacturing a semiconductor structure as claimed in item 9, wherein: In the first three-dimensional semiconductor element, the widths of the plurality of first openings are smaller the farther away from the first substrate; In the second three-dimensional semiconductor element, widths of the plurality of second openings are smaller closer to the second substrate; and During the bonding of the first three-dimensional semiconductor element and the second three-dimensional semiconductor element, the widths of the plurality of first openings and the widths of the plurality of second openings are equal to those that are farther away from the first substrate. The smaller the way the configuration is. The method for manufacturing a semiconductor structure according to claim 9, wherein the plurality of first conductive layers and the plurality of second conductive layers are not exposed during the formation of the first via hole. The method for manufacturing a semiconductor structure as claimed in item 9, wherein the step of performing the wet etching comprises: removing the first substrate within the first via hole using a first etchant; and The plurality of first insulating layers and the plurality of second insulating layers in the first through hole are removed using a second etchant. The method for manufacturing a semiconductor structure according to claim 9, further comprising: before forming the conductive connection in the second via hole: filling the second through hole with an organic planar layer, and the organic planar layer does not cover the sidewall of the first substrate; removing a portion of the first substrate not covered by the organic planar layer to form a third through hole, wherein the third through hole overlaps with the second through hole, and the width of the third through hole is larger than the The width of the second through hole; forming a passivation layer on the first substrate and the sidewall of the third through hole, and exposing the surface of the organic planar layer; and The organic planar layer is removed to expose part of the dummy structure, part of the plurality of first conductive layers, and part of the plurality of second conductive layers. The method for manufacturing a semiconductor structure as claimed in claim 9, wherein the step of forming the conductive connector in the second through hole comprises: conformally forming a barrier layer on the surface of the second via hole and A conductive material layer is filled in the second through hole. A method of fabricating a semiconductor structure, comprising: A three-dimensional semiconductor element is provided on the carrier, the three-dimensional semiconductor element comprising: a substrate disposed on the carrier; and a stack structure, disposed between the substrate and the carrier plate, the stack structure includes: a plurality of insulating layers and a plurality of conductive layers stacked alternately, wherein at least one of the plurality of conductive layers has a dummy structure, and the plurality of conductive layers has a plurality of openings; performing plasma etching using the dummy structure as a stop layer, so as to form first through holes penetrating the substrate, the plurality of insulating layers, and the plurality of openings in the substrate and the stacked structure; performing wet etching to remove the substrate and the plurality of insulating layers in the first through hole until a part of the plurality of conductive layers is exposed, so as to form a second through hole; and A conductive connection is formed in the second through hole to be electrically connected to the plurality of conductive layers. The method for manufacturing a semiconductor structure as claimed in claim 17, wherein the step of performing the wet etching includes overetching the plurality of insulating layers, so that the maximum width of the second via hole is greater than that of the plurality of openings maximum width. The method for manufacturing a semiconductor structure as claimed in claim 17, wherein the shape of the first through hole and the shape of the second through hole are columnar or tapered, respectively. The method for manufacturing a semiconductor structure according to claim 17, wherein in the three-dimensional semiconductor element, the widths of the plurality of openings are smaller the farther away from the substrate. The method of manufacturing a semiconductor structure as claimed in claim 17, wherein the plurality of conductive layers are not exposed during the formation of the first via hole. The method for manufacturing a semiconductor structure as claimed in item 17, wherein the step of performing the wet etching comprises: removing the substrate within the first via hole using a first etchant; and The plurality of insulating layers within the first via is removed using a second etchant. The method for manufacturing a semiconductor structure according to claim 17, further comprising: before forming the conductive connection in the second via hole: filling the second through hole with an organic planar layer, and the organic planar layer does not cover the sidewall of the substrate; removing a portion of the substrate not covered by the organic planar layer to form a third through hole, wherein the third through hole overlaps with the second through hole, and the width of the third through hole is larger than that of the first through hole. The width of the two through holes; forming a passivation layer on the substrate and the sidewall of the third through hole, and exposing the surface of the organic planar layer; and The organic planar layer is removed to expose part of the dummy structure and part of the plurality of conductive layers.

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