CN106847925B - Power device with surface inversion type fixed interface charges - Google Patents

Power device with surface inversion type fixed interface charges Download PDF

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Publication number
CN106847925B
CN106847925B CN201710087033.8A CN201710087033A CN106847925B CN 106847925 B CN106847925 B CN 106847925B CN 201710087033 A CN201710087033 A CN 201710087033A CN 106847925 B CN106847925 B CN 106847925B
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fixed interface
active layer
oxide layer
field oxide
power device
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CN106847925A (en
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李琦
陆诗维
李海鸥
首照宇
陈永和
杨年炯
李思敏
张法碧
高喜
傅涛
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Guilin University of Electronic Technology
Guangxi University of Science and Technology
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Guilin University of Electronic Technology
Guangxi University of Science and Technology
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H01L29/7824—Lateral DMOS transistors, i.e. LDMOS transistors with a substrate comprising an insulating layer, e.g. SOI-LDMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/36—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the concentration or distribution of impurities in the bulk material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

The invention provides a power device with surface inversion type fixed interface charges, which comprises a field oxygen layer and an active layer, wherein the field oxygen layer is positioned on the active layer; a variable-doping fixed interface charge region is also arranged in the field oxygen layer; the charge polarity of the fixed charge region is opposite to the polarity of the active layer ions; the fixed interfacial charge region is located at a lower portion of the field oxide layer and is in contact with a lower surface of the field oxide layer, i.e., an interface between the field oxide layer and the active layer. The interaction between the charges of the inversion-type fixed interface forms a continuous peak electric field in the field oxide layer, and the peak electric field improves the electric field distribution of the active layer, thereby effectively improving the breakdown voltage of the device. Meanwhile, as partial power lines of ions in the drift region are terminated by inverted fixed interface charges, the optimized doping concentration of the active layer is improved, and the on-resistance is reduced.

Description

Power device with surface inversion type fixed interface charges
Technical Field
The invention relates to the technical field of semiconductor power devices, in particular to a power device with surface inversion type fixed interface charges.
Background
Modern power integrated circuits are widely applied to daily consumption fields such as power control systems, automotive electronics, display device driving, communication and lighting, and a plurality of important fields such as national defense and aerospace, and the requirements on high-voltage power semiconductor devices of core parts of the modern power integrated circuits are higher and higher along with the continuous expansion of the application fields.
In the design process of the transverse high-voltage power device, the mutual influence of factors such as breakdown voltage, on-resistance, process complexity, reliability and the like must be comprehensively considered, so that a reasonable compromise is achieved. Generally, the performance improvement on one side often leads to the performance reduction on the other side, and the breakdown voltage and the on-resistance have such a contradictory relationship. How to keep the on-resistance reduced or unchanged while improving the breakdown voltage becomes a goal pursued by researchers in the related art.
Disclosure of Invention
The invention provides a power device with surface inversion type fixed interface charges, which can improve electric field distribution, improve the voltage withstanding characteristic of a power semiconductor device and reduce on-resistance.
In order to solve the problems, the invention is realized by the following technical scheme:
the power device with surface inversion type fixed interface charges comprises a field oxide layer and an active layer, wherein the field oxide layer is positioned on the active layer; a variable-doping fixed interface charge region is also arranged in the field oxygen layer; the charge polarity of the fixed charge region is opposite to the polarity of the active layer ions; the fixed interfacial charge region is located at a lower portion of the field oxide layer and is in contact with a lower surface of the field oxide layer, i.e., an interface between the field oxide layer and the active layer.
In the above scheme, the fixed interface charge regions are continuously or discontinuously arranged in the lateral extension direction.
In the above scheme, the fixed interface charge region is a laterally-varying doped fixed interface charge region.
In the above-described aspect, the surface charge density of the fixed interface charge region gradually changes in the lateral direction.
In the above scheme, the active layer is made of Si, SiC, GaAs, SiGe or GaN.
Compared with the prior art, the invention has the following characteristics:
1. the interaction between the charges of the inversion fixed interfaces pulls the electric field lines of the active layer high, and a new electric field peak value is introduced at the position of the abrupt change of the surface charge density, so that the maximum electric field peak value is reduced, and the lateral withstand voltage of the device is improved.
2. Due to the existence of the inversion type fixed interface charges in the field oxide layer, ions in the drift region partially interact with the inversion type fixed interface charges, compared with a conventional device, the optimal doping concentration of an active layer of the power device with the surface inversion type fixed interface charges needs to be improved, and the on-resistance of the device is reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional SOI type P-LDMOS power device.
Fig. 2 is a schematic structural diagram of a power device with surface inversion type fixed interface charges (an SOI type P-LDMOS power device).
FIG. 3 is a graph comparing the breakdown characteristics of conventional SOI type P-LDMOS power devices and SOI type P-LDMOS power device structures with surface inversion type fixed interface charges.
FIG. 4 is a graph comparing the surface electric field distribution of a conventional SOI type P-LDMOS power device with that of an SOI type P-LDMOS power device having a surface inversion type fixed interface charge.
Fig. 5 is a schematic diagram of another power device (diode power device) with surface inversion fixed interface charges.
Reference numbers in the figures: 1. a substrate; 2. a dielectric buried layer; 3. an active layer; 4. a field oxide layer; 5. a source electrode; 6. a gate electrode; 7. a drain electrode; 8. a channel; 9. a contact zone; 10. a source region; 11. a drain region; 12. a fixed interface charge region; 13. an anode region; 14. a cathode region; 15. an anode; 16. and a cathode.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technology in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
A power device with surface inversion type fixed interface charges comprises a field oxide layer 4 and an active layer 3, wherein the field oxide layer 4 is positioned on the active layer 3. A fixed interface charge region 12 is also provided in the field oxide layer 4. Due to the existence of the inversion type fixed interface charges in the field oxide layer 4, the ions in the drift region partially interact with the fixed interface charges, so that compared with a conventional device, the optimized active layer 3 has higher doping concentration, and the on-resistance of the device is reduced.
Structurally, the fixed interface charge region 12 is located at a lower portion of the field oxide layer 4 and is in contact with a lower surface of the field oxide layer 4, i.e., an interface between the field oxide layer 4 and the active layer 3. The fixed interface charge regions 12 are disposed continuously or intermittently in the lateral extension direction. When the fixed interface charge region 12 is continuously disposed, the fixed interface charge region 12 is an uninterrupted whole in the lateral direction. When the fixed interface charge region 12 is disposed intermittently, the fixed interface charge region 12 is divided into a plurality of regions in the lateral direction.
In terms of surface charge density, the fixed interface charge region 12 is a laterally-doped fixed interface charge region 12. The fixed interface charge region 12 has a gradual change in the surface charge density in the lateral direction, i.e., the surface charge density of the fixed interface charge region 12 increases or decreases in the lateral direction. When the fixed interface charge region 12 is disposed continuously, the fixed interface charge region 12 is laterally doped in regions, i.e., the entire fixed interface charge region 12 is laterally divided into a plurality of regions, each having an area charge density. When the fixed interface charge region 12 is intermittently disposed, the fixed interface charge region 12 is formed with laterally varying doping in blocks, i.e., each spaced block has a fixed surface charge density, and the surface charge density of each block is different from each other.
The fixed charge region is inverted in polarity, that is, the polarity of the fixed charge region is opposite to the polarity of the ions of the active layer 3. When the polarity of the ions of the active layer 3 is positive, the fixed charge region is negative. When the polarity of the ions of the active layer 3 is negative, the fixed charge region is positive. The interaction between the charges of the inversion fixed interfaces pulls the electric field lines of the active layer 3 high, and a new electric field peak value is introduced at the position of the abrupt change of the surface charge density, so that the maximum electric field peak value is reduced, and the lateral withstand voltage of the device is improved.
The inversion type fixed interface charge region 12 is arranged in the field oxide layer 4 to form a voltage-resistant structure, so that the voltage-resistant structure can be suitable for various transverse power devices and structures such as MOSFET, BJT, IGBT, GTO and IGCT, and is suitable for various semiconductor materials such as Si, SiC, GaAs and SiGe.
Example 1:
a power device with surface inversion type fixed interface charges, namely an SOI type P-LDMOS power device, is shown in FIG. 2 and comprises a substrate 1, a medium buried layer 2, an active layer 3, a field oxide layer 4, a source electrode 5, a gate electrode 6, a drain electrode 7, a channel 8, a contact region 9, a source region 10, a drain region 11 and a fixed interface charge region 12. The substrate 1, the medium buried layer 2, the active layer 3 and the field oxide layer 4 are stacked in sequence from top to bottom. The channel 8 is arranged on the left side of the active region 10, above the channel 8 is the gate electrode 6. The adjacent source region 10 and contact region 9 are connected with the surface of the channel 8, and the source electrode 5 is arranged above the source region 10 and contact region 9. The drain region 11 is disposed on the right side of the active region 10, and the drain electrode 7 is above the drain region 11. The source electrode 5, the gate electrode 6 and the drain electrode 7 are disposed in the field oxide layer 4, wherein the source electrode 5 and the gate electrode 6 are disposed on the left side of the field oxide layer 4, and the drain electrode 7 is disposed on the right side of the field oxide layer 4. In the present embodiment, the contact region 9 is a heavily doped N-type region. Source region 10 is a heavily doped P-type region. The channel 8 is lightly doped N-type. The drain region 11 is heavily P-doped. The active layer 3 is doped P-type and has a concentration of 8.8e14/cm3。
The fixed interface charge region 12 is located within the field oxide layer 4 between the gate electrode 6 and the drain electrode 7. The fixed interface charge region 12 is located below the field oxide layer 4 and is connected to the lower surface of the field oxide layer 4, i.e. the boundary between the field oxide layer 4 and the active layer 3The surfaces are contacted. The fixed interface charge region 12 is continuously arranged in the lateral extension direction, that is, the fixed interface charge region 12 is composed of a plurality of virtually divided regions, and the areal density of the virtually divided regions is in a decreasing distribution. From the gate electrode 6 to the drain electrode 7, the surface charge density was from 2.0e12/cm2To 1.0e12/cm2Gradually changing with the gradual change step length of 0.5e12/cm2. The fixed charge region is positively charged.
FIG. 3 is a graph comparing the breakdown characteristics of the conventional SOI type P-LDMOS power device shown in FIG. 1 with the SOI type P-LDMOS power device shown in FIG. 2 having a surface inversion type fixed interface charge. As can be seen from the figure, compared with the structure of the conventional SOI type P-LDMOS power device, the breakdown voltage of the SOI type P-LDMOS power device with the surface inversion fixed interface charge is improved by 50 percent by applying the SOI type P-LDMOS power device.
FIG. 4 is a graph comparing the surface electric field distribution of the conventional SOI type P-LDMOS power device shown in FIG. 1 with that of the SOI type P-LDMOS power device shown in FIG. 2 having a surface inversion type fixed interface charge. As can be seen from the figure, the surface electric field of the conventional SOI type P-LDMOS power device forms a higher spike electric field near the gate electrode 6 and the drain electrode 7 of the device, and the electric field intensity between the gate and the drain is small, so that the device is easy to break down and the breakdown voltage is low; by applying the surface electric field of the SOI type P-LDMOS power device with the surface inversion type fixed interface charge, the electric field peak near the gate electrode 6 and the drain electrode 7 is reduced, the electric field intensity near the introduced inversion type fixed interface charge region 12 is obviously increased, the electric field distribution is improved, and the breakdown voltage is improved.
Example 2:
a power device with surface inversion type fixed interface charges, i.e., a diode power device, as shown in fig. 5, includes a substrate 1, an active layer 3, a field oxide layer 4, an anode region 13, a cathode region 14, an anode 15, a cathode 16, and a fixed interface charge region 12. The substrate 1, the active layer 3 and the field oxide layer 4 are sequentially stacked from bottom to top. The anode region 13 and the cathode region 14 are located at an upper portion of the active layer 3, which are located at both sides of the active layer 3, respectively. An anode 15 and a cathode 16 are disposed on either side of the field oxide layer 4, the anode 15 being located directly above the anode region 13 and the cathode region 14 being located directly above the cathode region 14.
The fixed interface charge region 12 is located within the field oxide layer 4 between the anode 15 and the cathode 16. The fixed interface charge region 12 is located at the lower portion of the field oxide layer 4 and is in contact with the lower surface of the field oxide layer 4, i.e., the interface between the field oxide layer 4 and the active layer 3. The fixed interface charge region 12 is intermittently arranged in the lateral extension direction, that is, the fixed interface charge region 12 is composed of a plurality of independent spaced blocks, and the spaced blocks are sequentially arranged in the horizontal direction. The areal density of these spaced patches is decreasing from the anode 15 to the cathode 16. The charge polarity of the fixed charge region is negative.
The invention introduces inversion type fixed interface charges near the lower surface in the field oxide layer 4 in the whole range or partial range between the gate electrode 6 and the drain electrode 7 (or between the cathode 16 and the anode 15) of the power device, so that the electric field intensity near the gate electrode 6 and the drain electrode 7 (or between the cathode 16 and the anode 15) of the device can be reduced, and the device can be prevented from being broken down in advance. The interaction between the charges of the inversion type fixed interface forms a continuous peak electric field in the field oxide layer 4, and the peak electric field improves the electric field distribution of the active layer 3, thereby effectively improving the breakdown voltage of the device. Meanwhile, as part of the power lines of the ions in the drift region are terminated by the charges of the inversion fixed interface, the optimized doping concentration of the active layer 3 is increased, and the on-resistance is reduced.

Claims (4)

1. The power device with surface inversion type fixed interface charges comprises a field oxide layer (4) and an active layer (3), wherein the field oxide layer (4) is positioned on the active layer (3); the method is characterized in that: a variable-doping fixed interface charge area (12) is also arranged in the field oxide layer (4), and the charge polarity of the fixed interface charge area (12) is opposite to the polarity of ions of the active layer (3); the fixed interface charge regions (12) are arranged discontinuously in the transverse extension direction, each interval block has a fixed surface charge density, and the surface charge densities of the interval blocks are different; the fixed interface charge region (12) is positioned at the lower part of the field oxide layer (4) and is in contact with the lower surface of the field oxide layer (4), namely the interface between the field oxide layer (4) and the active layer (3).
2. The power device with surface inversion fixed interface charge of claim 1, wherein: the area charge density of the fixed interface charge region (12) gradually changes in the lateral direction.
3. The power device with surface inversion fixed interface charge of claim 1, wherein: the active layer (3) is made of Si, SiC, GaAs, SiGe or GaN.
4. The power device with surface inversion fixed interface charge of claim 1, wherein: the power device is a lateral power device.
CN201710087033.8A 2017-02-17 2017-02-17 Power device with surface inversion type fixed interface charges Active CN106847925B (en)

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Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098758A (en) * 2016-08-17 2016-11-09 电子科技大学 A kind of junction termination structures of power device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010014281A1 (en) * 2008-07-30 2010-02-04 Maxpower Semiconductor Inc. Semiconductor on insulator devices containing permanent charge
CN104269441B (en) * 2014-10-22 2017-05-10 桂林电子科技大学 SOI voltage resistance structure with charge regions fixed at equal intervals and SOI power device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN106098758A (en) * 2016-08-17 2016-11-09 电子科技大学 A kind of junction termination structures of power device

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