CN106847818A - The preparation method of Split-gate flash memory - Google Patents
The preparation method of Split-gate flash memory Download PDFInfo
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- CN106847818A CN106847818A CN201710078924.7A CN201710078924A CN106847818A CN 106847818 A CN106847818 A CN 106847818A CN 201710078924 A CN201710078924 A CN 201710078924A CN 106847818 A CN106847818 A CN 106847818A
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- layer
- side wall
- gate
- flash memory
- split
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
Abstract
The present invention proposes a kind of preparation method of Split-gate flash memory, one layer of side wall sacrifice layer is formed outside side wall, because the thickness of side wall sacrifice layer is controllable, its thickness can be the amount of being etched of side wall in the prior art, so as to by the amount of being etched for controlling the thickness of side wall sacrifice layer to control side wall, and then the floating gate layer for exposing is controlled, it is finally reached the purpose of the tip height of control floating boom, it is to avoid form device unstable properties.
Description
Technical field
The present invention relates to field of semiconductor manufacture, more particularly to a kind of preparation method of Split-gate flash memory.
Background technology
In the structure of Split-gate flash memory, the height of Split-gate flash memory (Flash Cell) tip (Tip) is
One highly important factor of influence integral device performance.In the manufacturing process of reality, at present to the height optimization at tip
Technique is used and is etched back to technique (Pull Back Clean).
Specifically, refer to Fig. 1 to Fig. 3, in the prior art, oxide layer 11 is formed with over the substrate 10, in oxide layer 11
On be formed with floating gate layer 20, be formed with grid structure on the floating gate layer 20, the grid structure includes the (side wall 30 of side wall 30
Material be silica), control gate 40 and grid protective layer 50, wherein, when floating boom is formed, it is necessary to first be carried out to the side wall 30
Floating boom silicon nitride is etched back to technique, with etched portions side wall 30, as shown in Fig. 2 being located at side wall before now exposing part
Floating gate layer 20 under 30, then, then using the side wall 30 as hard mask layer, performs etching to the floating gate layer 20, forms floating
Grid, while floating boom is formed, its edge can be formed with tip 21, and the height at tip 21 exposes many after being etched by side wall 30
Lack floating gate layer 20 and determine.If the amount of being etched of side wall 30 is larger, tip 21 can be made highly relatively low, if the amount of being etched is smaller,
The height of tip 21 can be made higher.
Wherein, the height at tip 21 is too high can influence to wipe (Erase) and write the performance of (Program), it is necessary to by point
The height at end 21 maintains predetermined height can keep the performance of device.However, be etched back to use harsh etching technique,
And acid has the term of validity, such as the etching rate between resting period more long old acid and the eo-acid being just made has very big difference,
This results in the side wall amount of being etched and there are the factors of instability, and then causes the highly uncontrollable of tip 21, also just cannot be true
It is conformal into device performance.
The content of the invention
It is an object of the invention to provide a kind of preparation method of Split-gate flash memory, it can be ensured that the height at floating boom tip
Degree, and then ensure the performance of device.
To achieve these goals, the present invention proposes a kind of preparation method of Split-gate flash memory, including step：
Semiconductor substrate is provided, floating gate layer and floating boom mask layer, the floating boom are sequentially formed with the Semiconductor substrate
Mask layer is provided with multiple grooves, and the groove exposes the floating gate layer；
One layer of side wall sacrifice layer is formed in the floating gate layer and floating boom mask layer surface；
One layer of side wall layer is formed in the side wall sacrificial layer surface；
The side wall layer and side wall sacrifice layer are sequentially etched, side wall and side wall sacrifice layer are retained in the groove；
The etching removal floating boom mask layer and the side wall sacrifice layer positioned at side wall side wall, expose the part and are located at
The floating gate layer of side wall sacrifice layer bottom；
Etch the floating gate layer and form floating boom.
Further, in the preparation method of described Split-gate flash memory, the side wall sacrifice layer material is nitridation
Silicon.
Further, in the preparation method of described Split-gate flash memory, the floating boom mask layer material is nitridation
Silicon.
Further, in the preparation method of described Split-gate flash memory, the floating boom is removed using wet etching
Mask layer and the side wall sacrifice layer positioned at side wall side wall.
Further, in the preparation method of described Split-gate flash memory, the material of the side wall is silica.
Further, in the preparation method of described Split-gate flash memory, one is formed with the Semiconductor substrate
Layer oxide layer, the floating gate layer is formed in the oxidation layer surface.
Further, in the preparation method of described Split-gate flash memory, formed between the side wall in the groove
There is control gate.
Further, in the preparation method of described Split-gate flash memory, the control gate surface is formed with control
Grid protective layer.
Further, in the preparation method of described Split-gate flash memory, the material of the control gate is polysilicon.
Further, in the preparation method of described Split-gate flash memory, the material of the floating gate layer is polysilicon.
Compared with prior art, the beneficial effects are mainly as follows：One layer of side wall sacrifice layer is formed outside side wall,
Because the thickness of side wall sacrifice layer is controllable, its thickness can be the amount of being etched of side wall in the prior art such that it is able to by control
The thickness of side wall sacrifice layer processed controls the amount of being etched of side wall, and then controls the floating gate layer for exposing, and is finally reached control floating
The purpose of the tip height of grid, it is to avoid form device unstable properties.
Brief description of the drawings
Fig. 1 to Fig. 3 is generalized section in the prior art in Split-gate flash memory preparation process；
Fig. 4 is the flow chart of the preparation method of Split-gate flash memory in one embodiment of the invention；
Fig. 5 to Fig. 8 is the generalized section in Split-gate flash memory preparation process in one embodiment of the invention.
Specific embodiment
The preparation method of Split-gate flash memory of the invention is described in more detail below in conjunction with schematic diagram, its
In illustrate the preferred embodiments of the present invention, it should be appreciated that those skilled in the art can change invention described herein, and
Still advantageous effects of the invention are realized.Therefore, description below is appreciated that knowing extensively for those skilled in the art
Road, and it is not intended as limitation of the present invention.
For clarity, not describing whole features of practical embodiments.In the following description, it is not described in detail known function
And structure, because they can make the present invention chaotic due to unnecessary details.It will be understood that opening in any practical embodiments
In hair, it is necessary to make a large amount of implementation details to realize the specific objective of developer, such as according to relevant system or relevant business
Limitation, another embodiment is changed into by one embodiment.Additionally, it should think that this development is probably complicated and expends
Time, but it is only to those skilled in the art routine work.
The present invention is more specifically described by way of example referring to the drawings in the following passage.Will according to following explanation and right
Book is sought, advantages and features of the invention will become apparent from.It should be noted that, accompanying drawing is in the form of simplifying very much and using non-
Accurately ratio, is only used to conveniently, lucidly aid in illustrating the purpose of the embodiment of the present invention.
Fig. 4 is refer to, in the present embodiment, it is proposed that a kind of preparation method of Split-gate flash memory, including step：
S100：Semiconductor substrate is provided, floating gate layer and floating boom mask layer are sequentially formed with the Semiconductor substrate, it is described
Floating boom mask layer is provided with multiple grooves, and the groove exposes the floating gate layer；
S200：One layer of side wall sacrifice layer is formed in the floating gate layer and floating boom mask layer surface；
S300：One layer of side wall layer is formed in the side wall sacrificial layer surface；
S400：The side wall layer and side wall sacrifice layer are sequentially etched, side wall and side wall sacrifice layer are retained in the groove；
S500：The etching removal floating boom mask layer and the side wall sacrifice layer positioned at side wall side wall, expose the portion
Divide the floating gate layer positioned at side wall sacrifice layer bottom；
S600：Etch the floating gate layer and form floating boom.
Specifically, refer to Fig. 5, in the present embodiment, layer of oxide layer 110 is formed with the Semiconductor substrate 100,
The floating gate layer 200 is formed in the surface of the oxide layer 110, and the material of the floating gate layer 200 can be polysilicon.
Additionally, the surface of the floating gate layer 200 is formed with floating boom mask layer 300, the floating boom mask layer 300 is provided with multiple
Groove, the groove exposes the floating gate layer 200；Specific generation type can be for first in the surface shape of the floating gate layer 200
Into one layer of floating boom mask layer 300, photoresistance is then coated with, and development treatment is exposed to photoresistance, then the photoresistance to pattern
The etching of floating boom mask layer 300 is carried out as mask, groove is formed.Wherein, the material of the floating boom mask layer 300 is nitridation
Silicon.
Then, one layer of side wall sacrifice layer 310, the side wall are formed in the floating gate layer 200 and the surface of floating boom mask layer 300
The material of sacrifice layer 310 is silicon nitride, and its thickness is controllable.
Then, one layer of side wall layer 400 is formed on the surface of the side wall sacrifice layer 310, the material of the side wall 400 is oxygen
SiClx.
Fig. 6 is refer to, Fig. 6 is the Local map of Fig. 5 dotted line frames, is sequentially etched the side wall layer 400 and side wall sacrifice layer
310, side wall 400 and side wall sacrifice layer 310 are retained in the groove.
Refer to Fig. 7, the etching removal floating boom mask layer 300 and the side wall sacrifice layer positioned at the side wall of side wall 400
310, expose floating gate layer 200 of the part positioned at the bottom of side wall sacrifice layer 310；Individual in this step, etching uses wet method
Etching, because the material of floating boom mask layer 300 and side wall sacrifice layer 310 is silicon nitride, because both can be in same etching
It is removed in technique, and without additional process step.Further, since the material of side wall 400 is silica, to floating
When grid mask layer 300 and side wall sacrifice layer 310 are performed etching, side wall 400 will not be performed etching, therefore, etch the side of removal
The thickness of wall sacrifice layer 310 becomes can be as the amount of being etched of side wall 400 in the prior art.
Fig. 8 is refer to, the floating gate layer 200 is etched and is formed floating boom, the floating boom has tip 210, and because side wall is sacrificial
The thickness of domestic animal layer 310 is controllable, therefore, it can the height at control tip 210, so that the performance of control device.
Additionally, being formed with control gate 500 between side wall 400 in the groove, the surface of the control gate 500 is formed with control
Grid protective layer 600 processed.The material of the floating gate layer 200 and control gate 500 is polysilicon.
To sum up, in the preparation method of Split-gate flash memory provided in an embodiment of the present invention, one layer is formed outside side wall
Side wall sacrifice layer, because the thickness of side wall sacrifice layer is controllable, its thickness can be the amount of being etched of side wall in the prior art, so that
By the amount of being etched that controls the thickness of side wall sacrifice layer to control side wall, and then the floating gate layer for exposing can be controlled, finally
Reach the purpose of the tip height of control floating boom, it is to avoid form device unstable properties.
The preferred embodiments of the present invention are above are only, any restriction effect is not played to the present invention.Belonging to any
Those skilled in the art, not departing from the range of technical scheme, to the invention discloses technical scheme and
Technology contents make the variation such as any type of equivalent or modification, belong to the content without departing from technical scheme, still
Belong within protection scope of the present invention.
Claims (10)
1. a kind of preparation method of Split-gate flash memory, it is characterised in that including step：
Semiconductor substrate is provided, floating gate layer and floating boom mask layer, the floating boom mask are sequentially formed with the Semiconductor substrate
Layer is provided with multiple grooves, and the groove exposes the floating gate layer；
One layer of side wall sacrifice layer is formed in the floating gate layer and floating boom mask layer surface；
One layer of side wall layer is formed in the side wall sacrificial layer surface；
The side wall layer and side wall sacrifice layer are sequentially etched, side wall and side wall sacrifice layer are retained in the groove；
The etching removal floating boom mask layer and the side wall sacrifice layer positioned at side wall side wall, expose the part positioned at side wall
The floating gate layer of sacrifice layer bottom；
Etch the floating gate layer and form floating boom.
2. the preparation method of Split-gate flash memory as claimed in claim 1, it is characterised in that the side wall sacrifice layer material
It is silicon nitride.
3. the preparation method of Split-gate flash memory as claimed in claim 1, it is characterised in that the floating boom mask layer material
It is silicon nitride.
4. the preparation method of Split-gate flash memory as claimed in claim 1, it is characterised in that institute is removed using wet etching
State floating boom mask layer and the side wall sacrifice layer positioned at side wall side wall.
5. the preparation method of Split-gate flash memory as claimed in claim 1, it is characterised in that the material of the side wall is oxygen
SiClx.
6. the preparation method of Split-gate flash memory as claimed in claim 1, it is characterised in that shape in the Semiconductor substrate
Into there is layer of oxide layer, the floating gate layer is formed in the oxidation layer surface.
7. the preparation method of Split-gate flash memory as claimed in claim 1, it is characterised in that side wall in the groove it
Between be formed with control gate.
8. the preparation method of Split-gate flash memory as claimed in claim 7, it is characterised in that the control gate surface is formed
There is control gate protective layer.
9. the preparation method of Split-gate flash memory as claimed in claim 7, it is characterised in that the material of the control gate is
Polysilicon.
10. the preparation method of Split-gate flash memory as claimed in claim 1, it is characterised in that the material of the floating gate layer
It is polysilicon.
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| CN201710078924.7A CN106847818B (en) | 2017-02-14 | 2017-02-14 | Preparation method of split-gate flash memory |
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| CN201710078924.7A CN106847818B (en) | 2017-02-14 | 2017-02-14 | Preparation method of split-gate flash memory |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807399A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | The preparation method of flash memory |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1459846A (en) * | 2002-05-20 | 2003-12-03 | 台湾积体电路制造股份有限公司 | Manufacturing method of composite silicon crystal clearance wall for separating grid electrode quick flashing storage unit |
| CN102104044A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory and manufacturing method thereof |
| CN104538367A (en) * | 2014-12-30 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Mirror image split gate flash memory and forming method thereof |
| US20160254269A1 (en) * | 2015-02-27 | 2016-09-01 | Silicon Storage Technology, Inc. | Array Of Non-volatile Memory Cells With ROM Cells |
-
2017
- 2017-02-14 CN CN201710078924.7A patent/CN106847818B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1459846A (en) * | 2002-05-20 | 2003-12-03 | 台湾积体电路制造股份有限公司 | Manufacturing method of composite silicon crystal clearance wall for separating grid electrode quick flashing storage unit |
| CN102104044A (en) * | 2009-12-17 | 2011-06-22 | 中芯国际集成电路制造(上海)有限公司 | Separate gate flash memory and manufacturing method thereof |
| CN104538367A (en) * | 2014-12-30 | 2015-04-22 | 上海华虹宏力半导体制造有限公司 | Mirror image split gate flash memory and forming method thereof |
| US20160254269A1 (en) * | 2015-02-27 | 2016-09-01 | Silicon Storage Technology, Inc. | Array Of Non-volatile Memory Cells With ROM Cells |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108807399A (en) * | 2018-06-08 | 2018-11-13 | 上海华虹宏力半导体制造有限公司 | The preparation method of flash memory |
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