CN106783862B - STT-MRAM memory cell - Google Patents
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- CN106783862B CN106783862B CN201611201099.7A CN201611201099A CN106783862B CN 106783862 B CN106783862 B CN 106783862B CN 201611201099 A CN201611201099 A CN 201611201099A CN 106783862 B CN106783862 B CN 106783862B
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- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/20—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the three-dimensional arrangements, e.g. with cells on different height levels
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- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
- H10B53/30—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors characterised by the memory core region
Abstract
The invention discloses an STT-MRAM storage unit, which comprises a transistor and an MTJ unit; the transistor is established on the substrate, and the drain electrode of the transistor is in drain contact with the MTJ unit through the metal wire; the MTJ unit comprises an inner electrode, and a seed layer, a ferromagnetic pinning layer, a nonmagnetic barrier layer, a ferromagnetic free layer and an outer electrode which are wrapped on the periphery of the inner electrode; the metal wire is connected with the inner electrode; the seed layer, the ferromagnetic pinning layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode are not parallel to the plane of the substrate; the seed layer, the ferromagnetic pinning layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode are arranged at intervals with the metal wire. The MTJ unit in the invention is arranged in a manner that the thermal stability coefficient delta is weakened into linear change along with the square change relation of the original plane structure size, can be compensated by height, and is beneficial to the miniaturization of the MTJ. The invention can effectively utilize space, ensure good thermal stability, improve storage density, provide various storage modes and have application prospect on the storage below 20nm technical nodes.
Description
Technical Field
The invention relates to the technical field of STT-MRAM (Spin Transfer Torque-Magnetic Random Access Memory) Memory devices, in particular to a Magnetic Tunnel Junction (MTJ) structure and a preparation method of the STT-MRAM device.
Background
Magnetic Random Access Memory (MRAM) is an advanced memory technology that can replace traditional memory. Has good non-volatility, namely no data loss after power failure, good thermal stability, over ten years of storage information conservation, and good read-write stability, and the read-write frequency can reach 1016Next, the process is carried out. Early MRAMs used a current to generate an external magnetic field to change the magnetic state of the free layer, which limited miniaturization due to the large write current required and high power consumption. Spin transfer torque magnetic random access memory (STT-MRAM) in which the magnetic state is controlled by spin current can effectively avoid such a situation, and is of great significance for miniaturization of memory devices.
The read and write functions of STT-MRAM memory devices are controlled by their memory cells and spin-polarized currents, and typical STT-MRAM memory devices consist of MTJ memory cells and selective transistors. The MTJ memory cell further includes a ferromagnetic pinned layer, an insulating tunneling layer, and a ferromagnetic free layer. With the progress of semiconductor technology, the structure of the currently existing MTJ is a planar structure, that is, the planes of all layers of the MTJ are parallel to the surface of a wafer substrate, and current flows in the direction perpendicular to the film surface. As nanotechnology nodes continue to scale down, the dimensions of various portions of MTJ cells continue to decrease, and their thermal stability is greatly challenged. The thermal stability of the MTJ can be characterized by the equation Δ KAt/kT. Wherein Δ represents a thermal stability factor, K represents an anisotropy constant, a represents an area of the magnetic free layer, T represents a thickness of the free layer, K is a boltzmann constant, and T is a temperature [ a.v. khvalkovskiy.j.phys.d: appl.phys.2013 ]. It is generally required that the storage unit has a thermal stability for more than 10 years, i.e. the thermal stability factor Δ must be kept around 60-70. As device dimensions decrease, i.e., MTJ area a shrinks, the value of thermal stability Δ needs to be maintained by increasing the anisotropy constant K or/and the thickness t of the film. According to the above formula of thermal stability, as the device size decreases, the free layer area a will decrease in square with the device size, where Kt must increase in square with the device size to ensure thermal stability. On the one hand, the anisotropy constant K is usually determined by the interface process and material type of the free layer and the oxide barrier layer of the magnetic thin film, and it is difficult to adjust the anisotropy constant K in the MTJ, and it is technically difficult to increase K to compensate according to the decrease of the MTJ size. On the other hand, increasing Δ by increasing the thickness t of the free layer is also inefficient because Δ varies linearly with t much slower than the square of the MTJ size, and the switching current density is proportional to the film thickness t, increasing t increases the write energy dramatically [ a.goyal.appl.phys.lett.1996], so compensation by adjusting t is not feasible. Therefore, under the small-sized 10nm technology node, new design of the MTJ structure is required to maintain good thermal stability of the MTJ.
Disclosure of Invention
The present invention is directed to an STT-MRAM memory cell to solve the above-mentioned problems.
In order to achieve the purpose, the invention adopts the following technical scheme:
an STT-MRAM memory cell comprising a transistor and an MTJ cell; the transistor is established on the substrate, and the drain electrode of the transistor is in drain contact with the MTJ unit through the metal wire; the MTJ unit comprises an inner electrode, and a seed layer, a ferromagnetic pinning layer, a nonmagnetic barrier layer, a ferromagnetic free layer and an outer electrode which are wrapped on the periphery of the inner electrode; the metal wire is connected with the inner electrode; the seed layer, the ferromagnetic pinning layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode are not parallel to the plane of the substrate; the seed layer, the ferromagnetic pinning layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode are arranged at intervals with the metal wire.
Further, the MTJ unit includes, in order from the inside to the outside, an inner electrode, a seed layer, a ferromagnetic pinned layer, a nonmagnetic barrier layer, a ferromagnetic free layer, and an outer electrode, or includes, in order from the inside to the outside, an inner electrode, a seed layer, a ferromagnetic free layer, a nonmagnetic barrier layer, a ferromagnetic pinned layer, and an outer electrode.
Further, the transistor comprises a source electrode, a drain electrode and a grid electrode laminated layer; the source electrode and the drain electrode are arranged on the substrate at intervals and are connected through a grid laminated layer; the grid laminated layer is connected with the first word line, and the drain electrode and the MTJ unit reach drain contact through a metal line.
Furthermore, the MTJ unit is a rectangular parallelepiped columnar structure.
Furthermore, the metal wire and the inner electrode are of an integrated structure, or the inner electrode is prepared on the metal wire.
Further, the MTJ cell behaves from inside to outside as: the inner electrode is in a cuboid columnar structure, the ferromagnetic pinning layer conformally surrounds the inner electrode along the side face of the cuboid inner electrode, the nonmagnetic barrier layer conformally surrounds the ferromagnetic pinning layer along the side face, the ferromagnetic free layer conformally surrounds the nonmagnetic barrier layer along the side face, and the outer side of the ferromagnetic free layer is an outer electrode; alternatively, the MTJ cell behaves as: the inner electrode is in a cuboid columnar structure, the ferromagnetic free layer conformally surrounds the inner electrode along the side face of the cuboid inner electrode, the nonmagnetic barrier layer conformally surrounds the ferromagnetic free layer along the side face, the ferromagnetic pinning layer conformally surrounds the nonmagnetic barrier layer along the side face, and the outer side of the ferromagnetic pinning layer is an outer electrode.
Furthermore, the upper part of the MTJ unit is a dielectric protective layer which covers the seed layer, the ferromagnetic pinning layer, the nonmagnetic barrier layer and the ferromagnetic free layer, and the external electrode part is exposed outside the dielectric protective layer.
Further, the MTJ top dielectric cap is made of Al2O3CrO and TaO with a thickness of 0.5-2 nm.
Furthermore, an insulating medium wrapping the transistor and the MTJ unit is arranged on the substrate; the external electrode of the MTJ cell exposed outside the dielectric protective layer is connected to a second word line.
Furthermore, the seed layer, the ferromagnetic pinning layer, the nonmagnetic barrier layer, the ferromagnetic free layer and the outer electrode are all vertical to the plane of the substrate.
Furthermore, the length of the inner electrode of the MTJ structure is 1-10nm, the width is 1-10nm, and the height is 1-100 nm; the thickness of the seed layer is 0.5-3 nm; the thickness of the ferromagnetic pinning layer is 0.5-15 nm; the thickness of the barrier layer is 0.5-5 nm; the thickness of the free layer is 1-10 nm; the thickness of the external electrode is 0.5-10 nm.
Further, the material of the inner electrode is Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf, Ta, V, Cr, W, Nb, poly-Si and alloy or semiconductor material thereof;
the seed layer is made of NiFe, NiCr, NiFeCr, Cu, Ti, TiN, Ta, Ru or Rh;
the ferromagnetic pinning layer consists of an antiferromagnetic film and a ferromagnetic film, or consists of a hard ferromagnetic film and a ferromagnetic film, or consists of an antiferromagnetic layer, a coupling layer and a ferromagnetic film, or consists of a hard ferromagnetic film, a coupling layer and a ferromagnetic film; the material for preparing the antiferromagnetic film is a multilayer film formed by IrMn, RhMn, RuMn, OsMn, FeMn, FeMnCr, FeMnRh, CrPtMn, TbMn, NiMn, PtMn, PtPdMn, NiO, CoNiO alloy and alloy containing the elements; the material for preparing the hard ferromagnetic film is Co, Fe, Pt, Pd and alloy formed by two or more elements of Co, Fe, Pt and Pd, or CoPtB alloy; the ferromagnetic film is prepared from transition metals Fe, Co, Ni and alloy thereof, alloy consisting of B, Zr, Pt, Pd, Hf, Ta, V, Zr, Ti, Cr, W, Mo and Nb, and multilayer film formed by the elements or the alloy;
the material for preparing the ferromagnetic free layer is transition metal Fe, Co, Ni and alloy thereof, alloy consisting of B, Zr, Pt, Pd, Hf, Ta, V, Zr, Ti, Cr, W, Mo and Nb, and multilayer film formed by the elements or the alloy;
the nonmagnetic barrier layer is made of MgO or Al2O3、Al2MgO4、ZnO、ZnMgO2、TiO2、HfO2、TaO2、Cd2O3、ZrO2、Ga2O3、Sc2O3、V2O5、Fe2O3、Co2O3NiO and one or more of the above compounds; or the nonmagnetic barrier layer is made of nitride;
the outer electrode material is Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf, Ta, V, Cr, W, Nb, poly-Si and alloy or semiconductor material thereof.
Compared with the prior art, the invention has the following beneficial effects:
in the STT-MRAM storage unit, the MTJ unit is designed to be vertical or not parallel to the substrate, namely, each layer of the MTJ is vertical to the surface of the round crystal substrate, each layer is a closed rectangular parallelepiped columnar structure in a shape like a Chinese character 'hui', and the length and the width of the MTJ unit are respectively 5-50nm and 1-100 nm. In the structure provided by the invention, as the size of the MTJ is reduced, the thermal stability coefficient Δ is 2LK (a + b) t/kT, where a, b, and L are the length, width, and height of the MTJ respectively, and then Δ will vary linearly with the length, width a, and b of the planar dimension, and also vary linearly with the height. The MTJ structure can reduce the square variation of delta along with the original plane structure size into linear variation, can use height compensation, and is beneficial to the miniaturization of the MTJ unit structure. The pattern produced by the Self-aligned Double Patterning (SADP) technique, which is well established in the semiconductor industry today, is a rectangular structure [ Zigan Xiao, IEEE, IEEE Transactions on Computer-aid Design of Integrated Circuits and Systems,2013], and thus the square MTJ cell structure Design in the present invention can be easily implemented by the SADP technique.
The middle of the MTJ structure is a rectangular parallelepiped columnar inner electrode, transversely extends from inside to outside along the side surface of the inner electrode to the periphery in a shape-preserving manner, and sequentially comprises a ferromagnetic pinning layer, a nonmagnetic barrier layer, a ferromagnetic free layer and an outer electrode; or a ferromagnetic free layer, a nonmagnetic barrier layer, a ferromagnetic pinning layer and an external electrode. In this MTJ structure, free electrons generate a spin-polarized current in the lateral direction from the internal electrode through the pinned layer and then through the barrier layer to the free layer, causing the magnetization direction of the free layer to be switched to the electron spin polarization direction, so that the magnetic moments of the two magnetic layers are in parallel, i.e., data "1". Free electrons are generated from the outer electrode in the transverse direction, pass through the free layer, then pass through the barrier layer, reach the pinning layer, pass through electrons with the polarization direction consistent with that of the pinning layer, reflect back with opposite polarization and then act on the free layer, and the magnetic moments of the two magnetic layers are in an antiparallel state, namely data 0.
A rectangular columnar inner electrode of a magnetic storage unit of the STT-MRAM is formed on a bottom electrode, a rectangular columnar MTJ structure is transversely prepared along the side surface of the inner electrode, and an outer electrode is prepared along the side surface. The invention also comprises a preparation method of the inner electrode, which comprises the steps of preparing a cuboid columnar inner electrode on a metal wire, covering a layer of insulating medium, exposing a part of the inner electrode, preparing an MTJ structure along the side surface of the exposed part, wherein the specific MTJ structure comprises a seed layer, a pinned layer, a barrier layer and a free layer or the seed layer, the free layer, the barrier layer and the pinned layer from inside to outside uniformly along the side surface of the inner electrode, and preparing the outer electrode outside the MTJ.
The memory cell of the invention is represented by a cuboid columnar three-dimensional Magnetic Tunnel Junction (MTJ) structure, the length and the width of the memory cell are respectively 5-50nm, and the height of the memory cell is 1-100 nm; the appearance of the three-dimensional Magnetic Tunnel Junction (MTJ) structure is a cuboid columnar structure, wherein a pinning layer (free layer), a barrier layer and the free layer (pinning layer) surround the side surface of an inner electrode to form the three-dimensional MTJ structure. The structure has the advantages of effectively utilizing space, ensuring good thermal stability, improving storage density, providing various storage modes and having application prospect on the storage below 20nm technical nodes.
Drawings
The drawings are included to aid in the description of the embodiments and are intended to be illustrative only and not limiting.
FIG. 1 is a schematic side view of a three-dimensional STT-MRAM memory cell structure according to an embodiment of the invention;
FIG. 2 is a schematic diagram of an MTJ 200; wherein, fig. 2(a) is a top view, and fig. 2(b) is a cross-sectional schematic view;
FIG. 3 is a schematic diagram of an MTJ inner electrode according to an embodiment of the invention; wherein, fig. 3(a) is a top view, and fig. 3(b) is a cross-sectional schematic view;
FIGS. 4-13 are schematic views illustrating the detailed fabrication process of the MTJ cell proposed in the embodiments of the present invention.
FIG. 14 is a schematic view of a second form of MTJ 200; wherein, fig. 14(a) is a top view, and fig. 14(b) is a cross-sectional view;
FIG. 15 is a schematic diagram of a second alternative MTJ200 structure;
FIGS. 16-19 are schematic diagrams illustrating a method for fabricating an MTJ inner electrode according to embodiments of the invention;
FIGS. 20-22 are schematic diagrams of another fabrication method of MTJ inner electrode proposed in the embodiments of the present invention.
Detailed Description
Aspects of embodiments of the invention are disclosed in the following description and related drawings directed to specific examples of the invention. Alternate embodiments are contemplated without departing from the scope of the invention. In other instances, well known techniques have not been described in detail in order not to obscure the present invention. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration. Any example described as "exemplary" herein is not necessarily to be construed as preferred or advantageous over other embodiments. Likewise, the term "embodiments of the invention" does not require that all embodiments of the invention include the described features, advantages, or modes of operation.
The following describes in further detail embodiments of the present invention with reference to the accompanying drawings. The invention describes a magnetic memory cell structure of spin transfer torque memory STT-MRAM.
An STT-MRAM memory cell comprises a Magnetic Tunnel Junction (MTJ) structure unit (Magnetic Tunnel Junction), the MTJ unit comprises a pinned layer, a barrier layer and a free layer, and the geometrical structure of the MTJ unit is a rectangular column. Writing and modifying of information is accomplished by changing the direction of the magnetic moment of the free layer in the MTJ cell by a spin-polarized current. The change in magnetic moment causes a change in the resistance of the MTJ element, and the difference in resistance states can be used to program or erase information in the memory element.
Example 1
FIG. 1 is a diagram of a STT-MRAM memory cell architecture. Comprising a transistor 101 and MTJ cell 200. Transistor 101 is built on substrate 100 and includes source 103a, drain 103b and gate stack 102. The gate stack 102 is connected to a word line 105, the drain 103b is in drain contact with the MTJ cell 200 via a metal line 106, and the source 103a is in source contact with the source node region 104. The MTJ cell 200 is connected to a word line 107. The MTJ cell 200 is formed with a tunneling layer between the pinned layer and the free layer, and is perpendicular to the upper plane of the metal line 106.
Various technical descriptions relating thereto indicate that fabricating the MTJ cell can be accomplished by conformal deposition techniques, such as Atomic Layer Deposition (ALD) techniques to fabricate the MTJ cell structure. Fig. 1-2 disclose detailed structures of inventions relating to magnetic recording elements. The first invention is a transistor 101, and the transistor 101 is fabricated on a substrate 100 and includes a source 103a, a drain 103b, and a gate stack 102. The gate stack 102 is connected to a word line 105, the drain 103b is in drain contact with the magnetic recording element 200 via a metal line 106, and the source 103a is in source contact with a source node region 104. The second part of the invention is an MTJ cell 200, located above the transistor 101 and connected to the transistor 101 through 106. The metal line 106 is connected to the inner electrode 204, wherein the inner electrode 204 is perpendicular to the metal line 106 and the inner electrode 204 is rectangular parallelepiped, and the bottom of the inner electrode 204 is buried in the inner electrode 206. The MTJ structure is prepared by conformal deposition technology on the side surface of the exposed part of the inner electrode 204, and the seed layer 212, the pinning layer 203, the barrier layer 202 and the free layer 201 are arranged from inside to outside in sequence. Outside the free layer is an outer electrode 205. Above the MTJ cell 200 is a dielectric cap layer 207. Fig. 2(a) is a top view of the MTJ cell 200.
In the MTJ cell of fig. 2, electrons are spin-polarized by the pinned layer 203 and then pass through the barrier layer 202 to the free layer 201, causing the magnetic moment direction of the free layer 201 to change. This process is known as Spin-transfer Torque Switching (STS), which can transfer information from the pinned layer 203 to the free layer 201 via a Spin-polarized current. In this process, the pinned layer 203 acts as spin filter, the spin filtered electrons tunnel through the barrier layer 202, and the spin electrons then act on the magnetic moment of the free layer 201, changing the state of the MTJ from anti-parallel "1" to parallel "0". Conversely, reversing the current flow can change the state of the MTJ from parallel "0" to anti-parallel "1". By again using transistor 101 as a select device, binary stored information can be written or altered on the STT-MRAM chip by controlling the current.
FIG. 3 is a schematic diagram of the preparation of an MTJ inner electrode according to an embodiment of the present invention. Firstly, a layer of metal electrode is prepared by utilizing magnetron sputtering or Atomic Layer Deposition (ALD), and the thickness of the metal electrode is about 10-50 nm. The metal layer is then etched according to fig. 3(a) using ion beam etching or electron beam etching. During etching, the metal layer is not completely etched, and the inverted T-shaped electrode shown in FIG. 3(b) is obtained. Finally, an insulating layer is plated, and the part which is not etched at the bottom is buried under the insulating layer. The exposed rectangular parallelepiped columnar metal is the internal electrode 204.
Fig. 4-12 illustrate the specific fabrication process of the MTJ cell proposed in the embodiments of the present invention. A seed layer 212 is prepared on the prepared inner electrode, and a seed layer is prepared by utilizing magnetron sputtering or Atomic Layer Deposition (ALD) technology as shown in fig. 4. The seed layer 212 is then obtained by ion beam etching or electron beam etching as shown in FIG. 5. Thereafter, the ferromagnetic pinned layer 201, the insulating barrier layer 202, and the free layer 203 are prepared by repeating magnetron sputtering or Atomic Layer Deposition (ALD) and ion beam etching or electron beam etching.
Example 2
FIG. 14 is a diagram of another three dimensional STT-MRAM memory cell architecture. Comprising a transistor 101 and MTJ cell 200. The transistor structure is the same as in embodiment 1. Partial adjustments are made at the MTJ cell 200: the corresponding structure of MTJ is changed from inner to outer into inner electrode, free layer, barrier layer, pinning layer and outer electrode. The materials used and the preparation methods for the respective layer structures were similar to those in example 1. The specific structure of the MTJ is shown in FIG. 15.
Two methods for fabricating the electrode 204 in the MTJ 200.
In the first manufacturing method, the inner electrode 204 is directly manufactured on the substrate 106 by ion beam etching or electron beam etching, as shown in fig. 16 and 17. A layer of insulating dielectric 206 is then prepared on the basis of fig. 17 by magnetron sputtering or Atomic Layer Deposition (ALD) to obtain the structure of fig. 18. The insulating medium around 204 is removed by ion beam etching or electron beam etching to obtain the device as shown in fig. 19, and then the device is prepared by the process of preparing MTJ in embodiments 1 and 2.
In a second fabrication method, an insulating dielectric 206 is first deposited on the substrate 106 by magnetron sputtering or Atomic Layer Deposition (ALD), as shown in FIG. 20. And etching a rectangular parallelepiped groove on the insulating medium 206 by using an ion beam etching or electron beam etching technology, wherein the depth of the groove reaches 106. Then, the grooves are filled with the material for forming the inner electrode 204 by magnetron sputtering or Atomic Layer Deposition (ALD), as shown in fig. 21. The insulating medium around the inner electrode 204 is etched into the structure as shown in fig. 22 by using ion beam etching or electron beam etching technology, and the required electrode is obtained. The device was then prepared by the procedure for the preparation of the MTJ in examples 1 and 2.
Claims (2)
1. A method of fabricating an STT-MRAM memory cell, the STT-MRAM memory cell comprising a transistor (101) and an MTJ cell (200);
the transistor (101) is established on the substrate (100), and the drain electrode (103b) of the transistor (101) is in drain contact with the MTJ unit (200) through the metal wire (106); the transistor (101) comprises a source (103a), a drain (103b) and a gate stack (102); the source electrode (103a) and the drain electrode (103b) are arranged on the substrate (100) at intervals, and the source electrode (103a) and the drain electrode (103b) are connected through the grid laminated layer (102); the gate stack (102) is connected to a first word line (105), and the drain (103b) and the MTJ cell (200) are in drain contact via a metal line (106);
the MTJ unit (200) comprises an inner electrode (204), a seed layer (212) wrapping the periphery of the inner electrode (204), a ferromagnetic pinning layer (203), a nonmagnetic barrier layer (202), a ferromagnetic free layer (201) and an outer electrode (205) from inside to outside in sequence, wherein the ferromagnetic pinning layer (203) and the ferromagnetic free layer (201) can exchange sequences;
the seed layer (212), the ferromagnetic pinning layer (203), the nonmagnetic barrier layer (202), the ferromagnetic free layer (201) and the outer electrode (205) are not parallel to the plane of the substrate (100); the seed layer (212), the ferromagnetic pinning layer (203), the nonmagnetic barrier layer (202), the ferromagnetic free layer (201) and the outer electrode (205) are arranged at intervals with the metal wire (106);
the MTJ unit (200) is positioned above the transistor (101) and is connected with the transistor (101) through a metal wire (106); the metal wire (106) is connected with the inner electrode (204), wherein the inner electrode (204) is vertical to the metal wire (106) and the inner electrode (204) is in a cuboid column shape; fabricating the MTJ cell by conformal deposition techniques on the lateral surface of the exposed portion of the inner electrode (204);
the length of the inner electrode of the MTJ structure is 1-10nm, the width is 1-10nm, and the height is 1-100 nm; the thickness of the seed layer is 0.5-3 nm; the thickness of the ferromagnetic pinning layer is 0.5-15 nm; the thickness of the barrier layer is 0.5-5 nm; the thickness of the free layer is 1-10 nm; the thickness of the external electrode is 0.5-10 nm;
the preparation method comprises the following steps:
preparation process of MTJ unit (200): preparing a seed layer on the prepared inner electrode, and etching to obtain the required seed layer (212); then, repeatedly utilizing an atomic layer deposition technology and ion beam etching or electron beam etching to prepare a ferromagnetic pinning layer, a nonmagnetic barrier layer (202) and a ferromagnetic free layer;
the preparation method of the inner electrode (204) comprises the following steps: covering a layer of insulating medium (206) on the metal wire (106) by utilizing an atomic layer deposition technology; etching a cuboid groove on the insulating medium (206) by utilizing an ion beam etching or electron beam etching technology, wherein the depth of the cuboid groove reaches the metal wire (106); then, filling the groove with a material for preparing the inner electrode (204) by utilizing an atomic layer deposition technology; then etching the insulating medium at the periphery of the inner electrode (204) to obtain the inner electrode (204); or, firstly, preparing a layer of metal electrode by utilizing an atomic layer deposition technology; then etching the metal electrode, and during etching, incompletely etching the metal electrode to obtain an inverted T-shaped electrode; finally, plating an insulating layer, and burying the part which is not etched at the bottom under the insulating layer; the exposed cuboid columnar metal is an inner electrode (204);
the MTJ cell behaves from inside to outside as: the inner electrode is in a cuboid columnar structure, the ferromagnetic pinning layer conformally surrounds the inner electrode along the side face of the cuboid inner electrode, the nonmagnetic barrier layer conformally surrounds the ferromagnetic pinning layer along the side face, the ferromagnetic free layer conformally surrounds the nonmagnetic barrier layer along the side face, and the outer side of the ferromagnetic free layer is an outer electrode; alternatively, the MTJ cell behaves as: the inner electrode is in a cuboid columnar structure, the ferromagnetic free layer conformally surrounds the inner electrode along the side face of the cuboid inner electrode, the nonmagnetic barrier layer conformally surrounds the ferromagnetic free layer along the side face, the ferromagnetic pinning layer conformally surrounds the nonmagnetic barrier layer along the side face, and the outer side of the ferromagnetic pinning layer is an outer electrode;
the upper part of the MTJ unit is a dielectric protective layer (207), the dielectric protective layer (207) covers the seed layer (212), the ferromagnetic pinning layer (203), the nonmagnetic barrier layer (202) and the ferromagnetic free layer (201), and the external electrode (205) is partially exposed outside the dielectric protective layer (207);
an insulating medium wrapping the transistor (101) and the MTJ unit (200) is arranged on the substrate (100); an external electrode (205) of the MTJ cell (200) exposed outside the dielectric protection layer (207) is connected to the second word line (107);
the seed layer (212), the ferromagnetic pinning layer (203), the nonmagnetic barrier layer (202), the ferromagnetic free layer (201) and the outer electrode (205) are all vertical to the plane of the substrate (100).
2. The method of claim 1, wherein the inner electrode is made of Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf, Ta, V, Cr, W, Nb, their alloys, or a semiconductor material;
the seed layer is made of NiFe, NiCr, NiFeCr, Cu, Ti, TiN, Ta, Ru or Rh;
the ferromagnetic pinning layer consists of an antiferromagnetic film and a ferromagnetic film, or consists of a hard ferromagnetic film and a ferromagnetic film, or consists of an antiferromagnetic layer, a coupling layer and a ferromagnetic film, or consists of a hard ferromagnetic film, a coupling layer and a ferromagnetic film;
the antiferromagnetic film is a single-layer film or a multi-layer film, and the material of each film is IrMn, RhMn, RuMn, OsMn, FeMn, FeMnCr, FeMnRh, CrPtMn, TbMn, NiMn, PtMn, PtPdMn, NiO or CoNiO;
the material for preparing the hard ferromagnetic film is Co, Fe, Pt, Pd and alloy formed by two or more elements of Co, Fe, Pt and Pd, or CoPtB alloy;
the ferromagnetic film is a single-layer film or a multi-layer film, and the material of each film is transition metal Fe, Co, Ni and alloy thereof, or alloy consisting of Fe, Co, Ni, B, Zr, Pt, Pd, Hf, Ta, V, Zr, Ti, Cr, W, Mo and Nb;
the ferromagnetic free layer is a single-layer film or a multi-layer film, and the material of each film is transition metal Fe, Co, Ni and alloy thereof, or alloy consisting of Fe, Co, Ni, B, Zr, Pt, Pd, Hf, Ta, V, Zr, Ti, Cr, W, Mo and Nb;
the nonmagnetic barrier layer is made of MgO or Al2O3、Al2MgO4、ZnO、ZnMgO2、TiO2、HfO2、TaO2、Cd2O3、ZrO2、Ga2O3、Sc2O3、V2O5、Fe2O3、Co2O3NiO and one or more of the above compounds; or the nonmagnetic barrier layer is made of nitride;
the outer electrode material is Au, Ag, Cu, Nd, Ti, Al, Ru, Rh, Mo, Zr, Hf, Ta, V, Cr, W, Nb and their alloys, or semiconductor material.
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