CN110544498B

CN110544498B - Magnetic random access memory using bow-shaped word line

Info

Publication number: CN110544498B
Application number: CN201810519948.6A
Authority: CN
Inventors: 戴瑾
Original assignee: Shanghai Ciyu Information Technologies Co Ltd
Current assignee: Shanghai Ciyu Information Technologies Co Ltd
Priority date: 2018-05-28
Filing date: 2018-05-28
Publication date: 2021-03-16
Anticipated expiration: 2038-05-28
Also published as: CN110544498A

Abstract

The invention provides a magnetic random access memory using an arched word line, wherein an array is formed by a unit structure, and the unit structure at least comprises an active region bearing layer, an arched word line segment, a first contact column, a second contact column and a third contact column; the first contact column, the third contact column and the second contact column are sequentially arranged on the active region bearing layer; the bow-shaped character line section passes through the area among the first contact column, the second contact column and the third contact column, so that the first contact column and the second contact column are positioned on one side of the bow-shaped character line section, the third contact column is positioned on the other side of the bow-shaped character line section, and an oxidation layer is arranged below the bow-shaped character line section. The invention has the beneficial effects that: (1) the peripheral circuit is simple in design; (2) only two rows share the source line, so that the speed is high; (3) in the active region with the same area, the active region bears larger current and provides faster speed; (4) the cost is reduced by using one layer of metal, the mutual inductance capacitance is reduced, and the speed is improved.

Description

Magnetic random access memory using bow-shaped word line

Technical Field

The invention relates to a storage device, in particular to a magnetic random access memory using an arched word line, and belongs to the technical field of integrated circuit memory chips.

Background

MRAM is a new memory and storage technology, can be read and written randomly as SRAM/DRAM, and can permanently retain data after power failure as Flash memory. The chip has good economy, and the silicon chip area occupied by unit capacity has great advantages compared with SRAM, NOR Flash frequently used in the chips and embedded NOR Flash. Its performance is also quite good, the read-write time delay is close to the best SRAM, and the power consumption is the best in various memory and storage technologies. Also MRAM is not compatible with standard CMOS semiconductor processes like DRAM and Flash, and MRAM can be integrated with logic circuits in one chip.

Each memory cell of the MRAM consists of a magnetic tunnel junction and a MOS transistor. Each memory cell needs to be connected to three wires: the grid electrode of the MOS tube is connected to a word line of the chip and is responsible for switching on or switching off the unit; one pole (source or drain) of the MOS transistor is connected to the source line, the other pole (drain or source) of the MOS transistor is connected to one pole of the magnetic tunnel junction, and the other pole of the magnetic tunnel junction is connected to the bit line.

As shown in fig. 1, an MRAM chip is composed of one or more arrays of MRAM memory cells, each array having a number of external circuits, including: a row address decoder for changing a received address to a selection of a word line; a column address decoder for changing a received address to a selection of bit lines; a read/write controller for controlling a read (measure) write (add current) operation on the bit line; input and output control: for exchanging data with the outside.

The core of an MRAM chip is an array of memory cells, which have different layout methods.

(1) Bit line and source line layout in parallel, as shown in FIG. 2

The word lines 200 and bit lines 300 in an array must be vertical. A relatively simple design is that the bit line 300 and source line 400 are parallel. It is relatively easy to write, with the word line 200 raised to a high potential, turning on a row of memory cells, and then raising the potential on the bit line 300 or source line 400, respectively, as required for writing a 0 or 1 per cell. Although this method is simple, the board layout usually occupies a relatively large area, and the chip cost is high.

(2) Bit line and source line vertical layout, as shown in FIG. 3

The vertical layout of the bit lines 300 and the source lines 400 is beneficial to reducing the chip area occupied by each memory cell and reducing the cost. In fig. 3, the first word line 201, the second word line 202 and the source line 400 are parallel, and this design allows two adjacent NMOS transistors to share one source, which greatly saves area. But the control of the write operation is more complicated.

In the various layouts of the currently known MRAM, the source and bit lines must be perpendicular if the density is to be high. In this case, the design is rather complicated. Of the various designs, the preferred design is slower because of the need for column-shared source lines.

In US patent US9653137B2, another idea is proposed. The source and bit lines are still parallel, but each two columns share a source line. The reduced source lines enable greater density while maintaining the compactness and high speed characteristics of the peripheral circuitry. Fig. 13 is a schematic illustration, and fig. 14 is a specific memory cell layout design. As can be seen from fig. 14, the

source lines

130 and 132 still occupy some space between the active areas of the two columns, reducing the density.

Disclosure of Invention

In view of the above-mentioned drawbacks of the prior art, the technical problems to be solved by the present invention are: a scheme that a source line and a bit line are parallel and the density is high is provided, and the scheme is attractive in many application scenarios.

A unit structure of a magnetic random access memory at least comprises an active region bearing layer, a segment of a bow-shaped character line, a first contact column, a second contact column and a third contact column; the first contact column, the third contact column and the second contact column are sequentially arranged on the active region bearing layer; the bow-shaped character line section passes through the area among the first contact column, the second contact column and the third contact column, so that the first contact column and the second contact column are positioned on one side of the bow-shaped character line section, the third contact column is positioned on the other side of the bow-shaped character line section, and an oxidation layer is arranged below the bow-shaped character line section.

Furthermore, the segment of the bow-shaped character line consists of a first segment, a second segment, a third segment, a fourth segment and a fifth segment which are connected end to end, wherein the first segment and the fifth segment are positioned on the same straight line and are parallel to the third segment. The included angle of the joint of the second section and the third section is a first obtuse angle, and the included angle of the joint of the fourth section and the third section is a second obtuse angle. Preferably, the first obtuse angle ranges from 120 degrees to 160 degrees, and the second obtuse angle ranges from 120 degrees to 160 degrees.

Alternatively, the second section is perpendicular to the third section and the fourth section is perpendicular to the third section.

Furthermore, the active area bearing layer is concave, the first contact column and the second contact column are respectively arranged at the positions close to the left and right two protruded corner tops of the concave, and the outer edge of the third section exceeds the side line of the concave position of the concave.

Furthermore, the unit structure also comprises a first bit line segment, a first magnetic tunnel junction, a second bit line segment, a second magnetic tunnel junction and a source line segment which are parallel to each other, wherein the source line segment is attached to the upper surface of the third contact column, and the source line segment is vertical to the third segment; the upper surface of the first contact column is connected with a first magnetic tunnel junction, and the other end of the first magnetic tunnel junction is connected with a first bit line segment; the upper surface of the second contact column is connected with a second magnetic tunnel junction, and the other end of the second magnetic tunnel junction is connected with a second bit line segment.

Furthermore, the active region bearing layer is provided with a first drain electrode, a second drain electrode and a source electrode, the first drain electrode is positioned below the first contact column, the second drain electrode is positioned below the second contact column, and the source electrode is positioned below the third contact column. The second section, the oxide layer, the first drain electrode and the source electrode are combined to form a first field effect transistor. The fourth segment, the oxide layer, the second drain electrode and the source electrode are combined to form a second field effect transistor.

A magnetic random access memory comprises a plurality of memory arrays formed by the unit structures, wherein all arch word line segments in each row of the memory arrays are connected end to form a complete word line, all first bit line segments in each column of the memory arrays are connected end to form a complete first bit line, all second bit line segments in each column are connected end to form a complete second bit line, and source line segments in each column are connected end to form a complete source line.

Compared with the design that the source line and the bit line are vertical, the invention has the following advantages:

(1) the peripheral circuit is simple in design.

(2) Only two columns share the source line, so that the speed is high.

(3) The word line advantage of the skew angle is greater. The inclined word lines can provide wider effective gates, larger current and faster speed in the active region with the same area.

(4) In the conventional layout, since the source line and the word line are parallel, the metal word line is generally added (for reducing resistance), and two layers of metal are required to be added. The invention only needs a layer of metal, on one hand, the cost is reduced, and on the other hand, the mutual inductance capacitance is reduced, which is also beneficial to improving the speed.

Compared with the published patent US9653137B2, the invention has the advantages that two columns share the same point of one source line, but the directions of the word line and the bit line are just opposite, and the better effect is achieved:

(1) the source line utilizes space more effectively, and overall density is higher, and the chip cost is lower.

(2) The arcuate word lines provide a greater drive current. Can help to increase speed or reduce density.

Drawings

FIG. 1 is a schematic diagram of an MRAM chip architecture;

FIG. 2 is a schematic diagram of a parallel layout of bit lines and source lines in a prior art memory cell array;

FIG. 3 is a schematic diagram of a bit line and source line vertical layout in a prior art memory cell array;

FIG. 4 is an enlarged partial schematic view of FIG. 3;

FIG. 5 is a schematic diagram of the shape of the active region in a preferred embodiment of the invention;

FIG. 6 is a diagram illustrating the shape of segments of a Chinese character 'Bow' word in accordance with a preferred embodiment of the present invention;

FIG. 7 is a schematic diagram of the structure of the bow-shaped word lines on the active area in a preferred embodiment of the present invention;

fig. 8 is a top view of the arcuate word lines of fig. 7 arranged over an active area;

FIG. 9 is a schematic diagram of the layout of word lines over active areas in another preferred embodiment of the present invention;

FIG. 10 is a schematic diagram of word lines, bit lines, and source lines in accordance with a preferred embodiment of the present invention;

FIG. 11 is a top view of the word lines, bit lines, and source lines of FIG. 10;

FIG. 12 is a schematic diagram of a memory cell array structure according to a preferred embodiment of the invention.

FIG. 13 is a schematic diagram of a prior art magnetic random access memory;

FIG. 14 is a layout diagram of a memory cell of a magnetic random access memory according to the prior art.

Description of reference numerals: 100-an active region carrier layer, 101-a first contact pillar, 102-a second contact pillar, 103-a third contact pillar, 110-a field effect transistor, 120-a magnetic tunnel junction, 130-a source line, 132-a source line, 200-a word line, 201-a first word line, 202-a second word line, 210-an arcuate word line segment, 211-215-a segment of an arcuate word line segment, 220-a square word line segment, 300-a bit line, 301-a first bit line, 302-a second bit line, 400-a source line.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in detail below. It is to be noted that the drawings are in simplified form and are not to precise scale, which is provided for the purpose of facilitating and distinctly claiming the embodiments of the present invention.

Fig. 4 shows a structure of a magnetic random access memory in the prior art, in which an NMOS transistor is built on an N-type doped region on a P-type substrate, called Active Area (Active Area), and a word line 201 made of polysilicon is separated from a word line 202 into a source region and a drain region across an oxide layer. The source line 400 is typically implemented on a first layer of metal connected to the source region by a contact. The magnetic tunnel junction needs to be connected to the drain, so there must be a piece of metal on the first layer of metal that is connected to the drain region through a contact. The magnetic tunnel junction will be located above this layer of metal, and possibly higher, and connected to this piece of metal by multiple layers of vias and metal sheet.

Fig. 5 to 7 show the components and the combination of the cell structure of a magnetic random access memory. The unit structure is two memory units, and two NMOS tubes share a source electrode. Three contact columns, the middle of which is connected to the source line, and the left and right of which are respectively connected to the two magnetic tunnel junctions and then respectively connected to the bit lines.

The unit structure at least comprises an active region bearing layer 100, a segment 210 of a segment of a Chinese character 'bow', a first contact pillar 101, a second contact pillar 102 and a third contact pillar 103. The first contact pillar 101, the third contact pillar 103, and the second contact pillar 102 are sequentially disposed on the active region carrier layer 100. The segment 210 passes through the area between the first contact post 101, the second contact post 102, and the third contact post 103 such that the first contact post 101 and the second contact post 102 are located on one side of the segment 210 and the third contact post 103 is located on the other side of the segment 210.

In fig. 6 and 7, the segment 210 is composed of a first segment 211, a second segment 212, a third segment 213, a fourth segment 214, and a fifth segment 215 connected end to end. The first segment 211 and the fifth segment 215 are located on the same straight line, and are parallel to the third segment 213. The angle at the junction of the second section 212 and the third section 213 is an obtuse angle, and the angle at the junction of the fourth section 214 and the third section 213 is also an obtuse angle. Preferably, the two obtuse angles are both 120-160 degrees.

As shown in fig. 8, the active region carrier layer 100 is in a concave shape, the first contact pillar 101 and the second contact pillar 102 are respectively disposed near the left and right two protruded corner tops of the concave shape, and the outer edge of the third segment 213 exceeds the edge line of the concave depression. This is done to leave room for etching and to improve the yield of the product.

The square line segment in fig. 9 is square, and the square line segment 220 is also composed of five segments connected end to end, which is different from the above-mentioned bow line segment 210 in that the second segment and the third segment of the square line segment 220 are perpendicular, and the fourth segment and the third segment are perpendicular. The word line also serves as the gate of the field effect transistor, and the slant line is long in the same area. Thus, the arcuate wordline segment 210 is better than the square wordline segment 220, and can withstand greater current when used as a gate. The following is illustrated by the segment 210.

As shown in fig. 10 and 11, the cell structure further includes a first bit line segment 301, a first magnetic tunnel junction (not shown), a second bit line segment 302, a second magnetic tunnel junction (not shown), and a source line segment 400, which are parallel to each other. The source line segment 400 is attached to the upper surface of the third contact pillar, and the source line segment 400 is perpendicular to the third segment; the upper surface of the first contact column is connected with a first magnetic tunnel junction, and the other end of the first magnetic tunnel junction is connected with a first bit line segment 301; the upper surface of the second contact stud is connected to a second magnetic tunnel junction, and the other end of the second magnetic tunnel junction is connected to the second bit line segment 302.

The active region supporting layer 100 has a first drain, a second drain and a source, the first drain is located under the first contact pillar 101, the second drain is located under the second contact pillar 102, and the source is located under the third contact pillar 103. A first oxide layer is disposed between the lower surface of the second segment 212 and the upper surface of the active region carrier layer 100, and a second oxide layer is disposed between the lower surface of the fourth segment 214 and the upper surface of the active region carrier layer 100. The second segment 212 of the word line 210, the first oxide layer, the first drain and the source combine to form a first field effect transistor, and the second segment 212 acts as a gate. The fourth segment 214, the second oxide layer, the second drain and the source combine to form a second field effect transistor, and the fourth segment 214 serves as a gate. The two field effect transistors share a source electrode.

As shown in fig. 12, a magnetic random access memory includes a plurality of memory arrays composed of the above-mentioned cell structures, the individual segment word lines in each row of the memory array are connected end to form a complete word line, the individual first bit line segments 301 in each column of the memory array are connected end to form a complete first bit line (not shown), the individual second bit line segments 302 in each column are connected end to form a complete second bit line (not shown), and the source line segments 400 in each column are connected end to form a complete source line (not shown).

For the layout of two adjacent columns sharing one source line, special processing is needed for reading and writing. One preferred solution is as follows:

1. for two columns sharing a source line, only one of the columns is read-written at a time.

2. And 4 or 8 adjacent double column groups share one read-write circuit, and one column is selected by a column address decoder to be read and written.

3. For two columns contributing source lines, when one column is read or written, the bit line of the other column is shorted to the common source line.

4. Many combinations in 2 can be read and written at the same time to complete the input and output of one word.

The invention belongs to the field of semiconductor chips, and is most importantly applied to the fields of large data processing, solid state disk and the like which have requirements on content addressing.

The foregoing detailed description of the preferred embodiments of the invention has been presented. It should be understood that numerous modifications and variations could be devised by those skilled in the art in light of the present teachings without departing from the inventive concepts. Therefore, the technical solutions available to those skilled in the art through logic analysis, reasoning and limited experiments based on the prior art according to the concept of the present invention should be within the scope of protection defined by the claims.

Claims

1. A unit structure of a magnetic random access memory is characterized by at least comprising an active region bearing layer, a segment of a bow-shaped character line, a first contact column, a second contact column and a third contact column; the first contact column, the third contact column and the second contact column are sequentially arranged on the active region bearing layer; the segment of the bow-shaped character line passes through the area among the first contact column, the second contact column and the third contact column, so that the first contact column and the second contact column are positioned on one side of the segment of the bow-shaped character line, the third contact column is positioned on the other side of the segment of the bow-shaped character line, and an oxide layer is arranged below the segment of the bow-shaped character line.

2. The cell structure of claim 1, wherein the segment of the word segment is composed of first, second, third, fourth and fifth segments connected end to end, and the first and fifth segments are located on the same straight line and parallel to the third segment.

3. The cell structure of claim 2, wherein the second segment is perpendicular to the third segment, and the fourth segment is perpendicular to the third segment.

4. The cell structure of claim 2, wherein the junction angle between the second segment and the third segment is a first obtuse angle, and the junction angle between the fourth segment and the third segment is a second obtuse angle.

5. The cell structure of claim 4, wherein the first obtuse angle is 120-160 degrees, and the second obtuse angle is 120-160 degrees.

6. The cell structure of claim 5, wherein the active region supporting layer is recessed, the first contact pillar and the second contact pillar are respectively disposed near two protruded corners of the recessed portion, and the outer edge of the third segment exceeds the edge of the recessed portion.

7. The cell structure of claim 1, further comprising a first bit line segment, a first magnetic tunnel junction, a second bit line segment, a second magnetic tunnel junction, and a source line segment parallel to each other, wherein the source line segment is attached to the upper surface of the third contact pillar, and the source line segment is perpendicular to the third segment; the upper surface of the first contact column is connected with the first magnetic tunnel junction, and the other end of the first magnetic tunnel junction is connected with a first bit line segment; the upper surface of the second contact column is connected with a second magnetic tunnel junction, and the other end of the second magnetic tunnel junction is connected with a second bit line segment.

8. A magnetic random access memory comprising a plurality of memory arrays comprised of the cell structure of claim 7, wherein each of the arcuate word line segments in each row of the memory array are connected end to form a complete word line, each of the first bit line segments in each column of the memory array are connected end to form a complete first bit line, each of the second bit line segments in each column are connected end to form a complete second bit line, and the source line segments in each column are connected end to form a complete source line.