CN117615580A - Semiconductor memory cell and array structure thereof - Google Patents

Abstract

The invention relates to a semiconductor memory unit and an array structure thereof, wherein the memory unit comprises a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a first memory R1 and a second memory R2; the source electrode of the first NMOS tube N1 is connected with a source line SL1, the grid electrode of the first NMOS tube N1 is connected with a word line WL1, the drain electrode of the first NMOS tube N1 is connected with the source electrode/drain electrode of one end of the second NMOS tube N2, the grid electrode of the second NMOS tube N2 is connected with the word line WL2, the source electrode/drain electrode of the other end of the second NMOS tube N2 is connected with the drain electrode of a third NMOS tube N3, the source electrode of the third NMOS tube N3 is connected with the source line SL2, and the grid electrode of the third NMOS tube N3 is connected with the word line WL3; one end of the first memory R1 is connected with the joint of the first NMOS tube N1 and the second NMOS tube N2, the other end of the first memory R2 is connected with the bit line BL1, one end of the second memory R2 is connected with the joint of the third NMOS tube N3 and the second NMOS tube N2, and the other end of the second memory R2 is connected with the bit line BL2; the area of the memory cell is effectively reduced, and the array density is improved.

Description

Semiconductor memory cell and array structure thereof

Technical Field

The invention belongs to the technical field of semiconductor and CMOS hybrid integrated circuits, and particularly relates to a semiconductor memory cell compatible with the existing CMOS process and integrated with CMOS and an array structure thereof.

Background

In recent years, the development of information technology has led to an increasing storage demand, and new semiconductor memories such as Resistive Random Access Memory (RRAM), phase change memory (PRAM), magnetoresistive memory (MRAM), and ferroelectric memory (FeRAM) have been widely studied and paid attention. The novel memory array has the characteristics of potential high density, low power consumption, high speed and the like, and is likely to cope with the increasing information processing and storage demands.

The novel semiconductor memory array is generally limited by severe write crosstalk and leakage paths, and transistors are generally required to be connected in series on memory cells to eliminate crosstalk, so as to form a transistor-memory device (1T 1R) array, fig. 1 shows a schematic circuit structure diagram of a conventional common source 1T1R array, in which 8 memory devices are shown, each memory device is connected to one transistor, and the memory array in fig. 1 can be considered to be formed by repeating 4 times a memory cell located in the upper left corner of a dashed line frame 101, where each memory cell includes a first memory device R1, a first NMOS transistor N1, a second memory device R2, and a second NMOS transistor N2. In the repeating unit, the gates of N1, N2 are connected to WL1 and WL2, N1 and N2 sources, respectively, and the drains of N1, N2 are connected to the common source line SL, respectively, with R1, R2, forming two independent 1T1R structures, further, R1 and R2 are connected to BL to form a complete circuit structure, and the memory can be written or read by controlling the voltages on WL1, WL2, BL, SL.

The development of technology requires that the area of the memory cells be continuously reduced, however, the memory array shown in fig. 1 requires that the adjacent memory cells have a space as indicated by a dashed box 102, otherwise, normal read-write functions of the memory array are affected, and the space severely reduces the area utilization of the memory cells, thereby limiting the increase of the density of the memory array. Fig. 2 is a schematic diagram of the memory array of fig. 1, wherein 16 memory devices are depicted, the layout comprising 4 levels of active area, gate, memory device and source, respectively, wherein active area 201 corresponds to a memory cell of 101. The spacing of 102 in fig. 1 corresponds to the dashed box 202 in fig. 2, which has a width that is process dependent, generally similar to the transistor gate length under process. It can be seen that the conventional array structure of fig. 1 does not fully utilize layout area.

Disclosure of Invention

In view of the above problems in the prior art, the present invention proposes a semiconductor memory cell and an array structure thereof, which utilize a memory cell and an array design of a common transistor to reduce array areas of novel memories such as a Resistive Random Access Memory (RRAM), a phase change memory (PRAM), a magnetoresistive memory (MRAM), and a ferroelectric memory (FeRAM) while maintaining normal read/write functions of a memory circuit and gate transistor driving capability, thereby improving memory array density.

The technical scheme of the invention is as follows:

the semiconductor memory unit is characterized by comprising a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a first memory R1 and a second memory R2, wherein the first memory R1 and the second memory R2 are respectively two-end novel memory devices, and the semiconductor memory unit is connected with a word line WL1, a word line WL2, a word line WL3, a source line SL1, a source line SL2, a bit line BL1 and a bit line BL2; the source electrode of the first NMOS transistor N1 is connected to the source line SL1, the gate electrode thereof is connected to the word line WL1, the drain electrode thereof is connected to the source electrode/drain electrode of one end of the second NMOS transistor N2, the source electrode/drain electrode of the other end of the second NMOS transistor N2 is connected to the drain electrode of the third NMOS transistor N3, the first NMOS transistor N1, the second NMOS transistor N2 and the third NMOS transistor N3 are connected in series, the gate electrode of the second NMOS transistor N2 is connected to the word line WL2, and the source electrode of the third NMOS transistor N3 is connected to the source line SL2 and the gate electrode thereof is connected to the word line WL3; one end of the first memory R1 is connected with the connecting position of the first NMOS tube N1 and the second NMOS tube N2, the other end of the first memory R2 is connected with the bit line BL1, and one end of the second memory R2 is connected with the connecting position of the third NMOS tube N3 and the second NMOS tube N2, and the other end of the second memory R2 is connected with the bit line BL2.

Further, the first memory R1 and the second memory device R2 are respectively a resistive memory, a phase change memory, a magneto-resistive memory, or a ferroelectric memory.

In order to further explain the advantages of the present invention compared with the conventional structure, the present invention further provides a memory array formed by the above memory cells, which is characterized in that the memory cells are arranged in a matrix structure along a lateral direction and a longitudinal direction, wherein the memory cells in the same column share a word line WL1, a word line WL2, and a word line WL3, that is, the word lines WL1, WL2, and WL3 of each memory cell in each column are connected, the memory cells in the same row share a bit line BL1 and a bit line BL2, that is, the bit line BL1 and the bit line BL2 of each memory cell in each row are connected, the memory cells in the same row are connected through a source line, that is, the source line SL2 of the previous memory cell in each row is connected with the source line SL1 of the next memory cell in each row, and are sequentially connected to form a series structure, and the source line SL1 and the source line SL2 of each memory cell in the same row are connected to a unified source line SL of the row.

In summary, the present invention utilizes the memory cell and the array design of the common transistor to reduce the memory array area of the novel memory, thereby improving the memory array density. Unlike the existing memory cell, the memory cell of the present invention can turn on three transistors in the cell during operation, thereby having two operation current paths, and reducing the requirements on transistor size in the memory circuit. Meanwhile, the storage units in the same row in the storage array adopt an interconnecting series structure, so that an isolation area between adjacent storage units in the original array structure is eliminated, and the area utilization rate of a storage circuit is improved. By combining the two points, the invention can effectively reduce the area of a single storage unit, thereby improving the density of the storage array.

Drawings

FIG. 1 is a schematic diagram of a circuit configuration of a conventional common source 1T1R array;

FIG. 2 is a schematic diagram of a layout design of a conventional common source 1T1R array;

FIG. 3 is a schematic diagram of a circuit structure of a memory cell according to the present invention;

FIG. 4 is a schematic diagram of a circuit structure of an array of memory cells according to the present invention;

FIG. 5 is a schematic diagram of a layout of an array of memory cells according to the present invention.

Detailed Description

The following description of the embodiments of the present invention will be made more apparent and fully hereinafter with reference to the accompanying drawings, in which some, but not all embodiments of the invention are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

As shown in fig. 3, the schematic diagram of the circuit structure of the memory cell provided by the invention includes a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a first memory R1 and a second memory R2, where the first memory R1 and the second memory R2 are two-terminal novel memory devices respectively, and the semiconductor memory cell is connected with a word line WL1, a word line WL2, a word line WL3, a source line SL1, a source line SL2, a bit line BL1 and a bit line BL2; the source electrode of the first NMOS transistor N1 is connected to the source line SL1, the gate electrode thereof is connected to the word line WL1, the drain electrode thereof is connected to the source electrode/drain electrode of one end of the second NMOS transistor N2, the source electrode/drain electrode of the other end of the second NMOS transistor N2 is connected to the drain electrode of the third NMOS transistor N3, the first NMOS transistor N1, the second NMOS transistor N2 and the third NMOS transistor N3 are connected in series, the gate electrode of the second NMOS transistor N2 is connected to the word line WL2, and the source electrode of the third NMOS transistor N3 is connected to the source line SL2 and the gate electrode thereof is connected to the word line WL3; one end of the first memory R1 is connected with the connecting position of the first NMOS tube N1 and the second NMOS tube N2, the other end of the first memory R2 is connected with the bit line BL1, and one end of the second memory R2 is connected with the connecting position of the third NMOS tube N3 and the second NMOS tube N2, and the other end of the second memory R2 is connected with the bit line BL2.

Fig. 4 is a schematic circuit diagram of an array of memory cells according to the present invention. The memory array is formed by arranging the memory units in the transverse direction and the longitudinal direction to form a matrix structure which is tightly arranged. In the array, word lines WL1, WL2 and WL3 are shared among memory cells in the same column, namely, word lines WL1, WL2 and WL3 of each memory cell in each column are connected, the shared bit line BL1 and BL2 of each memory cell in the same row are connected, namely, the bit line BL1 and BL2 of each memory cell in each row are connected, the memory cells in the same row are connected through source lines, namely, the source line SL2 of the previous memory cell in each row is connected with the source line SL1 of the next memory cell, the memory cells are sequentially connected to form a series structure, and the source lines SL1 and SL2 of each memory cell in the same row are connected to a unified source line SL of the row.

The invention takes an array formed by 8 storage units (16 storage devices) as an example, and illustrates that compared with layout calculation in the prior art, the invention can improve the storage density of the array according to the calculation result. FIG. 5 is a schematic diagram of layout design of an array of 8 memory cells of the present invention, which is an active region, a gate, a memory device and a source, wherein one active region in the diagram corresponds to one row in the array of FIG. 4, a 40nm process node is selected, a resistive random access memory RRAM is selected for the memory device, and key process parameters are: the spacing d=110 nm of the active regions, the gate width w=300 nm of the transistors is selected, and the structural design can bring about 24.4% of storage density improvement on the premise of not influencing the driving capability according to the layout comparison calculation of fig. 2 and 5.

In summary, the embodiment realizes a memory array structure realized by the memory unit provided by the invention, and can effectively improve the density of the memory array.

It should be noted that, the first, second, etc. numbering order in the foregoing description is only for accurately describing the structures of the memory cells and arrays according to the present invention, and the modification or exchange of numbers does not affect the protection of the present invention in the case of the same or similar structures.

Finally, it is required to explain: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments may be modified or some or all of the technical features may be replaced with equivalents. For example, the array corresponding to the above embodiment may be extended to any scale; the transistors in the memory unit provided by the invention are not necessarily selected to have the same size, but can be flexibly selected according to actual needs; in addition, the array structure that the memory cell of the present invention can be configured is more than one of the embodiments. Therefore, the invention should not be limited to the disclosed embodiments, but rather the scope of the invention is defined by the appended claims.

Claims (3)

1. The semiconductor memory unit is characterized by comprising a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a first memory R1 and a second memory R2, wherein the first memory R1 and the second memory R2 are respectively two-end novel memory devices, and the semiconductor memory unit is connected with a word line WL1, a word line WL2, a word line WL3, a source line SL1, a source line SL2, a bit line BL1 and a bit line BL2; the source electrode of the first NMOS transistor N1 is connected to the source line SL1, the gate electrode thereof is connected to the word line WL1, the drain electrode thereof is connected to the source electrode/drain electrode of one end of the second NMOS transistor N2, the source electrode/drain electrode of the other end of the second NMOS transistor N2 is connected to the drain electrode of the third NMOS transistor N3, the first NMOS transistor N1, the second NMOS transistor N2 and the third NMOS transistor N3 are connected in series, the gate electrode of the second NMOS transistor N2 is connected to the word line WL2, and the source electrode of the third NMOS transistor N3 is connected to the source line SL2 and the gate electrode thereof is connected to the word line WL3; one end of the first memory R1 is connected with the connecting position of the first NMOS tube N1 and the second NMOS tube N2, the other end of the first memory R2 is connected with the bit line BL1, and one end of the second memory R2 is connected with the connecting position of the third NMOS tube N3 and the second NMOS tube N2, and the other end of the second memory R2 is connected with the bit line BL2.

2. The semiconductor memory cell of claim 1, wherein the first memory R1 and the second memory device R2 are respectively a resistive memory, a phase change memory, a magnetoresistive memory, or a ferroelectric memory.

3. A memory array, wherein the memory cells of claim 1 are arranged in a matrix structure along a horizontal direction and a vertical direction, wherein word lines WL1, WL2 and WL3 are shared among the memory cells of a same column, that is, word lines WL1, WL2 and WL3 of each memory cell in each column are connected, bit lines BL1 and BL2 are shared among the memory cells of a same row, that is, bit lines BL1 and BL2 of each memory cell in each row are connected, the memory cells of a same row are connected through source lines, that is, source line SL2 of a previous memory cell in each row is connected with source line SL1 of a next memory cell, and source lines SL1 and SL2 of each memory cell in a same row are connected in sequence to form a serial structure.