CN111739570B - SOT-MRAM memory cell and SOT-MRAM memory - Google Patents
SOT-MRAM memory cell and SOT-MRAM memory Download PDFInfo
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- CN111739570B CN111739570B CN201910228164.2A CN201910228164A CN111739570B CN 111739570 B CN111739570 B CN 111739570B CN 201910228164 A CN201910228164 A CN 201910228164A CN 111739570 B CN111739570 B CN 111739570B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
- G11C14/0009—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell
- G11C14/0036—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a DRAM cell and the nonvolatile element is a magnetic RAM [MRAM] element or ferromagnetic cell
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
Abstract
The invention provides an SOT-MRAM memory cell, comprising: the device comprises a heavy metal line for providing spin orbit torque, two MTJs and diodes, a bidirectional gate and a transistor which are connected with the two MTJs, wherein two ends of the heavy metal line are connected to a bit line respectively, the two MTJs are located on the upper surface of the heavy metal line, a free layer of each MTJ is close to the heavy metal line, a fixed layer of each MTJ is far away from the heavy metal line, the two MTJs are connected to a drain electrode of the transistor through the diodes which are connected with the two MTJs respectively, and the connection directions of the two diodes are opposite; one end of the bidirectional gate is connected with the heavy metal wire, a connection point is located between the two MTJs of the heavy metal wire, and the other end of the bidirectional gate is connected with the drain electrode of the transistor; the gate of the transistor is connected to a word line, and the source of the transistor is connected to a source line. The invention can reduce the area of the memory unit and improve the memory density.
Description
Technical Field
The invention relates to the technical field of magnetic memories, in particular to an SOT-MRAM memory cell and an SOT-MRAM memory.
Background
MRAM (Magnetic Random Access Memory) is a new type of solid-state nonvolatile Memory, which has the characteristic of high-speed read/write, and can be made into a Memory cell of the Magnetic Random Access Memory by using the reversal of magnetization reversal of a free layer in a Magnetic Tunnel Junction (MTJ).
The Spin-Orbit Torque Magnetic Memory (SOT-MRAM) drives magnetization of a free layer of the MTJ to be turned over based on Spin-Orbit Torque generated by a Spin Hall effect, thereby achieving the purpose of regulating and controlling a Magnetic storage unit.
At present, the SOT-MRAM memory unit generally adopts a structure as shown in fig. 1, and the memory unit includes a spin orbit torque supply line, a magnetic tunnel junction MTJ located on the spin orbit torque supply line, and two transistors, the spin orbit torque supply line is used for supplying the spin orbit torque required for writing data to the magnetic tunnel junction MTJ, and when reading data, the spin orbit torque supply line is used only as an electrode, and the two transistors are respectively used for controlling reading and writing.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
the conventional SOT-MRAM memory unit has a three-terminal structure, needs two transistors to control reading and writing, can only store 1-bit data, and needs two memory units when storing 2-bit data, so that the memory unit occupies a large area and causes low storage density of the memory.
Disclosure of Invention
In order to solve the above problems, the present invention provides an SOT-MRAM memory cell and an SOT-MRAM memory, which can reduce the area of the memory cell and increase the memory density.
The invention provides an SOT-MRAM memory cell, comprising: a heavy metal line for providing spin orbit torque, two MTJs and their respective connected diodes, a bidirectional gate and a transistor,
two ends of the heavy metal wire are respectively connected to a bit line, the two MTJs are located on the upper surface of the heavy metal wire, the free layers of the MTJs are close to the heavy metal wire, the fixed layers of the MTJs are far away from the heavy metal wire, the two MTJs are connected to the drain electrode of the transistor through respective connected diodes, and the connection directions of the two diodes are opposite;
one end of the bidirectional gate is connected with the heavy metal wire, a connection point is located between the two MTJs of the heavy metal wire, and the other end of the bidirectional gate is connected with the drain electrode of the transistor;
the gate of the transistor is connected to a word line, and the source of the transistor is connected to a source line.
The present invention also provides an SOT-MRAM memory cell comprising: a heavy metal line for providing spin-orbit torque, two MTJs and their respective connected diodes, a bidirectional gate, and two transistors,
two ends of the heavy metal wire are respectively connected to the drain electrode of one transistor, the two MTJs are positioned on the upper surface of the heavy metal wire, the free layers of the MTJs are close to the heavy metal wire, the fixed layers of the MTJs are far away from the heavy metal wire, the two MTJs are connected to a bit line through respective connected diodes, and the connection directions of the two diodes are opposite;
one end of the bidirectional gate is connected with the heavy metal wire, a connection point is located between the two MTJs of the heavy metal wire, and the other end of the bidirectional gate is connected with the bit line;
the gates of the two transistors are respectively connected to a word line, and the sources of the two transistors are both connected to a source line.
Optionally, the MTJ is a perpendicular magnetization structure, and the MTJ has a structure including, in order from bottom to top, a free layer, a tunneling layer, a fixed layer, a spacer layer, and a bias layer, where the bias layer is configured to provide a bias magnetic moment for the free layer, so that the free layer magnetic moment generates an initial bias angle.
Optionally, the MTJ is an in-plane magnetization structure, and the MTJ has a structure including, from bottom to top, a free layer, a tunneling layer, and a fixed layer in this order.
Optionally, the MTJ connected diode is vertically stacked on the MTJ.
Optionally, the bidirectional gate is a bidirectional diode and has a bidirectional conduction function.
Optionally, the bidirectional gate is connected in parallel with the two MTJs through a multilayer wiring metal interconnection process.
The invention also provides an SOT-MRAM memory, which comprises the SOT-MRAM memory unit.
The SOT-MRAM storage unit provided by the invention comprises two MTJs which are connected in parallel and can store 2bit data, the two MTJs which are connected in parallel share the transistor, the heavy metal layer and the bidirectional gate, the use efficiency is higher, the use of the transistor, the heavy metal layer and the bidirectional gate is reduced, the area of the storage unit can be saved, and the storage density of the data is improved. Furthermore, the stored 2-bit data can be independently read and written respectively, so that the complexity of writing the data is reduced, and the difficulty and the error rate of reading the data are also reduced.
Drawings
FIG. 1 is a schematic diagram of a conventional SOT-MRAM memory cell;
FIG. 2 is a schematic diagram of an SOT-MRAM memory cell according to an embodiment of the invention;
FIG. 3 is a schematic diagram of a write current path of the SOT-MRAM memory cell shown in FIG. 2;
FIG. 4 is a schematic diagram of a read current path of the SOT-MRAM memory cell of FIG. 2;
FIG. 5 is a schematic diagram of an SOT-MRAM memory cell according to another embodiment of the invention;
FIG. 6 is a schematic diagram of an SOT-MRAM memory cell according to yet another embodiment of the invention;
FIG. 7 is a schematic write current path of the SOT-MRAM memory cell of FIG. 6;
FIG. 8 is a schematic diagram of a read current path of the SOT-MRAM memory cell of FIG. 6;
FIG. 9 is a schematic diagram of an SOT-MRAM memory cell according to another embodiment of the invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
FIG. 2 is a schematic diagram of an SOT-MRAM memory cell according to an embodiment of the invention. As shown in FIG. 2, the SOT-MRAM memory cell includes: the device comprises a heavy metal wire HM for providing spin orbit torque, a diode D10 connected with the magnetic tunnel junction MTJ-10 and the MTJ-10, a diode D11 connected with the magnetic tunnel junction MTJ-11 and the MTJ-11, a bidirectional gate Selector and a transistor M11, wherein one end of the heavy metal wire HM is connected to a bit line BL-10, the other end of the heavy metal wire HM is connected to the bit line BL-11, the MTJ-10 and the MTJ-11 are both positioned on the upper surface of the heavy metal wire HM, the MTJ-10 and the MTJ-11 adopt a perpendicular magnetization structure, and the structure comprises a free layer, a tunneling layer, a fixed layer, a spacer layer and a bias layer from bottom to top in sequence, wherein the bias layer is used for providing a bias magnetic moment for the free layer so as to enable the magnetic moment of the free layer to generate an initial bias angle, and the spacer layer is used for isolating the fixed layer from the bias layer. MTJ-10 is connected to the drain of M11 through D10, MTJ-11 is connected to the drain of M11 through D11, wherein the bias layer of MTJ-10 is connected to the anode of D10, the cathode of D10 is connected to the drain of M11, the bias layer of MTJ-11 is connected to the cathode of D11, the anode of D11 is connected to the drain of M11, and the connection directions of D10 and D11 are opposite. Specifically, there is a metal layer between the bias layer and the diode of the two MTJs, including but not limited to Ta, Ru, IrMn, PtMn, Cu, Al, W, and the like, and combinations thereof.
One end of the bidirectional gate Selector is connected with the heavy metal line HM, the connection point is located at the position between the MTJ-10 and the MTJ-11 of the heavy metal line HM, and the other end of the bidirectional gate Selector is connected with the drain electrode of the M11; the gate of M11 is connected to the word line WL, and the source of M11 is connected to the source line SL.
Specifically, in the structure, the bidirectional gate Selector is a bidirectional diode and has a bidirectional conduction function, and the bidirectional gate Selector can be connected with the two MTJs in parallel through a modern multilayer wiring metal interconnection process. In addition, the diode respectively connected with the two MTJs can be vertically stacked on the MTJ, which is beneficial to improving the integration level of the device.
For the SOT-MRAM memory cell shown in FIG. 2, 2bit data can be stored, such as 00, 01,10, 11. The process of writing and reading the SOT-MRAM memory cells can be seen with reference to FIGS. 3-4.
When data is written into MTJ-10, WL is connected to voltage V, transistor M11 is turned on, bit line BL-10 is connected to voltage Vwor-Vw(VwIs a write voltage, and Vw>VsIn which V issIs the turn-on threshold voltage of the bi-directional gate Selector), the bit line BL-11 is floated when BL-10 accesses VwWhen the bidirectional gate Selector is turned on, the write current path is as follows: bit line BL-10 → heavy metal line HM → bidirectional gate Selector → chipTransistor M11 → source line SL, data "0 (or 1)" can be written; when BL-10 is accessed to-VwWhen the bidirectional gate Selector is turned on downwards, the write current path is as follows: the source line SL → the transistor M11 → the bidirectional gate Selector → the heavy metal line HM → the bit line BL-10, data "1 (or 0)" can be written, and it can be seen that writing "0" and writing "1" are only different in path direction, and a specific path can refer to a broken line shown in (a) in fig. 3;
when data is written into MTJ-11, WL is connected to voltage V, transistor M11 is turned on, bit line BL-10 is floated, and bit line BL-11 is connected to voltage Vwor-Vw(VwIs a write voltage, and Vw>VsIn which V issIs the turn-on threshold voltage of the bidirectional gate Selector), when BL-11 is switched in VwWhen the bidirectional gate Selector is turned on, the write current path is as follows: bit line BL-11 → heavy metal line HM → bidirectional gate Selector → transistor M11 → source line SL, data "1 (or 0)" can be written when BL-11 is connected to-VwWhen the bidirectional gate Selector is turned on downwards, the write current path is as follows: the source line SL → the transistor M11 → the bidirectional gate Selector → the heavy metal line HM → the bit line BL-11, data "0 (or 1)" can be written, and similarly, writing "0" and writing "1" are only different in path direction, and a specific path may refer to a broken line shown in (b) in fig. 3.
It should be noted that, when the SOT writing operation is performed on the MTJ cell, an STT (Spin-Transfer Torque) current may exist in the MTJ, and the STT current may be reduced by increasing the resistance of the MTJ or the like. Due to the small current flowing in the MTJ, the STT effect can be provided with limited impact, without impacting the SOT write operation of the MTJ.
When reading MTJ-10 data, the WL is connected to voltage V, which turns on transistor M11, and bit line BL-10 is connected to voltage Vr(VrIs a read voltage, and Vr<VsIn which V issIs the conduction threshold voltage of the bidirectional gate Selector), the bit line BL-11 is floating, at this time, the bidirectional gate Selector is turned off, and the read current path is: bit line BL-10 → heavy metal line HM → MTJ-10 → D10 → transistor M11 → source line SL, as shown by the broken line in fig. 4 (a);
when reading MTJ-11 data, WL is connected to voltage V, transistor M11 is turned on, bit line BL-10 is floated, and bit line BL-11 is connected to voltage-VrAt this time, the Selector of the bidirectional gate is turned off, and the read current path is as follows: the source line SL → the transistor M11 → D11 → MTJ-11 → heavy metal line HM → bit line BL-11, as shown by the broken line in fig. 4 (b).
FIG. 5 is a schematic diagram of an SOT-MRAM memory cell according to another embodiment of the invention. As shown in FIG. 5, compared to the SOT-MRAM memory cell shown in FIG. 2, the difference is that the magnetic tunnel junctions MTJ-10 and MTJ-11 no longer adopt a perpendicular magnetization structure, but adopt an in-plane magnetization structure, which is sequentially a free layer, a tunneling layer and a pinned layer from bottom to top, wherein [ ] indicates that the magnetization direction is out of plane perpendicular to the plane,
meaning that the magnetization direction is perpendicular to the plane inward. For the SOT-MRAM memory cell shown in FIG. 5, the writing and reading processes are similar to those for the SOT-MRAM memory cell shown in FIG. 2 and will not be described.
Further, FIG. 6 is a schematic structural diagram of an SOT-MRAM memory cell according to yet another embodiment of the invention. As shown in FIG. 6, the SOT-MRAM memory cell includes: the device comprises a heavy metal wire HM for providing spin orbit torque, a diode D20 connected with the magnetic tunnel junction MTJ-20 and the MTJ-20, a diode D21 connected with the magnetic tunnel junction MTJ-21 and the MTJ-21, a bidirectional gate Selector and two transistors M20 and M21, wherein one end of the heavy metal wire HM is connected to a drain electrode of the M20, the other end of the heavy metal wire HM is connected to a drain electrode of the M21, the MTJ-20 and the MTJ-21 are both positioned on the upper surface of the heavy metal wire HM, the MTJ-20 and the MTJ-21 adopt a vertical magnetization structure, and the structure sequentially comprises a free layer, a tunneling layer, a fixed layer, a spacer layer and a bias layer from bottom to top, wherein the bias layer is used for providing a magnetic moment bias for the free layer so that the magnetic moment of the free layer generates an initial bias angle, which is beneficial to the magnetic moment overturning of the free layer, and the spacer layer is used for isolating the fixed layer and the bias layer. MTJ-20 is connected to bit line BL through D20, MTJ-21 is connected to bit line BL through D21, where the bias layer of MTJ-20 is connected to the anode of D20, the cathode of D20 is connected to bit line BL, the bias layer of MTJ-21 is connected to the cathode of D21, the anode of D21 is connected to bit line BL, and the connection direction of D20 and D21 is opposite. Specifically, there is a metal layer between the bias layer and the diode of the two MTJs, including but not limited to Ta, Ru, IrMn, PtMn, Cu, Al, W, and the like, and combinations thereof.
One end of the bidirectional gate Selector is connected with the heavy metal wire HM, the connection point is located at the position between the MTJ-20 and the MTJ-21 of the heavy metal wire HM, and the other end of the bidirectional gate Selector is connected with the bit line BL; the gate of M20 is connected to word line WL-20, the source of M20 is connected to source line SL, the gate of M21 is connected to word line WL-21, and the source of M21 is connected to source line SL.
For the SOT-MRAM memory cell shown in FIG. 6, 2bit data can be stored, such as 00, 01,10, 11. The process of writing and reading the SOT-MRAM memory cells can be seen with reference to FIGS. 7-8.
When data is written into MTJ-20, WL-20 is connected to voltage V, transistor M20 is turned on, WL-21 is floated, M21 is turned off, and bit line BL is connected to voltage Vwor-Vw(VwIs a write voltage, and Vw>VsIn which V issIs the turn-on threshold voltage of the bidirectional gate Selector) when BL is connected to VwWhen the bidirectional gate Selector is turned on downwards, the write current path is as follows: bit line BL → bidirectional gate Selector → heavy metal line HM → transistor M20 → source line SL, data "0 (or 1)" can be written when BL is turned on-VwWhen the bidirectional gate Selector is turned on, the write current path is as follows: the source line SL → the transistor M20 → the heavy metal line HM → the bidirectional gate Selector → the bit line BL, data "1 (or 0)" can be written, and a specific path may refer to a broken line shown in (a) in fig. 7;
when data is written into MTJ-21, WL-20 is floated, M20 is turned off, WL-21 is connected to voltage V, transistor M21 is turned on, and bit line BL is connected to voltage Vwor-Vw(VwIs a write voltage, and Vw>VsIn which V issIs the turn-on threshold voltage of the bidirectional gate Selector) when BL is connected to VwWhen the bidirectional gate Selector is turned on downwards, the write current path is as follows: bit line BL → bidirectional gate Selector → heavy metal line HM → transistor M21 → sourceLine SL, where data "0 (or 1)" can be written, when BL is turned on-VwWhen the bidirectional gate Selector is turned on, the write current path is as follows: the source line SL → the transistor M21 → the heavy metal line HM → the bidirectional gate Selector → the bit line BL, and data "1 (or 0)" can be written, and the specific path can refer to the broken line shown in (b) of fig. 7.
When reading MTJ-20 data, WL-20 is connected to voltage V to turn on transistor M20, WL-21 is floated, M21 is disconnected, and bit line BL is connected to voltage Vr(VrIs a read voltage, and Vr<VsIn which V issIs the on threshold voltage of the bidirectional gate Selector), when the bidirectional gate Selector is off, the read current path is: source line SL → transistor M20 → heavy metal line HM → MTJ-20 → D20 → bit line BL as shown by the broken line in fig. 8 (a);
when reading MTJ-21 data, WL-20 is floated, M20 is turned off, WL-21 is connected to voltage V, transistor M21 is turned on, bit line BL is connected to voltage Vr(VrIs a read voltage, and Vr<VsIn which V issIs the turn-on threshold voltage of the bidirectional gate Selector), when the bidirectional gate Selector is turned off, the read current path is: the bit line BL → D21 → MTJ-21 → heavy metal line HM → transistor M21 → source line SL, as shown by the broken line in fig. 8 (b).
Further, FIG. 9 is a schematic structural diagram of an SOT-MRAM memory cell according to yet another embodiment of the invention. As shown in FIG. 9, compared to the SOT-MRAM memory cell shown in FIG. 6, the difference is that the magnetic tunnel junctions MTJ-20 and MTJ-21 do not adopt a perpendicular magnetization structure any more, but adopt an in-plane magnetization structure, which is a free layer, a tunneling layer and a pinned layer in this order from bottom to top, wherein [ ] indicates that the magnetization direction is out of plane perpendicular to the plane,
meaning that the magnetization direction is perpendicular to the plane inward. For the SOT-MRAM memory cell shown in FIG. 9, the writing and reading processes are similar to those for the SOT-MRAM memory cell shown in FIG. 6 and will not be described.
The SOT-MRAM storage unit provided by the embodiment comprises two MTJs which are connected in parallel and can store 2bit data, the two MTJs which are connected in parallel share the transistor, the heavy metal layer and the bidirectional gate, the use efficiency is higher, the use of the transistor, the heavy metal layer and the bidirectional gate is reduced, the area of the storage unit can be saved, and the storage density of the data is improved. Furthermore, the stored 2-bit data can be independently read and written respectively, so that the complexity of writing the data is reduced, and the difficulty and the error rate of reading the data are also reduced.
The embodiment of the invention also provides an SOT-MRAM memory, which comprises the SOT-MRAM memory unit.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (8)
1. An SOT-MRAM memory cell, comprising: a heavy metal line for providing spin orbit torque, two MTJs and their respective connected diodes, a bidirectional gate and a transistor,
two ends of the heavy metal wire are respectively connected to one bit line of the two bit lines, the two MTJs are both positioned on the upper surface of the heavy metal wire, the free layers of the MTJs are close to the heavy metal wire, the fixed layers of the MTJs are far away from the heavy metal wire, the two MTJs are connected to the drain electrode of the transistor through respective connected diodes, and the connection directions of the two diodes are opposite;
one end of the bidirectional gate is connected with the heavy metal wire, a connection point is located between the two MTJs of the heavy metal wire, and the other end of the bidirectional gate is connected with the drain electrode of the transistor;
the gate of the transistor is connected to a word line, and the source of the transistor is connected to a source line.
2. An SOT-MRAM memory cell, comprising: a heavy metal line for providing spin-orbit torque, two MTJs and their respective connected diodes, a bidirectional gate, and two transistors,
two ends of the heavy metal wire are respectively connected to the drain electrode of one of the two transistors, the two MTJs are positioned on the upper surface of the heavy metal wire, the free layers of the MTJs are close to the heavy metal wire, the fixed layers of the MTJs are far away from the heavy metal wire, the two MTJs are connected to a bit line through respective connected diodes, and the connection directions of the two diodes are opposite;
one end of the bidirectional gate is connected with the heavy metal wire, a connection point is located between the two MTJs of the heavy metal wire, and the other end of the bidirectional gate is connected with the bit line;
the gates of the two transistors are each connected to one of the two word lines, and the sources of the two transistors are each connected to a source line.
3. The SOT-MRAM memory cell of claim 1 or 2, wherein the MTJ is a perpendicular magnetization structure, and the MTJ has a structure comprising, in order from bottom to top, a free layer, a tunneling layer, a pinned layer, a spacer layer, and a biasing layer, wherein the biasing layer is configured to provide a biased magnetic moment to the free layer such that the free layer magnetic moment produces an initial bias angle.
4. The SOT-MRAM memory cell of claim 1 or 2, wherein the MTJ is an in-plane magnetization structure, and the structure of the MTJ is, from bottom to top, a free layer, a tunneling layer, and a fixed layer.
5. The SOT-MRAM memory cell of claim 1 or 2, wherein the MTJ connected diode is vertically stacked on the MTJ.
6. The SOT-MRAM memory cell according to claim 1 or 2, wherein the bidirectional gate is a bidirectional diode having a bidirectional conduction function.
7. The SOT-MRAM memory cell according to claim 1 or 2, wherein the bidirectional gate is connected in parallel to both MTJs by a multi-layer wiring metal interconnect process.
8. An SOT-MRAM memory comprising the SOT-MRAM memory cell of any of claims 1 to 7.
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| CN201910228164.2A CN111739570B (en) | 2019-03-25 | 2019-03-25 | SOT-MRAM memory cell and SOT-MRAM memory |
| PCT/CN2019/127404 WO2020192201A1 (en) | 2019-03-25 | 2019-12-23 | Sot-mram storage unit and sot-mram memory |
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| CN111986717A (en) * | 2020-08-20 | 2020-11-24 | 中国科学院微电子研究所 | SOT-MRAM (spin on demand-random Access memory) without external magnetic field oriented spin reversal and array |
| EP4207200A4 (en) * | 2020-08-31 | 2023-12-13 | Huawei Technologies Co., Ltd. | Memory |
| CN112420096A (en) * | 2020-11-20 | 2021-02-26 | 复旦大学 | Spin orbit torque magnetic random access memory without MOS tube |
| CN114566196A (en) * | 2020-11-27 | 2022-05-31 | 浙江驰拓科技有限公司 | Memory chip |
| US11929105B2 (en) * | 2020-12-29 | 2024-03-12 | Changxin Memory Technologies, Inc. | Method of fabricating a semiconductor device |
| US11793001B2 (en) | 2021-08-13 | 2023-10-17 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory |
| US11915734B2 (en) | 2021-08-13 | 2024-02-27 | International Business Machines Corporation | Spin-orbit-torque magnetoresistive random-access memory with integrated diode |
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| CN111739570A (en) | 2020-10-02 |
| WO2020192201A1 (en) | 2020-10-01 |
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