CN107368888A - Class brain computing system and its cynapse - Google Patents
Class brain computing system and its cynapse Download PDFInfo
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- CN107368888A CN107368888A CN201610310747.6A CN201610310747A CN107368888A CN 107368888 A CN107368888 A CN 107368888A CN 201610310747 A CN201610310747 A CN 201610310747A CN 107368888 A CN107368888 A CN 107368888A
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Abstract
One species brain computing system and its cynapse, the cynapse are MTJ cynapses, and it includes remembering MTJ and with reference to MTJ；The output end of MTJ cynapses is connected to the neuron of input charge in class brain computing system, and the input of MTJ cynapses is connected to the neuron of output charge in class brain computing system；The output end of MTJ cynapses is placed in reference potential, remember the first pulse that MTJ is suitable to receive the input from the MTJ cynapses, it is suitable to the second pulse for receiving the input from MTJ cynapses with reference to MTJ, the first pulse is launched simultaneously with the second pulse, and shape is identical and symbol is opposite；MTJ cynapses also include, with remembering the first gating device that MTJ is connected and the second gating device being connected with reference to MTJ, being respectively arranged on the different current paths between the neuron of output charge and the neuron of input charge, and both water conservancy diversion are in opposite direction.Technical solution of the present invention can effectively reduce the area of cynapse, the scale of extension class brain computing system institute integrated chip, and reduce power consumption.
Description
Technical field
The present invention relates to semiconductor chip field, more particularly to a species brain computing system and its cynapse.
Background technology
On MTJ：
MTJ (MTJ, Magnetic Tunneling Junction) is pressed from both sides by two layers of ferrimagnet
The structure of one layer very thin of non-ferric magnetic dielectric composition, as shown in Figure 1.It it is current it is main should
With being used in magnetic RAM (MRAM, Magnetic Random Access Memory) internal memory
In chip.
Refering to Fig. 1, following one layer of ferromagnetic material is the reference layer for having fixed magnetisation direction, iron above
Magnetic material is the memory layer of changeable magnetization direction, its direction of magnetization can it is parallel with fixed magnetization layer or
It is antiparallel.Due to the effect of quantum physics, electric current can pass through middle tunnel barrier layer, but MTJ
Resistance it is relevant with the direction of magnetization of variable magnetization layer.The previous case resistance is low, latter event resistance
It is high.
(STT, Spin Torque Transfer) technology is shifted using newer spinning moment, changes MTJ
State it is also fairly simple：Using than reading stronger electric current write operation is carried out through MTJ.One from bottom to top
Electric current variable magnetization stratification is set to it instead into the direction parallel with fixed bed, top-down circuit
Parallel direction.
Neuron and framework on human brain：
Human brain is a network by the complicated connection of a large amount of neurons.Fig. 2 can be referred to, each neuron leads to
Substantial amounts of other substantial amounts of neurons of dendron connection are crossed, receive information, each tie point is cynapse
(Synapse).After outside stimulus accumulation to a certain extent, a stimulus signal is produced, passes through aixs cylinder
Send out.Aixs cylinder has substantial amounts of tip, by cynapse, is connected to the dendron of other a large amount of neurons.
Exactly such a network being made up of the neuron of simple functions, realize all intelligency activities of the mankind.
Man memory and intelligence, it is generally believed that in the different stiffness of couplings for being stored in each cynapse.
The response frequency of neuron is no more than 100Hz, 10,000,000 times faster than human brain of the CPU of modern computer,
But the ability of many challenges of processing is not so good as human brain.This has promoted computer industry to start to imitate human brain.
On neutral net (Neural Network)：
The earliest imitation to human brain, is in software view.The nerve net risen from the sixties in last century
Network algorithm, the function of neuron is imitated with a function.Function receives multiple inputs, and each input has
Different weights, the process of learning training are exactly to adjust each weight.Function is output to a lot of other god
Through member, a network is formed.This kind of algorithm, abundant achievement is had been achieved for, is used widely.
But if the meter of the scale (more than 100,000,000,000 neurons) for shifting human brain on this algorithm onto, not only modern times
Calculation system can not be born, and be exactly power consumption, it is also desirable to huge power station supply.And the power consumption of human brain is only
There are 25 watts or so.
On impulsive neural networks (Spiking Neural Network)
For the motivation for reducing power consumption, the research imitated on hardware view human brain has begun to.Pulse
Neutral net is considered as the basis that class brain of future generation calculates.It is designed to more like human brain, and neuron is in product
Just outwards one pulse of transmitting after tired input to a certain extent.Unlike traditional neutral net, Ren Heyi
Individual inappreciable input can all cause whole network to carry out computing, therefore can save substantial amounts of electric energy.This
The network of sample has had been made into chip.The TrueNorth chips of IBM Corporation, it is exactly a famous example
Son.It is integrated with 1,000,000 neurons, 256,000,000 cynapses.Demonstrate and completed with extremely low power consumption
The algorithm of some artificial intelligence.
Human intelligence and the key message of memory, are stored in cynapse.In IBM TrueNorth chips
In, cynapse is by a static RAM (SRAM, Static Random Access
Memory) bit imitates cynapse.However, SRAM is larger because of chip area is accounted for, it is ratio
Internal memory costly, therefore the scale of this chips and human brain gap are very remote；In addition, SRAM also has other
Problem, the power consumption as caused by electric leakage.
The content of the invention
The problem to be solved in the present invention is that the cynapse area occupied of existing class brain computing system is larger, it is difficult to is had
The scale of effect extension institute integrated chip, and the power consumption caused by electric leakage rise.
To solve the above problems, technical solution of the present invention provides the cynapse of a species brain computing system, it is described
Cynapse is the MTJ cynapses comprising MTJ, and the MTJ cynapses include memory MTJ and with reference to MTJ；Institute
The output end for stating MTJ cynapses is connected to the neuron of input charge in the class brain computing system, described
The input of MTJ cynapses is connected to the neuron of output charge in the class brain computing system；The class brain
When computing system is in normal mode of operation, the output end of the MTJ cynapses is placed in reference potential, institute
The first pulse that memory MTJ is suitable to receive the input from the MTJ cynapses is stated, it is described to refer to MTJ
Suitable for receiving the second pulse of the input from the MTJ cynapses, first pulse and the second pulse
Launch simultaneously, shape is identical and symbol on the contrary, the voltage difference of first pulse and the second pulse by described
Reference potential and reading voltage to the MTJ cynapses are determined；The MTJ cynapses also include and institute
State the first connected gating devices of memory MTJ and with second gating device being connected with reference to MTJ,
First gating device and the second gating device be respectively arranged at the neuron of the output charge with it is described
On different current paths between the neuron of input charge, and both water conservancy diversion are in opposite direction.
Optionally, first gating device and the second gating device are gate diode.
Optionally, the MTJ cynapses in the class brain computing system include remembering MTJ and one containing one
With reference to MTJ binary states MTJ cynapses.
Optionally, the MTJ cynapses in class brain computing system also include by two binary states MTJ cynapse structures
The four state MTJ cynapses made, put on one of binary states MTJ in the four states MTJ cynapses and dash forward
The pulse of tactile input is different from the pulse for putting on the input of another binary states MTJ cynapses.
To solve the above problems, technical solution of the present invention also provides a species brain computing system, including：One
Individual above neuron and more than one above-mentioned MTJ cynapses, pass through the MTJ cynapses between neuron and connect
Pick up and；All MTJ cynapses it is each it is self-contained with reference to MTJ all in the state of same agreement.
Optionally, the neuron includes charge integrator and impulse generator；The charge integrator is fitted
In collecting each electric charge from outside or other neurons input point input, and by the charge accumulated of input
Get up, when charge accumulated reaches setting value, trigger the impulse generator and dashed forward to the MTJ of each output
First pulse and the second pulse are penetrated in triggering, while the electric charge accumulated is zeroed；The MTJ cynapses
Output end be connected to the charge integrator that the neuron of input charge is included, the MTJ cynapses it is defeated
Enter end and be connected to the impulse generator that the neuron of output charge is included.
Optionally, the charge integrator includes operational amplifier and capacitor；The reference potential is placed in
The first input end of the operational amplifier, the second input of the operational amplifier connect the MTJ
The output end of cynapse, the output end of the operational amplifier connect the input of the impulse generator, institute
The both ends for stating capacitor are connected with the second input and output end of the operational amplifier respectively.
Optionally, the class brain computing system also includes writing drive circuit, described to write the first of drive circuit
Output end is connected with the impulse generator to each memory MTJ output end, described to write drive circuit
The second output end and the charge integrator each memory MTJ input is connected；In normal work
Drive circuit, which is write, described under operation mode is in pass-through state, the impulse generator and electricity under programming mode
Lotus integrator is in high-impedance state, and the drive circuit of writing is used to change under the programming mode or maintained
The state of the memory MTJ；Put on the voltage root of the memory MTJ and first gating device
Pressed according to the forward direction of the reference potential, the program voltage of the MTJ cynapses and first gating device
Drop or reverse turn-on voltages determine.
Optionally, the class brain computing system is integrated in semiconductor chip in the form of hierarchy, described
Hierarchy by more than one layer of neural elementary charge output layer and more than one layer of neural elementary charge input layer according to
Secondary alternating layer, which connects, to be formed, the neuron of the neural elementary charge output layer including more than one output charge and
Its corresponding one group of output line, the neural elementary charge input layer include the nerve of more than one input charge
Member and its corresponding one group of input line；The output lines of adjacent two layers and input line in arrangement form array in length and breadth,
Each crossover location between the output line and input line of adjacent two layers is provided with a MTJ cynapse, each
The input line of the neuron of the output line of the neuron of output charge and each input charge each self-contained two
Root wire, the wire that wire, the input line that output line includes include have connected the memory MTJ
And first gating device forms a current path, another wire that output line includes, input
Another wire that line includes has connected the reference MTJ and second gating device forms another
Current path.
Compared with prior art, technical scheme at least has advantages below：
The cynapse in class brain computing system is imitated by using MTJ structure, except that can realize that cynapse is answered
When the function of possessing, and can effectively reduces the area shared by cynapse, moreover it is possible to according to the non-volatile of MTJ
Storage characteristics and powered off when not in use, thus make future integrated class brain computing system class brain core
Piece can have bigger scale and smaller power consumption.
The advantage that the class brain computing system and its cynapse provided on technical solution of the present invention is embodied, specifically
It is analyzed as follows：
, can be the area reduction of cynapse to 1/10th 1. substitute traditional SRAM as cynapse by the use of MTJ
It is even more more, it is meant that same chip can carry out the much bigger calculating of scale.
2. SRAM can leak electricity when not in use used in traditional cynapse, this leaks electricity when chip-scale is big
It is quite serious, and MTJ cynapses can power off when not in use, so as to reduce power consumption.
3.MTJ retains original information when power is off, it is not necessary to is programmed and believed using another chip-stored
Breath, also without loading content during startup, it can be started with moment.
Brief description of the drawings
Fig. 1 is the structural representation of the MTJ with high-resistance state and low resistance state characteristic；
Fig. 2 is the neuron configuration diagram of human brain；
Fig. 3 is the structural representation of class brain computing system provided in an embodiment of the present invention；
Fig. 4 is the structural representation of the binary states MTJ cynapses of the embodiment of the present invention；
Fig. 5 is the structural representation of four state MTJ cynapses of the embodiment of the present invention；
Fig. 6 is a kind of electrical block diagram of the charge integrator of the embodiment of the present invention；
Fig. 7 is array layout schematic diagram of the embodiment of the present invention to the computing chip of integrated class brain computing system.
Embodiment
It is understandable to enable the above objects, features and advantages of the present invention to become apparent, below in conjunction with the accompanying drawings
The specific embodiment of the present invention is described in detail.
Fig. 3 can be referred to, the embodiment of the present invention provides a species brain computing system, including：More than one god
Through first and more than one MTJ cynapses, risen between neuron and neuron by the MTJ Synaptic junctions
Come.Specifically, more than one neuron includes the neuron of input charge and the neuron of output charge,
The neuron of each input charge is connected to more than one MTJ cynapses, the god of each output charge
More than one MTJ cynapses are also connected to through member.
Neuronal structure in the present embodiment is as shown in figure 3, it can include a charge integrator and one
Individual impulse generator, charge integrator collect each electricity from outside or other neurons input point input
Stream, the accumulation of electrical current of input is got up, when charge accumulated reaches setting value, trigger generator to
The cynapse transmitting pulse of each output, while electric charge is zeroed.Structure on neuron in the present embodiment will
Subsequently it is being described further.
In addition, the neuron in class brain computing system also receives externally fed and receives external control signal,
This is known to a person skilled in the art, is not described in detail herein.
It is pointed out that the scheme different from generally imitating cynapse with SRAM in the prior art, this hair
The cynapse used in the class brain computing system that bright embodiment provides is then the MTJ cynapses for including MTJ.
Specifically, Fig. 4 can be referred to, the MTJ cynapses include memory MTJ and with reference to MTJ；It is described
The output end of MTJ cynapses is connected to the neuron of input charge in the class brain computing system, the MTJ
The input of cynapse is connected to the neuron of output charge in the class brain computing system；The class brain calculates
When system is in normal mode of operation, the output end of the MTJ cynapses is placed in reference potential, the note
Recall the first pulse that MTJ is suitable to receive the input from the MTJ cynapses, it is described to be fitted with reference to MTJ
In the second pulse for receiving the input from the MTJ cynapses, first pulse and the second pulse are same
When launch, shape is identical and symbol on the contrary, the voltage difference of first pulse and the second pulse by the base
Quasi- current potential and reading voltage to the MTJ cynapses are determined；The MTJ cynapses also include with it is described
Remember the first connected gating devices of MTJ and with second gating device being connected with reference to MTJ, institute
State the first gating device and the second gating device be respectively arranged at the neuron of the output charge with it is described defeated
Enter on the different current paths between the neuron of electric charge, and both water conservancy diversion are in opposite direction.
In the present embodiment, all MTJ cynapses it is each it is self-contained with reference to MTJ all in the state of same agreement
Upper (be all high-impedance state or be all low resistance state).The operation principle of MTJ cynapses is as follows：
With continued reference to Fig. 4, output end (charge integrator for being connected to a neuron) quilt of MTJ cynapses
It is placed in reference potential V_b；
The impulse generator of input launches a pulse (i.e. the first pulse) to memory MTJ, for example launches
One square wave from reference potential V_b to V_b+V_read, wherein V_read are the readings to MTJ cynapses
Power taking pressure；
This impulse generator launches a pulse that shape is identical but symbol is opposite to reference to MTJ simultaneously
(i.e. the second pulse), with the example of above square wave, then can be one from reference potential V_b to
V_b-V_read square wave.
So, when remembering MTJ and being in same state with reference to MTJ, whole MTJ cynapses do not have
Net charge export, and only when memory MTJ be in refer to MTJ differences in the state of just have net charge defeated
Go out.
During actual implementation, first gating device and the second gating device can use gate diode
It is achieved, i.e., each connects a gate diode in memory MTJ and with reference to MTJ, is respectively used to pair
Respective read pulse conducting, therefore the both positive and negative polarity connection setting of the gate diode should be with read pulse
The sense of current is consistent.As shown in figure 4, gate diode (first gating corresponding with memory MTJ
Device) positive pole and impulse generator be used to export the output end of the first pulse and be connected, the gate diode
Negative pole then connect memory MTJ；The gate diode (second gating device) corresponding with reference MTJ
Negative pole and impulse generator be used to export the output end of the second pulse and be connected, the positive pole of the gate diode
Then connection refers to MTJ.
Certainly, MTJ is remembered, with reference to the not office of the position between MTJ and respective gate diode
It is limited to the mode shown in Fig. 4, position is entirely to exchange.Such as：Can will with remember MTJ phases
The input that the negative pole of corresponding gate diode is used to input the first pulse with charge integrator is connected, should
The positive pole of gate diode then connects memory MTJ；Or can be by the gating two corresponding with reference MTJ
The input that the positive pole of pole pipe is used to input the second pulse with charge integrator is connected, the gate diode
Negative pole is then connected with reference to MTJ.
In other embodiments, first gating device and the second gating device can also select other energy
The device or circuit for realizing similar functions are achieved.As for first gating device and the second gate
The effect of part will be subsequently further explained.
In the present embodiment, MTJ cynapses as shown in Figure 4 contain memory MTJ and one and refer to MTJ,
Such MTJ cynapses can represent the electric charge of 0,1 two unit, therefore can be called binary states MTJ and dash forward
Touch.Certainly, the MTJ cynapses in class brain computing system are except that including binary states MTJ cynapses, can also include
The four state MTJ cynapses formed by two binary states MTJ cynapses constructions, in the four states MTJ cynapses
The pulse for putting on the input of one of binary states MTJ cynapses is different from putting on another binary states MTJ
The pulse of the input of cynapse.One optimal design is the electric charge in the pulse of a binary states MTJ cynapse
Amount is another twice.
Shown in Fig. 4 is the MTJ cynapses of binary states, and can construct four states with two such cynapses
MTJ cynapses, as shown in Figure 5.When actually implementing, relative to first in some four state MTJ cynapse
Individual binary states MTJ synaptic structures, same impulse generator can be to second in the four states MTJ cynapses
Binary states MTJ synaptic structures launch the bigger pulse of a width., can be with still with this example of above-mentioned square wave
It is a same height (voltage difference), but width (i.e. burst length) is twice of square wave.It is so whole
Combination can export the electric charge of 0,1,2,3 four unit.
It is pointed out that the MTJ cynapses between neuron and neuron can both use the MTJ of binary states
Cynapse, the MTJ cynapses of four states can also be used, or even eight states, the MTJ of 16 states can also be taken
Cynapse, this is determined by the demand between neuron and neuron for bonding strength.Certainly, exist
During actual implementation, the MTJ cynapses of high state, its corresponding enforcement difficulty also will be more complicated.
It should be noted that perhaps also cynapse can be served as with variable-resistance material in the presence of some in the prior art
Tentative programme, but the mode for forming difference between currents in the present embodiment using two MTJ imitates the upper of cynapse
State design not then to be disclosed, also those skilled in the art had not expected for this.
As mentioned before this, in the present embodiment, the neuron includes charge integrator and pulse is sent out
Raw device；In the case where providing the control of externally fed and external control signal, the charge integrator is suitable to receive
Collect each electric charge (electric current) from outside or other neurons input point input, and the electric charge of input is (electric
Stream) accumulate, when charge accumulated reaches setting value, the impulse generator is triggered to each output
MTJ cynapses launch the first pulse and the second pulse, while the electric charge accumulated is zeroed；The MTJ
The output end of cynapse is connected to the charge integrator that the neuron of input charge is included, the MTJ cynapses
Input be connected to the impulse generator that the neuron of output charge is included.Those skilled in the art hold
It is intelligible to be, when actually implementing, because the resistance value of each MTJ cynapses may be different, that
The electric current exported to other each neurons or outside output point will be not quite similar.
It is actual when implementing, the charge integrator in the neuron of the present embodiment, can be standard simulation collection
Into circuit devcie, there are many different circuits on textbook.Give one example below：
The charge integrator includes operational amplifier and capacitor；The reference potential is placed in the computing
The first input end of amplifier, the second input of the operational amplifier connect the defeated of the MTJ cynapses
Go out end, the output end of the operational amplifier connects the input of the impulse generator, the capacitor
Both ends be connected respectively with the second input and output end of the operational amplifier (the one of the capacitor
End connects the second input of the operational amplifier, and the other end connects the output of the operational amplifier
End).
As shown in fig. 6, when actually implementing, the charge integrator can include an operational amplifier
With a capacitor C.The enlarge-effect of the operational amplifier causes the very close benchmark of current potential of A points
Current potential V_b, the electric charge that its high input resistance flows into all is run up on capacitor C, due to phase
Anti- charge accumulated, the current potential of B points will be gradually distance from reference potential V_b；When the current potential of B points reaches
During setting value, impulse generator transmitting pulse, and trigger the electric charge on a circuit releasing capacitor C.
As for the impulse generator in the present embodiment, its design is simpler, can be easily ability
Field technique personnel are realized, therefore are no longer described in detail.
In the present embodiment, the charge integrator is having time limitation, if not new for a long time is defeated
Enter, the electric charge on capacitor C be present can miss, and original accumulation can be lost.But this should be with the work of human brain
It is similar to make mode, continuous stimulate can just produce result.
It should be noted that the neuron in the present embodiment is by charge integrator and coordinates pulse generation
The analog circuit implementation of device is imitated, and the god in class brain computing system of the prior art
Through member imitated by the implementation of digital circuit mostly, the reality of neuron in the present embodiment
Existing mode is more easy and effective.In addition, charge integrator is although known to those skilled in the art, so
And the design not necessarily those skilled in the art for imitating neuron are gone easily to think using charge integrator
Arrive.
Be described above the class brain computing system of the present embodiment (mainly includes data in normal mode of operation
Read) under implementation, it is (main to include number in programming mode that the class brain computing system will be introduced further below
According to write-in) under implementation.
In the present embodiment, the class brain computing system can also include writing drive circuit, described to write driving electricity
First output end on road is connected with the impulse generator to each memory MTJ output end, described to write
Second output end of drive circuit is connected with the charge integrator to each memory MTJ input；
The drive circuit of writing is in pass-through state in the normal mode of operation, the pulse hair under programming mode
Raw device and charge integrator are in high-impedance state, and the drive circuit of writing is used to change under the programming mode
Become or maintain the state of the memory MTJ；Put on the memory MTJ and first gating device
Voltage according to the reference potential, the program voltage of the MTJ cynapses and first gating device
Forward voltage drop or reverse turn-on voltages determine.
As it was previously stated, when remembering MTJ and being in same state with reference to MTJ, whole MTJ cynapses
There is no net charge output, and only just have net electricity in the state of memory MTJ is in and referred to MTJ differences
Lotus exports.Therefore, if desired control MTJ cynapses whether can output charge, then need to change memory MTJ
It is the output end that this can be in impulse generator to each memory MTJ relative to the state with reference to MTJ
Drive circuit is write described in being set with charge integrator to each memory MTJ input, in normal work
Drive circuit is write under pattern and is in pass-through state, under programming mode, impulse generator and charge integrator
In high-impedance state.
It should be noted that described " high-impedance state (or being high-impedance state) " well known in the art normal
To know, it is term common in a digital circuit, refers to a kind of output state of tri-state gate circuit,
Neither high level is nor low level.When impulse generator and charge integrator are in high-impedance state, no
The voltage write drive circuit and applied for remembering MTJ both ends can be influenceed, that is, does not interfere with programming
Accuracy.
Actual when implementing, the drive circuit of writing can be by its first output end by the impulse generator
Output end be placed in current potential " V_b+V_write+ gate diodes forward voltage drop ", pass through its second output end
The input of charge integrator is placed in reference potential V_b, so can be arranged to one with a memory MTJ
Individual state；Similarly, the drive circuit of writing can also be by its first output end by the impulse generator
Output end be placed in reference potential V_b, and the input of charge integrator is put by its second output end
In current potential " V_b+V_write+ gate diodes reverse turn-on voltages ", such can will remember MTJ
It is placed in opposite state；Wherein, V_write is the program voltage for MTJ cynapses.
In the embodiment of the present invention, also a kind of computing chip for copying human brain principle is devised using MTJ technology
(industry is commonly referred to as class brain chip), among above-mentioned class brain computing system is integrated in into the computing chip,
One of its most important application is artificial intelligence field.
A kind of common embodiment of the computing chip is described as follows：
Above-mentioned class brain computing system is integrated in semiconductor chip, the hierarchy in the form of hierarchy
By more than one layer of neural elementary charge output layer and more than one layer of neural elementary charge input layer successively alternating layer
Connect and form, the neuron of the neural elementary charge output layer including more than one output charge and its corresponding
One group of output line, the neuron of the neural elementary charge input layer including more than one input charge and its right
Answer one group of input line；The output line of adjacent two layers is with input line in arrangement form array in length and breadth, adjacent two layers
Output line and input line between each crossover location be provided with a MTJ cynapse, each output charge
Neuron output line and each input charge neuron each self-contained two wires of input line,
The wire that wire, the input line that output line includes include has connected the memory MTJ and institute
State the first gating device and form a current path, another wire, the input line that output line includes include
Another wire connected and described form another electric current road with reference to MTJ and second gating device
Footpath.
It is pointed out that it will be appreciated by those skilled in the art that " hierarchy " of the embodiment of the present invention
In " layer " be neutral net a concept, in particular to network structure in layer, rather than three
Layer in dimension space.
Class brain computing system is integrated in array layout such as Fig. 7 institutes of semiconductor chip in the form of hierarchy
Show.N-th layer neuron (being assumed to be neural elementary charge output layer) and its output line are shown in Fig. 7,
Such as neuron 1, neuron 1, neuron 1, neuron 1 etc., neural elementary charge is defeated
Each neuron for going out layer is all connected with the output line (each in Fig. 7 being made up of two wires
Line actually includes two wires), the output line that each neuron is connected in n-th layer neuron forms one
Group output line；Also show in Fig. 7 N+1 layers neuron (being assumed to be neural elementary charge input layer) and
Its input line, such as neuron 21, neuron 22, neuron 23, neuron 24 etc., god
Each neuron through elementary charge input layer equally connects an input line being made up of two wires, the
The input line that each neuron is connected in N+1 layer neurons forms one group of input line；N-th layer neuron
Output line and N+1 layer neurons input line can be arranged in array as shown in Figure 7, and two groups of lines divide two layers
It is laid out in length and breadth, a MTJ cynapse (as shown in Black oval in Fig. 7) is disposed on each crosspoint,
Each MTJ cynapse comprises at least a pair of MTJ being made up of two MTJ, is memory MTJ respectively
With with reference to MTJ, wherein memory MTJ and its corresponding gate diode are connected with two wires respectively, join
MTJ and its corresponding gate diode is examined also to be connected with two wires respectively；For example：For N
Set by a certain article of output line of layer neuron and the crossover location of a certain article of input line of N+1 layer neurons
The MTJ cynapses put, the wire that a wire that the output line includes, the input line include connect
The memory MTJ and its corresponding gate diode form a current path, and the output line includes another
Another wire that a piece wire, the input line include has connected the reference MTJ and its corresponding gating
Diode forms another current path.
It should be noted that connection memory MTJ gate diode and connection refer to MTJ gating two
Pole pipe, it is that when forcing the electric current to be flowed in the network that class brain computing system is formed, can only select that it, which is acted on,
Simplest route, i.e., it can only turn round once, it is impossible to repeatedly turn round, to ensure the normal operation of system.
It is pointed out that above-mentioned array layout can also be with reference to IBM TrueNorth chips in the prior art
Design, it is otherwise varied, memory is employed in the array layout of the computing chip of the embodiment of the present invention
MTJ and the cynapse between neuron is imitated with reference to the structure that MTJ is formed, and unconventional SRAM institutes
The cynapse of composition；In addition, neuron is with charge integrator and coordinates the analog circuit of impulse generator to realize
Mode is also different from the prior art by the implementation of digital circuit.
It is (such as of the prior art relative to the cynapse imitated using traditional SRAM in class brain computing system
IBM TrueNorth chips), the computing chip of the class brain computing system is integrated in the embodiment of the present invention
Advantage embodies as follows：
Traditional SRAM is substituted effectively to reduce the area shared by cynapse as cynapse by using MTJ,
So same computing chip can carry out more massive calculating；SRAM used in traditional cynapse exists
There can be leaky when not in use, this electric leakage is especially serious when chip-scale is larger, and MTJ cynapses
Power-off control can be carried out when not in use, so as to reduce power consumption；MTJ retains original when power is off
Information, it is not necessary to using another chip-stored programming information, also without loading content during startup,
Both design had been simplified, has improved the speed of system startup again.
When actually implementing, each MTJ cynapses typically have different resistance in the state of difference, because
This electric current exported to other each neurons or outside output point will be not quite similar.It should be noted that
What the chip due to being integrated with the class brain computing system in the present embodiment was carried out is that simulation calculates, simulation meter
Calculation has error, there is the error for carrying out self noise, has caused by being slightly different due to each MTJ resistance
Error, as being also the simulation calculating carried out in human brain.Intelligent algorithm has certain tolerance to error,
On the premise of intelligent algorithm acceptable error, being achieved using the ball bearing made of the present embodiment offer has been
It is complete possible.
Although the present invention is disclosed as above with preferred embodiment, it is not for limiting the present invention, appointing
What those skilled in the art without departing from the spirit and scope of the present invention, may be by the disclosure above
Methods and technical content makes possible variation and modification to technical solution of the present invention, therefore, every not take off
From the content of technical solution of the present invention, the technical spirit according to the present invention is made any to above example
Simple modification, equivalent variation and modification, belong to the protection domain of technical solution of the present invention.
Claims (9)
1. the cynapse of a species brain computing system, it is characterised in that the cynapse is that the MTJ comprising MTJ dashes forward
Touch, the MTJ cynapses include memory MTJ and with reference to MTJ；The output end connection of the MTJ cynapses
The neuron of input charge into the class brain computing system, the input of the MTJ cynapses are connected to institute
State the neuron of output charge in class brain computing system；The class brain computing system is in normal mode of operation
When, the output end of the MTJ cynapses is placed in reference potential, and the memory MTJ, which is suitable to receive, comes from institute
The first pulse of the input of MTJ cynapses is stated, it is described to be dashed forward with reference to MTJ suitable for receiving from the MTJ
Second pulse of tactile input, first pulse are launched simultaneously with the second pulse, and shape is identical and accords with
Number on the contrary, the voltage difference of first pulse and the second pulse by the reference potential and to the MTJ
The reading voltage of cynapse is determined；The MTJ cynapses also include the first choosing being connected with the memory MTJ
Logical device and with second gating device being connected with reference to MTJ, first gating device and second
Gating device is respectively arranged between the neuron of the output charge and the neuron of the input charge
On different current paths, and both water conservancy diversion are in opposite direction.
2. the cynapse of class brain computing system according to claim 1, it is characterised in that first gating
Device and the second gating device are gate diode.
3. the cynapse of class brain computing system according to claim 1, it is characterised in that the class brain calculates
MTJ cynapses in system are included containing MTJ and binary states MTJ cynapse with reference to MTJ of a memory.
4. the cynapse of class brain computing system according to claim 3, it is characterised in that the class brain calculates
MTJ cynapses in system also include being dashed forward by the four state MTJ that two binary states MTJ cynapses constructions form
Touch, the pulse that the input of one of binary states MTJ cynapses is put in the four states MTJ cynapses is different
In the pulse for the input for putting on the MTJ cynapses of another binary states.
A 5. species brain computing system, it is characterised in that including：More than one neuron and more than one such as power
Profit requires the cynapse described in 1 to 4 any one, is got up between neuron by the MTJ Synaptic junctions；
All MTJ cynapses it is each it is self-contained with reference to MTJ all in the state of same agreement.
6. class brain computing system according to claim 5, it is characterised in that the neuron includes electric charge
Integrator and impulse generator；It is each from outside or other neurons that the charge integrator is suitable to collection
The electric charge of input point input, and the charge accumulated of input is got up, when charge accumulated reaches setting value,
Trigger MTJ cynapse of the impulse generator to each output and launch first pulse and the second pulse,
The electric charge accumulated is zeroed simultaneously；The output end of the MTJ cynapses is connected to the neuron of input charge
Comprising charge integrator, the neuron that the inputs of the MTJ cynapses is connected to output charge wrapped
The impulse generator contained.
7. class brain computing system according to claim 6, it is characterised in that the charge integrator includes
Operational amplifier and capacitor；The reference potential is placed in the first input end of the operational amplifier, institute
The second input for stating operational amplifier connects the output end of the MTJ cynapses, the operational amplifier
Output end connects the input of the impulse generator, and the both ends of the capacitor are put with the computing respectively
Second input of big device is connected with output end.
8. class brain computing system according to claim 6, it is characterised in that also include writing drive circuit,
Output end of first output end for writing drive circuit with the impulse generator to each memory MTJ
It is connected, second output end for writing drive circuit is with the charge integrator to each memory MTJ's
Input is connected；The drive circuit of writing is in pass-through state in the normal mode of operation, in programming mode
Under the impulse generator and charge integrator be in high-impedance state, the drive circuit of writing is used for described
Change or maintain the state of the memory MTJ under programming mode；Put on the memory MTJ and described
The voltage of first gating device is according to the reference potential, the program voltage of the MTJ cynapses and described
The forward voltage drop or reverse turn-on voltages of first gating device determine.
9. class brain computing system according to claim 5, it is characterised in that the class brain computing system with
The form of hierarchy is integrated in semiconductor chip, and the hierarchy is by more than one layer of neural elementary charge
Output layer connects with more than one layer of neural elementary charge input layer successively alternating layer and formed, the neural elementary charge
Output layer includes the neuron of more than one output charge and its corresponding one group of output line, the neuron
Electric charge input layer includes the neuron of more than one input charge and its corresponding one group of input line；Adjacent two layers
Output line and input line in arrangement form array in length and breadth, between the output line and input line of adjacent two layers
Each crossover location is provided with a MTJ cynapse, the output line of the neuron of each output charge and each
Each self-contained two wires of the input line of the neuron of input charge, a wire that output line includes,
The wire that input line includes has connected the memory MTJ and first gating device forms one
Current path, another wire that another wire, the input line that output line includes include have connected described
Another current path is formed with reference to MTJ and second gating device.
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